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@@ -37,16 +37,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
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#define SMM_CODE_ACCESS_CHK_BIT BIT58
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-//
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-// Set default value to assume SMRR is not supported
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-//
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-BOOLEAN mSmrrSupported = FALSE;
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-
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-//
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-// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
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-//
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-BOOLEAN mSmmFeatureControlSupported = FALSE;
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-
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//
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// Set default value to assume IA-32 Architectural MSRs are used
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//
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@@ -98,7 +88,7 @@ CpuFeaturesLibInitialization (
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// Check MTRR_CAP MSR bit 11 for SMRR support
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
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- mSmrrSupported = TRUE;
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+ ASSERT (FeaturePcdGet (PcdSmrrEnable));
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}
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}
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@@ -111,7 +101,7 @@ CpuFeaturesLibInitialization (
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//
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if (FamilyId == 0x06) {
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if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {
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- mSmrrSupported = FALSE;
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+ ASSERT (!FeaturePcdGet (PcdSmrrEnable));
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}
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}
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@@ -216,13 +206,12 @@ SmmCpuFeaturesInitializeProcessor (
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// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
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// is set, then the MSR is locked and can not be modified.
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//
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- if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
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+ if ((FeaturePcdGet (PcdSmrrEnable)) && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
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FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
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if ((FeatureControl & BIT3) == 0) {
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+ ASSERT ((FeatureControl & BIT0) == 0);
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if ((FeatureControl & BIT0) == 0) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
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- } else {
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- mSmrrSupported = FALSE;
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}
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}
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}
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@@ -234,7 +223,7 @@ SmmCpuFeaturesInitializeProcessor (
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// from SMRAM region. If SMRR is enabled here, then the SMRAM region
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// is protected and the normal mode code execution will fail.
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//
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- if (mSmrrSupported) {
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+ if (FeaturePcdGet (PcdSmrrEnable)) {
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//
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// SMRR size cannot be less than 4-KBytes
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// SMRR size must be of length 2^n
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@@ -287,7 +276,7 @@ SmmCpuFeaturesInitializeProcessor (
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// Do not access this MSR unless the CPU supports the SmmRegFeatureControl
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {
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- mSmmFeatureControlSupported = TRUE;
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+ ASSERT (FeaturePcdGet (PcdSmmFeatureControlEnable));
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}
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}
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}
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@@ -383,7 +372,7 @@ SmmCpuFeaturesDisableSmrr (
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VOID
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)
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{
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- if (mSmrrSupported && mNeedConfigureMtrrs) {
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+ if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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}
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@@ -398,7 +387,7 @@ SmmCpuFeaturesReenableSmrr (
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VOID
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)
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{
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- if (mSmrrSupported && mNeedConfigureMtrrs) {
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+ if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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}
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@@ -419,7 +408,7 @@ SmmCpuFeaturesRendezvousEntry (
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//
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// If SMRR is supported and this is the first normal SMI, then enable SMRR
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//
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- if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {
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+ if (FeaturePcdGet (PcdSmrrEnable) && !mSmrrEnabled[CpuIndex]) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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mSmrrEnabled[CpuIndex] = TRUE;
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}
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@@ -460,7 +449,7 @@ SmmCpuFeaturesIsSmmRegisterSupported (
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IN SMM_REG_NAME RegName
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)
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{
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- if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
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+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
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return TRUE;
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}
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@@ -486,7 +475,7 @@ SmmCpuFeaturesGetSmmRegister (
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IN SMM_REG_NAME RegName
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)
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{
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- if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
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+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
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return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
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}
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@@ -512,7 +501,7 @@ SmmCpuFeaturesSetSmmRegister (
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IN UINT64 Value
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)
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{
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- if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
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+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
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}
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}
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