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@@ -29,11 +29,12 @@ typedef enum {
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} IA32_PAGE_LEVEL;
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typedef struct {
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- UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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- UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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- UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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- UINT64 Reserved : 58;
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- UINT64 Nx : 1; // No Execute bit
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+ UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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+ UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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+ UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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+ UINT32 Reserved0 : 29;
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+ UINT32 Reserved1 : 31;
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+ UINT32 Nx : 1; // No Execute bit
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} IA32_PAGE_COMMON_ENTRY;
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///
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@@ -41,20 +42,20 @@ typedef struct {
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///
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typedef union {
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struct {
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- UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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- UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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- UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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- UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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- UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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- UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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- UINT64 Available0 : 1; // Ignored
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- UINT64 MustBeZero : 1; // Must Be Zero
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-
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- UINT64 Available2 : 4; // Ignored
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-
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- UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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- UINT64 Available3 : 11; // Ignored
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- UINT64 Nx : 1; // No Execute bit
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+ UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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+ UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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+ UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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+ UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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+ UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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+ UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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+ UINT32 Available0 : 1; // Ignored
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+ UINT32 MustBeZero : 1; // Must Be Zero
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+ UINT32 Available2 : 4; // Ignored
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+ UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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+
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+ UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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+ UINT32 Available3 : 11; // Ignored
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+ UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_NON_LEAF_ENTRY;
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@@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
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///
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typedef union {
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struct {
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- UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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- UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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- UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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- UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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- UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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- UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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- UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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- UINT64 MustBeOne : 1; // Page Size. Must Be One
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-
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- UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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- UINT64 Available1 : 3; // Ignored
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- UINT64 Pat : 1; // PAT
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-
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- UINT64 PageTableBaseAddress : 39; // Page Table Base Address
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- UINT64 Available3 : 7; // Ignored
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- UINT64 ProtectionKey : 4; // Protection key
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- UINT64 Nx : 1; // No Execute bit
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+ UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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+ UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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+ UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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+ UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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+ UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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+ UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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+ UINT32 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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+ UINT32 MustBeOne : 1; // Page Size. Must Be One
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+ UINT32 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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+ UINT32 Available1 : 3; // Ignored
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+ UINT32 Pat : 1; // PAT
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+ UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Low
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+
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+ UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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+ UINT32 Available3 : 7; // Ignored
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+ UINT32 ProtectionKey : 4; // Protection key
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+ UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;
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@@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
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///
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typedef union {
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struct {
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- UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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- UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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- UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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- UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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- UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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- UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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- UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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- UINT64 Pat : 1; // PAT
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-
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- UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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- UINT64 Available1 : 3; // Ignored
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-
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- UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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- UINT64 Available3 : 7; // Ignored
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- UINT64 ProtectionKey : 4; // Protection key
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- UINT64 Nx : 1; // No Execute bit
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+ UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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+ UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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+ UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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+ UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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+ UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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+ UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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+ UINT32 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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+ UINT32 Pat : 1; // PAT
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+ UINT32 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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+ UINT32 Available1 : 3; // Ignored
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+ UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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+
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+ UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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+ UINT32 Available3 : 7; // Ignored
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+ UINT32 ProtectionKey : 4; // Protection key
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+ UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PTE_4K;
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@@ -149,16 +150,16 @@ typedef union {
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///
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typedef union {
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struct {
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- UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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- UINT64 MustBeZero : 2; // Must Be Zero
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- UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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- UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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- UINT64 MustBeZero2 : 4; // Must Be Zero
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-
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- UINT64 Available : 3; // Ignored
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-
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- UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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- UINT64 MustBeZero3 : 12; // Must Be Zero
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+ UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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+ UINT32 MustBeZero : 2; // Must Be Zero
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+ UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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+ UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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+ UINT32 MustBeZero2 : 4; // Must Be Zero
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+ UINT32 Available : 3; // Ignored
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+ UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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+
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+ UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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+ UINT32 MustBeZero3 : 12; // Must Be Zero
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} Bits;
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UINT64 Uint64;
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} IA32_PDPTE_PAE;
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