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@@ -6,7 +6,7 @@
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If a register returned is a single 32-bit value, then a data structure is
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not provided for that register.
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- Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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+ Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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@@ -1550,9 +1550,17 @@ typedef union {
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///
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UINT32 AVX512_4FMAPS:1;
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///
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- /// [Bit 25:4] Reserved.
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+ /// [Bit 14:4] Reserved.
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///
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- UINT32 Reserved2:22;
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+ UINT32 Reserved4:11;
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+ ///
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+ /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
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+ ///
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+ UINT32 Hybrid:1;
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+ ///
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+ /// [Bit 25:16] Reserved.
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+ ///
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+ UINT32 Reserved5:10;
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///
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/// [Bit 26] Enumerates support for indirect branch restricted speculation
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/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
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