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- ## @file
- #
- # @copyright
- # Copyright 2015 - 2021 Intel Corporation. <BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- ##
- [Defines]
- DEC_SPECIFICATION = 0x00010005
- PACKAGE_NAME = CpRcPkg
- PACKAGE_GUID = 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408
- PACKAGE_VERSION = 0.1
- [Includes]
- Include
- #
- # Over time these will be removed as definitions are moved
- # out of BaseMemoryCoreLib and into the standard Include directory
- #
- Library/BaseMemoryCoreLib/Core
- Library/BaseMemoryCoreLib/Core/Include
- Library/BaseMemoryCoreLib/Platform
- [Guids]
- ## Include/Guid/MemBootHealthGuid.h
- gMemBootHealthGuid = { 0xACD56900, 0xDEFC, 0x4127, { 0xDE, 0x12, 0x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F }}
- ## Include/Guid/CpRcPkgTokenSpace.h
- gEfiCpRcPkgTokenSpaceGuid = { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
- gSystemInfoVarHobGuid = { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
- gReferenceCodePolicyHobGuid = { 0x5AC718A1, 0xFBA0, 0x4F5F, { 0xAF, 0x9F, 0x20, 0x4A, 0x1A, 0xF6, 0x15, 0x32 }}
- ## Include/SystemInfoVar.h
- gEfiSysInfoVarNvramDataGuid = { 0x0E5AD476, 0xE47D, 0x4E50, { 0xAE, 0x9D, 0x38, 0xDF, 0xE2, 0x71, 0x67, 0x96 }}
- gStatusCodeDataTypeExDebugGuid = { 0x7859daa2, 0x926e, 0x4b01, { 0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }}
- gDebugDataGuid = { 0xED585D92, 0x8F3D, 0x43E3, { 0xB7, 0x8D, 0xD1, 0xB8, 0xF9, 0x05, 0x7F, 0xCE }}
- gPerfStatsGuid = { 0x83f6e752, 0xd9ae, 0x48eb, { 0xab, 0xd4, 0xb5, 0xe9, 0x84, 0x63, 0x60, 0x68 }}
- ## Include/Guid/RcSimGlobalDataHob.h
- gEfiRcSimGlobalDataHobGuid = { 0x25a4a61a, 0x5a6d, 0x429e, { 0x99, 0x2b, 0xbe, 0xeb, 0x8a, 0xbd, 0xd8, 0x40 }}
- # OnBoardSPD library
- gOnBoardSpdTableGuid = { 0xe15c5c55, 0x09ec, 0x4a95, { 0xa3, 0x5a, 0x1e, 0x72, 0xa3, 0x2c, 0x4f, 0x0f }}
- gSpdTableHobGuid = { 0x429E8B23, 0xB8B1, 0x4208, { 0x96, 0xAA, 0x51, 0x5A, 0x11, 0x62, 0x80, 0x40 }}
- ## Include/Guid/FspInfo.h
- gFspInfoHobGuid = { 0x4a7bd124, 0xcbea, 0x4b3b, { 0x95, 0x86, 0x11, 0xe6, 0x68, 0xe9, 0xbc, 0xdd }}
- gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}
- gMemRasS3DataVariableGuid = { 0xe626f9ca, 0xfd71, 0x458c, { 0xb9, 0x26, 0xbf, 0x40, 0x80, 0x62, 0x42, 0xa9 }}
- gStaticPointerSmmSizeGuid = { 0xd0ee5959, 0xbae6, 0x4709, { 0xaa, 0x2b, 0x55, 0xbe, 0x90, 0x57, 0x65, 0x6d }}
- # Enhanced Warning Log (EWL) BDAT schema Guid
- gEwlBdatSchemaGuid = { 0xbffe532f, 0xca3b, 0x416c, { 0xa0, 0xf6, 0xff, 0xe4, 0xe7, 0x1e, 0x3a, 0xd }}
- # Memory SPD Raw data BDAT schema Guid
- gSpdBdatSchemaGuid = { 0x1b19f809, 0x1d91, 0x4f00, { 0xa3, 0xf3, 0x7a, 0x67, 0x66, 0x6, 0xd3, 0xb1 }}
- # Memory SPD Raw data version ID Guid
- gSpdVersion1Guid = { 0x46f60b90, 0x9c94, 0x43ca, { 0xa7, 0x7c, 0x9, 0xb8, 0x48, 0x99, 0x93, 0x48 }}
- # Memory SPD data variable
- gSpdVariableGuid = { 0x1f5d405b, 0x9b66, 0x4336, { 0x85, 0xe9, 0x52, 0xb4, 0xee, 0x6a, 0xca, 0x51 }}
- # Memory training data BDAT schema Guid
- gMemTrainingDataBdatSchemaGuid = { 0x27aab341, 0x5ef9, 0x4383, { 0xae, 0x4d, 0x9, 0x12, 0x41, 0xb2, 0xfa, 0xc }}
- # Memory training data version ID Guid
- gMemTrainingDataVersion1Guid = { 0x37e839b5, 0x4357, 0x47d9, { 0xa1, 0x3f, 0x6f, 0x9a, 0x43, 0x33, 0xfb, 0xc4 }}
- # Memory training data HOB Guid
- gMemTrainingDataHobGuid = { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
- #
- # Guid for the BiosId file, used only for RcSim
- #
- gRcSimBiosIdFileGuid = { 0xf0c51ad5, 0x44f0, 0x4622, { 0x95, 0x15, 0xe2, 0x7, 0x71, 0xf0, 0xe0, 0xf2 }}
- gSystemTopologyGuid = { 0x743e5992, 0xf2a0, 0x4c9f, { 0xa5, 0xf5, 0x3b, 0x24, 0xad, 0xe8, 0x7f, 0x4d }}
- [Protocols]
- gEfiCpuCsrAccessGuid = { 0x0067835f, 0x9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 }}
- [PPIs]
- ## Include/Ppi/MemorySetupPolicyPpi.h
- gMemoryPolicyPpiGuid = { 0x731b6dbc, 0x18ac, 0x4cc3, { 0x9e, 0xe2, 0x9e, 0x5f, 0x33, 0x39, 0x68, 0x81 }}
- [PcdsFeatureFlag]
- ## Indicate whether USRA can support S3
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012
- ## Use this feature PCD to support Single PCIe segment with static MMCFG Base
- gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014
- ## enable/disable USRA trace.
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016
- ## enable/disable Quiesce feature.
- gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017
- ## Enable / disable CTE build feature.
- gEfiCpRcPkgTokenSpaceGuid.PcdCteBuild|FALSE|BOOLEAN|0x0000001C
- ## Enable / disable COSIM build feature.
- gEfiCpRcPkgTokenSpaceGuid.PcdCosimBuild|FALSE|BOOLEAN|0x0000001D
- ## Enable / disable DDRT2 buffer build
- gEfiCpRcPkgTokenSpaceGuid.PcdDdrt2BufferlessBuild|FALSE|BOOLEAN|0x0000004F
- # Backside Rank Margin Tool
- gEfiCpRcPkgTokenSpaceGuid.EnableBacksideRmt|FALSE|BOOLEAN|0x0000001F
- # Backside Command Rank Margin Tool
- gEfiCpRcPkgTokenSpaceGuid.EnableBacksideCmdRmt|FALSE|BOOLEAN|0x00000030
- # RMT Pattern Length
- gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthCmd|32767|UINT32|0x00000031
- gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthExtCmdCtlVref|32767|UINT32|0x00000032
- gEfiCpRcPkgTokenSpaceGuid.PcdEnableNgnBcomMargining|FALSE|BOOLEAN|0x00000033
- #Enable per bit margining
- gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|TRUE|BOOLEAN|0x00000034
- ## Enable / disable MRS STACKING in the CPGC
- gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdr|FALSE|BOOLEAN|0x00000037
- gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdrt|FALSE|BOOLEAN|0x00000038
- gEfiCpRcPkgTokenSpaceGuid.MrsStackingNvdimm|FALSE|BOOLEAN|0x00000039
- # Use this PCD to control if separate CWL_adj calculation for 14nm and 10nm
- gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|FALSE|BOOLEAN|0x0000003B
- ## Enable / disable USRA register filter. For Sim and SMM.
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterFilterEnable|TRUE|BOOLEAN|0x0000002D
- ## Enable / disable USRA register log.
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterLogEnable|TRUE|BOOLEAN|0x0000002E
- ## Enable / disable override of debug levels during MRC call table execution
- gEfiCpRcPkgTokenSpaceGuid.PcdDebugLevelsOverride|TRUE|BOOLEAN|0x00000050
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved1|TRUE|BOOLEAN|0x00000051
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved2|FALSE|BOOLEAN|0x0000011c
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved3|FALSE|BOOLEAN|0x0000011d
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved4|FALSE|BOOLEAN|0x0000011e
- gEfiCpRcPkgTokenSpaceGuid.Reserved15|FALSE|BOOLEAN|0x00000052
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved5|TRUE|BOOLEAN|0x00000053
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved6|FALSE|BOOLEAN|0x00000054
- #Enable\Disable Mem Boot Health Feature
- gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|TRUE|BOOLEAN|0x00000055
- #Control Opportunistic Self Refresh(OSR) feature.
- #PCD hides\shows the OSR Setup knob based on setting
- #default disabled
- gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshSupported|FALSE|BOOLEAN|0x00000115
- gEfiCpRcPkgTokenSpaceGuid.PcdDprSizeFeatureSupport|FALSE|BOOLEAN|0x00000056
- #SecurityPolicy
- gSecurityPolicyDataGuid.PcdCoSignEnable|FALSE|BOOLEAN|0xE000002F
- [PcdsFixedAtBuild]
- #
- # MRC build time configuration PCD's
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE|BOOLEAN|0x00000100
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|FALSE|BOOLEAN|0x00000101
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE|BOOLEAN|0x00000102
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE|BOOLEAN|0x00000103
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE|BOOLEAN|0x00000104
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE|BOOLEAN|0x00000105
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE|BOOLEAN|0x00000106
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE|BOOLEAN|0x00000107
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE|BOOLEAN|0x00000113
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSpdDecodeLibTrace|FALSE|BOOLEAN|0x00000114
- #PCD controls Setup default for OSR
- #Default disabled
- gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshDefault|0|UINT8|0x00000116
- #PCD controls Setup default for DDRT Self Refresh
- #Default disabled
- gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSrefDefault|0|UINT8|0x00000117
- #
- # Dimm support
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE|BOOLEAN|0x00000108
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE|BOOLEAN|0x00000109
- #
- # SVID support
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidSupported|TRUE|BOOLEAN|0x8000010A
- #
- # Miscellaneous MRC options
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE|BOOLEAN|0x00000110
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE|BOOLEAN|0x00000112
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|FALSE|BOOLEAN|0x00000111
- ## Indicates the size of each PCIE segment
- gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010
- gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013
- ## Indicates the max nested level
- gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018
- ## Maximum number of sockets supported for this firmware build.
- # This PCD should be used sparingly. Dynamic allocation of data and
- # dynamic control flows are preferred over using this PCD for static
- # data allocation and control.
- gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019
- gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|0x22|UINT32|0x0000001A
- gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|0x2|UINT32|0x0000001B
- gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutBaseClock|0x0000001C|UINT32|0x00000022
- gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutThreshold|0x0000000C|UINT32|0x00000023
- gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutCreditLimit|0x00000020|UINT32|0x00000024
- ## Enable / Disable USRA trace configuration by IO port
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortEnable|FALSE|BOOLEAN|0x00000025
- ## Set the specific IO port for trace configuration low byte
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortLow|0x81|UINT8|0x00000026
- ## Set the specific IO port for trace configuration high byte
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortHigh|0x82|UINT8|0x00000027
- ## PcdUsraTraceConfigurationValue is used to control the USRA trace behavior, and the defination shown as below.
- # When PcdUsraTraceConfigurationPortEnable is TRUE, this configuration value can be overridden by configuration IO port.
- # When PcdUsraTraceConfigurationPortEnable is FALSE, the value can be overridden via the interface SetUsraTraceConfiguration().
- # Bit 0 - Bit 3 : USRA trace Signature,it should always be 0101B.
- # Bit 4: Set indicates USRA trace message's format is long mode.
- # Bit 5: Set indicates get address operation is traced.
- # Bit 6: Set indicates modify operation is traced.
- # Bit 7: Set indicates write operation is traced.
- # Bit 8: Set indicates read operation is traced.
- # Bit 9: Set indicates PCIE access is traced.
- # Bit 10: Set indicates CSR access is traced.
- # Bit 11 - Bit14: Reserved for future uses.
- # Bit 15: Set indicates dumps the content of CpuCsrAccessVar before dumping the register access trace information.
- # @Prompt USRA trace configuration settings.
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationValue|0x07F5|UINT16|0x00000028
- ## Default value to USRA trace start at earlier stage, this value can be overridden by the interface UsraTraceStart()
- ## and UsraTraceEnd().
- gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceStartAtEarlierStage|FALSE|BOOLEAN|0x00000029
- ## Indicates whether it needs to clear temp bus assignment in PCIE common init library
- gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE|BOOLEAN|0x0000002A
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion|{0, 0, 0, 0}|RC_VERSION|0x00000015 {
- <HeaderFiles>
- RcVersion.h
- <Packages>
- WhitleySiliconPkg/CpRcPkg.dec
- }
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A
- #
- # MRC DEFAULT SETTINGS
- #
- # PCD NAME | VALUE| TYPE| PCD NUM.
- ## Default Enable / Disable Legacy RMT Feature
- gEfiCpRcPkgTokenSpaceGuid.PcdLegacyRmtEnable | 1| UINT8|0x0000001E
- #
- # Enforce memory POR configurations
- # 0 (ENFORCE_POR_EN) - Enforce memory POR
- # 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal
- # 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | 0| UINT8|0x00000040
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE|BOOLEAN|0x0000003A
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | FALSE|BOOLEAN|0x00000060
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastColdBootDefault | TRUE|BOOLEAN|0x00000061
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault | TRUE|BOOLEAN|0x00000062
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault | 0xFF| UINT8|0x00000063
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault | 0xFF| UINT8|0x00000064
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault | 0x0| UINT8|0x00000065
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | 0x2| UINT8|0x00000066
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | FALSE|BOOLEAN|0x00000067
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | 0x6| UINT8|0x00000068
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOOLEAN|0x00000069
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | TRUE| UINT8|0x0000006A
- #Setup string for Mem boot health check
- gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHealthConfig"| VOID*|0x00000070
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | FALSE|BOOLEAN|0x00000071
- gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | FALSE|BOOLEAN|0x00000072
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | 1| UINT8|0x00000073
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | 1| UINT8|0x00000074
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2| UINT8|0x0000011F
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE|BOOLEAN|0x00000120
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | FALSE|BOOLEAN|0x00000075
- #option to choose Mem Boot Health configuration type. 00=>Auto (Use defaults), 01=>Manual (Override defaults with setup option), 02=>Disable (Disable feature)
- gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | 00| UINT8|0x00000076
- # The below values are setup\standard\build defaults. Can be overridden in platform specific dsc
- ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS STARTS#####################################
- #Left edge offset for TxDqDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayLeftEdge | 5| UINT8|0x00000077
- #Right edge offset for TxDqDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayRightEdge | 5| UINT8|0x00000078
- #Left edge offset for TxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefLeftEdge | 5| UINT8|0x00000079
- #Right edge offset for TxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefRightEdge | 5| UINT8|0x0000007A
- #Left edge offset for RxDqsDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayLeftEdge | 5| UINT8|0x0000007B
- #Right edge offset for RxDqsDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayRightEdge | 5| UINT8|0x0000007C
- #Left edge offset for RxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefLeftEdge | 5| UINT8|0x0000007D
- #Right edge offset for RxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefRightEdge | 5| UINT8|0x0000007E
- ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS ENDS#######################################
- ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS STARTS####################################
- #Left edge offset for TxDqDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayLeftEdge | 2| UINT8|0x0000007F
- #Right edge offset for TxDqDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayRightEdge | 2| UINT8|0x00000080
- #Left edge offset for TxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefLeftEdge | 2| UINT8|0x00000081
- #Right edge offset for TxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefRightEdge | 2| UINT8|0x00000082
- #Left edge offset for RxDqsDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayLeftEdge | 2| UINT8|0x00000083
- #Right edge offset for RxDqsDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayRightEdge | 2| UINT8|0x00000084
- #Left edge offset for RxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefLeftEdge | 2| UINT8|0x00000085
- #Right edge offset for RxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefRightEdge | 2| UINT8|0x00000086
- ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS ENDS######################################
- # Option to enable/disable RMT minimum margin test
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumMarginCheckDefault | 1| UINT8|0x00000124
- # Define the default minimum margin thresholds for RMT margin check
- # The minimum margin thresholds are applied to both margin directions.
- # Rx timing: RxDqsDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxTimingMargin | 3| UINT8|0x00000125
- # Rx voltage: RxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxVoltageMargin | 3| UINT8|0x00000126
- # Tx timing: TxDqDelay
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxTimingMargin | 3| UINT8|0x00000127
- # Tx voltage: TxVref
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxVoltageMargin | 3| UINT8|0x00000128
- # Cmd timing: CmdAll
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdTimingMargin | 5| UINT8|0x00000129
- # Cmd voltage: CmdVref
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdVoltageMargin | 5| UINT8|0x00000130
- # Ctl timing: CtlAll
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | 5| UINT8|0x00000131
- #MC VC0 Deadlock Breaker
- gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings | TRUE| BOOLEAN|0x00000132
- gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer | 18| UINT8|0x00000133
- gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold | 4| UINT8|0x00000134
- #Reset on Critical Margin failure to perform Memory Training from scratch
- gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | 1| UINT8|0x00000087
- #Enable Debug message inside MarginTest
- #BIT0 for API Debug messages
- #BIT1 for Log messages
- #BIT2 for Error messages
- #BIT3 for Function trace messages
- gEfiCpRcPkgTokenSpaceGuid.PcdEvDebugMsg | 0| UINT8|0x00000088
- #Non-Configurable...Number of Signals to test.
- gEfiCpRcPkgTokenSpaceGuid.PcdMemBootSignalsToTest | 4| UINT8|0x00000089
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved14| FALSE|BOOLEAN|0x0000008B
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations | FALSE|BOOLEAN|0x0000008C
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt| FALSE|BOOLEAN|0x0000008D
- #
- # Default SMBUS Speed - see SMB_CLOCK_FREQUENCY
- # 0 - SMB_CLK_100K - 100 Khz
- # 1 - SMB_CLK_400K - 400 Khz
- # 2 - SMB_CLK_700K - 700 Khz
- # 3 - SMB_CLK_1M - 1 Mhz
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault | 0x1| UINT8|0x0000008E
- #
- # Throttling mid on temp lo
- # 0 - Disabled
- # 1 - Enabled
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcThrottlingMidOnTempLo | 0| UINT8|0x0000008F
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault | 0x1| UINT8|0x00000090
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcCtleTrainingEnable | TRUE|BOOLEAN|0x00000091
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcImodeTrainingEnable | TRUE|BOOLEAN|0x00000092
- #CLTT settings
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault | 82| UINT8|0x00000093
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault | 83| UINT8|0x00000094
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault | 85| UINT8|0x00000095
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault | 83| UINT8|0x00000096
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault | 83| UINT8|0x00000097
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault | 93| UINT8|0x00000098
- gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault | 95| UINT8|0x00000099
- #
- # Allowed debug level at build time configuration
- # See RcDebugLib.h for mapping details
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugAllowedLevelsMask | 0xC7F0190B| UINT32|0x0000009A
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcTcoCompTrainingEnable | FALSE|BOOLEAN|0x0000009B
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault | 0x1| UINT8|0x0000009C
- gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault | 1| UINT8|0x0000009D
- #
- # Enforce memory population POR configurations.
- # 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce memory population POR.
- # 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported memory populations.
- # 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated memory populations.
- gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePopulationPorDefault | 1| UINT8|0x0000009E
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable | TRUE|BOOLEAN|0x0000009F
- #
- # Legacy ADR flow
- # 0 (LEGACY_ADR_MODE_DISABLE) - Pcode driven ADR flow
- # 1 (LEGACY_ADR_MODE_ENABLE) - Legacy ADR flow
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdLegacyAdrDefault | 0| UINT8|0x000000A0
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault | 0x1| UINT8|0x000000A1
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcPxcDefault | 0x1| UINT8|0x000000A2
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdjcDefault | 0x1| UINT8|0x000000A3
- #
- # Default debug level at build time configuration
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugBuildTimeDefault | 0x8000190B| UINT32|0x000000A9
- gEfiCpRcPkgTokenSpaceGuid.PcdRmtMarginInCaCsTm | TRUE|BOOLEAN|0x000000AC
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault | 0| UINT8|0x000000AE
- #Only enable for 14nm, not a feature for 10nm and above
- # 0 = Disable
- # 1 = TA Floor
- # 2 = Receive Enable Average
- # 3 = Receive Enable Average part 1 only
- gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption | 0|UINT8|0x000000A4
- #
- # Timers detinitions for priority promotions
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim | 0x100| UINT16|0x000000A5
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim | 0x100| UINT16|0x000000A6
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim | 0x100| UINT16|0x000000A7
- #Mrc memory default frequency
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdrFrequencyDefault | 0x0| UINT8|0x000000A8
- #MRC Panic Watermark default
- # 0 = Auto, 1 = High, 2 = Low
- gEfiCpRcPkgTokenSpaceGuid.PcdMrcPanicWatermarkDefault | 0x0| UINT8|0x000000AA
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved15 | 0x2| UINT8|0x000000AB
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved16 | 0x0| UINT8|0x000000AD
- # Additional Buffer Delay for Roundtrip
- gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk | 4| UINT8|0x000000AF
- # Option to enable / disable MCR Support
- gEfiCpRcPkgTokenSpaceGuid.PcdMcrSupport | FALSE|BOOLEAN|0x000000B0
- # Option to store SPD raw data to BDAT
- gEfiCpRcPkgTokenSpaceGuid.SaveSpdToBdat | TRUE|BOOLEAN|0x00000121
- # Option to store training data to BDAT
- gEfiCpRcPkgTokenSpaceGuid.SaveMrcTrainingDataToBdat | TRUE|BOOLEAN|0x00000122
- gEfiCpRcPkgTokenSpaceGuid.PcdVendorMemtestEnable | TRUE|BOOLEAN|0x00000123
- [PcdsDynamicEx]
- ## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 |
- gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011
- gEfiCpRcPkgTokenSpaceGuid.PcdSimStaticPointerTableMapPtr|{0x0}|VOID*|0x80000012
- ############### SVID Mapping ##################################
- #The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
- #Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
- #Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
- #and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
- #This information is per platform basis and can be obtained from platform schematics.
- #Need to map this token for MC to SVID based on platform.
- gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap|{0}|MEM_SVID_MAP|0x80000014 {
- <HeaderFiles>
- Library/MemVrSvidMapLib.h
- <Packages>
- WhitleySiliconPkg/WhitleySiliconPkg.dec
- }
- ############### SVID Mapping ##################################
- # IMON SVID VR address
- # Fill with IMON SVID Address
- # End the list with 0xFF (IMON_ADDR_LIST_END)
- # Assumption, all socket repeat same address
- #BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
- #BIT 0:3 => SVID ADDRESS
- gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr|{0xFF}|VCC_IMON|0x0000008A {
- <HeaderFiles>
- ImonVrSvid.h
- <Packages>
- WhitleySiliconPkg/WhitleySiliconPkg.dec
- }
- [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
- gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32|0x00000020
- gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x00000021
- gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035
- gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000036
- gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x00000118
- ## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor
- gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C
- gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D
- [PcdsDynamicEx]
- gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00000048
- gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0x00000049
- gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A
- gEfiCpRcPkgTokenSpaceGuid.PcdLtMemSize|0x00500000|UINT32|0x0000004B
- gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable|FALSE|BOOLEAN|0x0000004C
- gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size|0x0|UINT64|0x0000004D
- #
- # PCD for storing sizeof (SysHost) in PEI for later comparision in DXE
- #
- gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize|0x00000000|UINT32|0x0000004E
|