CpRcPkg.dec 30 KB

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  1. ## @file
  2. #
  3. # @copyright
  4. # Copyright 2015 - 2021 Intel Corporation. <BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. ##
  8. [Defines]
  9. DEC_SPECIFICATION = 0x00010005
  10. PACKAGE_NAME = CpRcPkg
  11. PACKAGE_GUID = 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408
  12. PACKAGE_VERSION = 0.1
  13. [Includes]
  14. Include
  15. #
  16. # Over time these will be removed as definitions are moved
  17. # out of BaseMemoryCoreLib and into the standard Include directory
  18. #
  19. Library/BaseMemoryCoreLib/Core
  20. Library/BaseMemoryCoreLib/Core/Include
  21. Library/BaseMemoryCoreLib/Platform
  22. [Guids]
  23. ## Include/Guid/MemBootHealthGuid.h
  24. gMemBootHealthGuid = { 0xACD56900, 0xDEFC, 0x4127, { 0xDE, 0x12, 0x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F }}
  25. ## Include/Guid/CpRcPkgTokenSpace.h
  26. gEfiCpRcPkgTokenSpaceGuid = { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
  27. gSystemInfoVarHobGuid = { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
  28. gReferenceCodePolicyHobGuid = { 0x5AC718A1, 0xFBA0, 0x4F5F, { 0xAF, 0x9F, 0x20, 0x4A, 0x1A, 0xF6, 0x15, 0x32 }}
  29. ## Include/SystemInfoVar.h
  30. gEfiSysInfoVarNvramDataGuid = { 0x0E5AD476, 0xE47D, 0x4E50, { 0xAE, 0x9D, 0x38, 0xDF, 0xE2, 0x71, 0x67, 0x96 }}
  31. gStatusCodeDataTypeExDebugGuid = { 0x7859daa2, 0x926e, 0x4b01, { 0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }}
  32. gDebugDataGuid = { 0xED585D92, 0x8F3D, 0x43E3, { 0xB7, 0x8D, 0xD1, 0xB8, 0xF9, 0x05, 0x7F, 0xCE }}
  33. gPerfStatsGuid = { 0x83f6e752, 0xd9ae, 0x48eb, { 0xab, 0xd4, 0xb5, 0xe9, 0x84, 0x63, 0x60, 0x68 }}
  34. ## Include/Guid/RcSimGlobalDataHob.h
  35. gEfiRcSimGlobalDataHobGuid = { 0x25a4a61a, 0x5a6d, 0x429e, { 0x99, 0x2b, 0xbe, 0xeb, 0x8a, 0xbd, 0xd8, 0x40 }}
  36. # OnBoardSPD library
  37. gOnBoardSpdTableGuid = { 0xe15c5c55, 0x09ec, 0x4a95, { 0xa3, 0x5a, 0x1e, 0x72, 0xa3, 0x2c, 0x4f, 0x0f }}
  38. gSpdTableHobGuid = { 0x429E8B23, 0xB8B1, 0x4208, { 0x96, 0xAA, 0x51, 0x5A, 0x11, 0x62, 0x80, 0x40 }}
  39. ## Include/Guid/FspInfo.h
  40. gFspInfoHobGuid = { 0x4a7bd124, 0xcbea, 0x4b3b, { 0x95, 0x86, 0x11, 0xe6, 0x68, 0xe9, 0xbc, 0xdd }}
  41. gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}
  42. gMemRasS3DataVariableGuid = { 0xe626f9ca, 0xfd71, 0x458c, { 0xb9, 0x26, 0xbf, 0x40, 0x80, 0x62, 0x42, 0xa9 }}
  43. gStaticPointerSmmSizeGuid = { 0xd0ee5959, 0xbae6, 0x4709, { 0xaa, 0x2b, 0x55, 0xbe, 0x90, 0x57, 0x65, 0x6d }}
  44. # Enhanced Warning Log (EWL) BDAT schema Guid
  45. gEwlBdatSchemaGuid = { 0xbffe532f, 0xca3b, 0x416c, { 0xa0, 0xf6, 0xff, 0xe4, 0xe7, 0x1e, 0x3a, 0xd }}
  46. # Memory SPD Raw data BDAT schema Guid
  47. gSpdBdatSchemaGuid = { 0x1b19f809, 0x1d91, 0x4f00, { 0xa3, 0xf3, 0x7a, 0x67, 0x66, 0x6, 0xd3, 0xb1 }}
  48. # Memory SPD Raw data version ID Guid
  49. gSpdVersion1Guid = { 0x46f60b90, 0x9c94, 0x43ca, { 0xa7, 0x7c, 0x9, 0xb8, 0x48, 0x99, 0x93, 0x48 }}
  50. # Memory SPD data variable
  51. gSpdVariableGuid = { 0x1f5d405b, 0x9b66, 0x4336, { 0x85, 0xe9, 0x52, 0xb4, 0xee, 0x6a, 0xca, 0x51 }}
  52. # Memory training data BDAT schema Guid
  53. gMemTrainingDataBdatSchemaGuid = { 0x27aab341, 0x5ef9, 0x4383, { 0xae, 0x4d, 0x9, 0x12, 0x41, 0xb2, 0xfa, 0xc }}
  54. # Memory training data version ID Guid
  55. gMemTrainingDataVersion1Guid = { 0x37e839b5, 0x4357, 0x47d9, { 0xa1, 0x3f, 0x6f, 0x9a, 0x43, 0x33, 0xfb, 0xc4 }}
  56. # Memory training data HOB Guid
  57. gMemTrainingDataHobGuid = { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
  58. #
  59. # Guid for the BiosId file, used only for RcSim
  60. #
  61. gRcSimBiosIdFileGuid = { 0xf0c51ad5, 0x44f0, 0x4622, { 0x95, 0x15, 0xe2, 0x7, 0x71, 0xf0, 0xe0, 0xf2 }}
  62. gSystemTopologyGuid = { 0x743e5992, 0xf2a0, 0x4c9f, { 0xa5, 0xf5, 0x3b, 0x24, 0xad, 0xe8, 0x7f, 0x4d }}
  63. [Protocols]
  64. gEfiCpuCsrAccessGuid = { 0x0067835f, 0x9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 }}
  65. [PPIs]
  66. ## Include/Ppi/MemorySetupPolicyPpi.h
  67. gMemoryPolicyPpiGuid = { 0x731b6dbc, 0x18ac, 0x4cc3, { 0x9e, 0xe2, 0x9e, 0x5f, 0x33, 0x39, 0x68, 0x81 }}
  68. [PcdsFeatureFlag]
  69. ## Indicate whether USRA can support S3
  70. gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012
  71. ## Use this feature PCD to support Single PCIe segment with static MMCFG Base
  72. gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014
  73. ## enable/disable USRA trace.
  74. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016
  75. ## enable/disable Quiesce feature.
  76. gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017
  77. ## Enable / disable CTE build feature.
  78. gEfiCpRcPkgTokenSpaceGuid.PcdCteBuild|FALSE|BOOLEAN|0x0000001C
  79. ## Enable / disable COSIM build feature.
  80. gEfiCpRcPkgTokenSpaceGuid.PcdCosimBuild|FALSE|BOOLEAN|0x0000001D
  81. ## Enable / disable DDRT2 buffer build
  82. gEfiCpRcPkgTokenSpaceGuid.PcdDdrt2BufferlessBuild|FALSE|BOOLEAN|0x0000004F
  83. # Backside Rank Margin Tool
  84. gEfiCpRcPkgTokenSpaceGuid.EnableBacksideRmt|FALSE|BOOLEAN|0x0000001F
  85. # Backside Command Rank Margin Tool
  86. gEfiCpRcPkgTokenSpaceGuid.EnableBacksideCmdRmt|FALSE|BOOLEAN|0x00000030
  87. # RMT Pattern Length
  88. gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthCmd|32767|UINT32|0x00000031
  89. gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthExtCmdCtlVref|32767|UINT32|0x00000032
  90. gEfiCpRcPkgTokenSpaceGuid.PcdEnableNgnBcomMargining|FALSE|BOOLEAN|0x00000033
  91. #Enable per bit margining
  92. gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|TRUE|BOOLEAN|0x00000034
  93. ## Enable / disable MRS STACKING in the CPGC
  94. gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdr|FALSE|BOOLEAN|0x00000037
  95. gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdrt|FALSE|BOOLEAN|0x00000038
  96. gEfiCpRcPkgTokenSpaceGuid.MrsStackingNvdimm|FALSE|BOOLEAN|0x00000039
  97. # Use this PCD to control if separate CWL_adj calculation for 14nm and 10nm
  98. gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|FALSE|BOOLEAN|0x0000003B
  99. ## Enable / disable USRA register filter. For Sim and SMM.
  100. gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterFilterEnable|TRUE|BOOLEAN|0x0000002D
  101. ## Enable / disable USRA register log.
  102. gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterLogEnable|TRUE|BOOLEAN|0x0000002E
  103. ## Enable / disable override of debug levels during MRC call table execution
  104. gEfiCpRcPkgTokenSpaceGuid.PcdDebugLevelsOverride|TRUE|BOOLEAN|0x00000050
  105. gEfiCpRcPkgTokenSpaceGuid.PcdReserved1|TRUE|BOOLEAN|0x00000051
  106. gEfiCpRcPkgTokenSpaceGuid.PcdReserved2|FALSE|BOOLEAN|0x0000011c
  107. gEfiCpRcPkgTokenSpaceGuid.PcdReserved3|FALSE|BOOLEAN|0x0000011d
  108. gEfiCpRcPkgTokenSpaceGuid.PcdReserved4|FALSE|BOOLEAN|0x0000011e
  109. gEfiCpRcPkgTokenSpaceGuid.Reserved15|FALSE|BOOLEAN|0x00000052
  110. gEfiCpRcPkgTokenSpaceGuid.PcdReserved5|TRUE|BOOLEAN|0x00000053
  111. gEfiCpRcPkgTokenSpaceGuid.PcdReserved6|FALSE|BOOLEAN|0x00000054
  112. #Enable\Disable Mem Boot Health Feature
  113. gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|TRUE|BOOLEAN|0x00000055
  114. #Control Opportunistic Self Refresh(OSR) feature.
  115. #PCD hides\shows the OSR Setup knob based on setting
  116. #default disabled
  117. gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshSupported|FALSE|BOOLEAN|0x00000115
  118. gEfiCpRcPkgTokenSpaceGuid.PcdDprSizeFeatureSupport|FALSE|BOOLEAN|0x00000056
  119. #SecurityPolicy
  120. gSecurityPolicyDataGuid.PcdCoSignEnable|FALSE|BOOLEAN|0xE000002F
  121. [PcdsFixedAtBuild]
  122. #
  123. # MRC build time configuration PCD's
  124. #
  125. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE|BOOLEAN|0x00000100
  126. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|FALSE|BOOLEAN|0x00000101
  127. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE|BOOLEAN|0x00000102
  128. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE|BOOLEAN|0x00000103
  129. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE|BOOLEAN|0x00000104
  130. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE|BOOLEAN|0x00000105
  131. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE|BOOLEAN|0x00000106
  132. gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE|BOOLEAN|0x00000107
  133. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE|BOOLEAN|0x00000113
  134. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSpdDecodeLibTrace|FALSE|BOOLEAN|0x00000114
  135. #PCD controls Setup default for OSR
  136. #Default disabled
  137. gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshDefault|0|UINT8|0x00000116
  138. #PCD controls Setup default for DDRT Self Refresh
  139. #Default disabled
  140. gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSrefDefault|0|UINT8|0x00000117
  141. #
  142. # Dimm support
  143. #
  144. gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE|BOOLEAN|0x00000108
  145. gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE|BOOLEAN|0x00000109
  146. #
  147. # SVID support
  148. #
  149. gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidSupported|TRUE|BOOLEAN|0x8000010A
  150. #
  151. # Miscellaneous MRC options
  152. #
  153. gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE|BOOLEAN|0x00000110
  154. gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE|BOOLEAN|0x00000112
  155. gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|FALSE|BOOLEAN|0x00000111
  156. ## Indicates the size of each PCIE segment
  157. gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010
  158. gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013
  159. ## Indicates the max nested level
  160. gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018
  161. ## Maximum number of sockets supported for this firmware build.
  162. # This PCD should be used sparingly. Dynamic allocation of data and
  163. # dynamic control flows are preferred over using this PCD for static
  164. # data allocation and control.
  165. gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019
  166. gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|0x22|UINT32|0x0000001A
  167. gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|0x2|UINT32|0x0000001B
  168. gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutBaseClock|0x0000001C|UINT32|0x00000022
  169. gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutThreshold|0x0000000C|UINT32|0x00000023
  170. gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutCreditLimit|0x00000020|UINT32|0x00000024
  171. ## Enable / Disable USRA trace configuration by IO port
  172. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortEnable|FALSE|BOOLEAN|0x00000025
  173. ## Set the specific IO port for trace configuration low byte
  174. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortLow|0x81|UINT8|0x00000026
  175. ## Set the specific IO port for trace configuration high byte
  176. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortHigh|0x82|UINT8|0x00000027
  177. ## PcdUsraTraceConfigurationValue is used to control the USRA trace behavior, and the defination shown as below.
  178. # When PcdUsraTraceConfigurationPortEnable is TRUE, this configuration value can be overridden by configuration IO port.
  179. # When PcdUsraTraceConfigurationPortEnable is FALSE, the value can be overridden via the interface SetUsraTraceConfiguration().
  180. # Bit 0 - Bit 3 : USRA trace Signature,it should always be 0101B.
  181. # Bit 4: Set indicates USRA trace message's format is long mode.
  182. # Bit 5: Set indicates get address operation is traced.
  183. # Bit 6: Set indicates modify operation is traced.
  184. # Bit 7: Set indicates write operation is traced.
  185. # Bit 8: Set indicates read operation is traced.
  186. # Bit 9: Set indicates PCIE access is traced.
  187. # Bit 10: Set indicates CSR access is traced.
  188. # Bit 11 - Bit14: Reserved for future uses.
  189. # Bit 15: Set indicates dumps the content of CpuCsrAccessVar before dumping the register access trace information.
  190. # @Prompt USRA trace configuration settings.
  191. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationValue|0x07F5|UINT16|0x00000028
  192. ## Default value to USRA trace start at earlier stage, this value can be overridden by the interface UsraTraceStart()
  193. ## and UsraTraceEnd().
  194. gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceStartAtEarlierStage|FALSE|BOOLEAN|0x00000029
  195. ## Indicates whether it needs to clear temp bus assignment in PCIE common init library
  196. gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE|BOOLEAN|0x0000002A
  197. gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion|{0, 0, 0, 0}|RC_VERSION|0x00000015 {
  198. <HeaderFiles>
  199. RcVersion.h
  200. <Packages>
  201. WhitleySiliconPkg/CpRcPkg.dec
  202. }
  203. gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0
  204. gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4
  205. gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2
  206. gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A
  207. #
  208. # MRC DEFAULT SETTINGS
  209. #
  210. # PCD NAME | VALUE| TYPE| PCD NUM.
  211. ## Default Enable / Disable Legacy RMT Feature
  212. gEfiCpRcPkgTokenSpaceGuid.PcdLegacyRmtEnable | 1| UINT8|0x0000001E
  213. #
  214. # Enforce memory POR configurations
  215. # 0 (ENFORCE_POR_EN) - Enforce memory POR
  216. # 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal
  217. # 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations
  218. #
  219. gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | 0| UINT8|0x00000040
  220. gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE|BOOLEAN|0x0000003A
  221. gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | FALSE|BOOLEAN|0x00000060
  222. gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastColdBootDefault | TRUE|BOOLEAN|0x00000061
  223. gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault | TRUE|BOOLEAN|0x00000062
  224. gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault | 0xFF| UINT8|0x00000063
  225. gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault | 0xFF| UINT8|0x00000064
  226. gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault | 0x0| UINT8|0x00000065
  227. gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | 0x2| UINT8|0x00000066
  228. gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | FALSE|BOOLEAN|0x00000067
  229. gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | 0x6| UINT8|0x00000068
  230. gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOOLEAN|0x00000069
  231. gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | TRUE| UINT8|0x0000006A
  232. #Setup string for Mem boot health check
  233. gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHealthConfig"| VOID*|0x00000070
  234. gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | FALSE|BOOLEAN|0x00000071
  235. gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | FALSE|BOOLEAN|0x00000072
  236. gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | 1| UINT8|0x00000073
  237. gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | 1| UINT8|0x00000074
  238. gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2| UINT8|0x0000011F
  239. gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE|BOOLEAN|0x00000120
  240. gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | FALSE|BOOLEAN|0x00000075
  241. #option to choose Mem Boot Health configuration type. 00=>Auto (Use defaults), 01=>Manual (Override defaults with setup option), 02=>Disable (Disable feature)
  242. gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | 00| UINT8|0x00000076
  243. # The below values are setup\standard\build defaults. Can be overridden in platform specific dsc
  244. ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS STARTS#####################################
  245. #Left edge offset for TxDqDelay
  246. gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayLeftEdge | 5| UINT8|0x00000077
  247. #Right edge offset for TxDqDelay
  248. gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayRightEdge | 5| UINT8|0x00000078
  249. #Left edge offset for TxVref
  250. gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefLeftEdge | 5| UINT8|0x00000079
  251. #Right edge offset for TxVref
  252. gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefRightEdge | 5| UINT8|0x0000007A
  253. #Left edge offset for RxDqsDelay
  254. gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayLeftEdge | 5| UINT8|0x0000007B
  255. #Right edge offset for RxDqsDelay
  256. gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayRightEdge | 5| UINT8|0x0000007C
  257. #Left edge offset for RxVref
  258. gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefLeftEdge | 5| UINT8|0x0000007D
  259. #Right edge offset for RxVref
  260. gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefRightEdge | 5| UINT8|0x0000007E
  261. ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS ENDS#######################################
  262. ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS STARTS####################################
  263. #Left edge offset for TxDqDelay
  264. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayLeftEdge | 2| UINT8|0x0000007F
  265. #Right edge offset for TxDqDelay
  266. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayRightEdge | 2| UINT8|0x00000080
  267. #Left edge offset for TxVref
  268. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefLeftEdge | 2| UINT8|0x00000081
  269. #Right edge offset for TxVref
  270. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefRightEdge | 2| UINT8|0x00000082
  271. #Left edge offset for RxDqsDelay
  272. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayLeftEdge | 2| UINT8|0x00000083
  273. #Right edge offset for RxDqsDelay
  274. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayRightEdge | 2| UINT8|0x00000084
  275. #Left edge offset for RxVref
  276. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefLeftEdge | 2| UINT8|0x00000085
  277. #Right edge offset for RxVref
  278. gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefRightEdge | 2| UINT8|0x00000086
  279. ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS ENDS######################################
  280. # Option to enable/disable RMT minimum margin test
  281. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumMarginCheckDefault | 1| UINT8|0x00000124
  282. # Define the default minimum margin thresholds for RMT margin check
  283. # The minimum margin thresholds are applied to both margin directions.
  284. # Rx timing: RxDqsDelay
  285. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxTimingMargin | 3| UINT8|0x00000125
  286. # Rx voltage: RxVref
  287. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxVoltageMargin | 3| UINT8|0x00000126
  288. # Tx timing: TxDqDelay
  289. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxTimingMargin | 3| UINT8|0x00000127
  290. # Tx voltage: TxVref
  291. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxVoltageMargin | 3| UINT8|0x00000128
  292. # Cmd timing: CmdAll
  293. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdTimingMargin | 5| UINT8|0x00000129
  294. # Cmd voltage: CmdVref
  295. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdVoltageMargin | 5| UINT8|0x00000130
  296. # Ctl timing: CtlAll
  297. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | 5| UINT8|0x00000131
  298. #MC VC0 Deadlock Breaker
  299. gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings | TRUE| BOOLEAN|0x00000132
  300. gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer | 18| UINT8|0x00000133
  301. gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold | 4| UINT8|0x00000134
  302. #Reset on Critical Margin failure to perform Memory Training from scratch
  303. gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | 1| UINT8|0x00000087
  304. #Enable Debug message inside MarginTest
  305. #BIT0 for API Debug messages
  306. #BIT1 for Log messages
  307. #BIT2 for Error messages
  308. #BIT3 for Function trace messages
  309. gEfiCpRcPkgTokenSpaceGuid.PcdEvDebugMsg | 0| UINT8|0x00000088
  310. #Non-Configurable...Number of Signals to test.
  311. gEfiCpRcPkgTokenSpaceGuid.PcdMemBootSignalsToTest | 4| UINT8|0x00000089
  312. gEfiCpRcPkgTokenSpaceGuid.PcdReserved14| FALSE|BOOLEAN|0x0000008B
  313. gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations | FALSE|BOOLEAN|0x0000008C
  314. gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt| FALSE|BOOLEAN|0x0000008D
  315. #
  316. # Default SMBUS Speed - see SMB_CLOCK_FREQUENCY
  317. # 0 - SMB_CLK_100K - 100 Khz
  318. # 1 - SMB_CLK_400K - 400 Khz
  319. # 2 - SMB_CLK_700K - 700 Khz
  320. # 3 - SMB_CLK_1M - 1 Mhz
  321. #
  322. gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault | 0x1| UINT8|0x0000008E
  323. #
  324. # Throttling mid on temp lo
  325. # 0 - Disabled
  326. # 1 - Enabled
  327. #
  328. gEfiCpRcPkgTokenSpaceGuid.PcdMrcThrottlingMidOnTempLo | 0| UINT8|0x0000008F
  329. gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault | 0x1| UINT8|0x00000090
  330. gEfiCpRcPkgTokenSpaceGuid.PcdMrcCtleTrainingEnable | TRUE|BOOLEAN|0x00000091
  331. gEfiCpRcPkgTokenSpaceGuid.PcdMrcImodeTrainingEnable | TRUE|BOOLEAN|0x00000092
  332. #CLTT settings
  333. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault | 82| UINT8|0x00000093
  334. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault | 83| UINT8|0x00000094
  335. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault | 85| UINT8|0x00000095
  336. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault | 83| UINT8|0x00000096
  337. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault | 83| UINT8|0x00000097
  338. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault | 93| UINT8|0x00000098
  339. gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault | 95| UINT8|0x00000099
  340. #
  341. # Allowed debug level at build time configuration
  342. # See RcDebugLib.h for mapping details
  343. #
  344. gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugAllowedLevelsMask | 0xC7F0190B| UINT32|0x0000009A
  345. gEfiCpRcPkgTokenSpaceGuid.PcdMrcTcoCompTrainingEnable | FALSE|BOOLEAN|0x0000009B
  346. gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault | 0x1| UINT8|0x0000009C
  347. gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault | 1| UINT8|0x0000009D
  348. #
  349. # Enforce memory population POR configurations.
  350. # 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce memory population POR.
  351. # 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported memory populations.
  352. # 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated memory populations.
  353. gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePopulationPorDefault | 1| UINT8|0x0000009E
  354. gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable | TRUE|BOOLEAN|0x0000009F
  355. #
  356. # Legacy ADR flow
  357. # 0 (LEGACY_ADR_MODE_DISABLE) - Pcode driven ADR flow
  358. # 1 (LEGACY_ADR_MODE_ENABLE) - Legacy ADR flow
  359. #
  360. gEfiCpRcPkgTokenSpaceGuid.PcdLegacyAdrDefault | 0| UINT8|0x000000A0
  361. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault | 0x1| UINT8|0x000000A1
  362. gEfiCpRcPkgTokenSpaceGuid.PcdMrcPxcDefault | 0x1| UINT8|0x000000A2
  363. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdjcDefault | 0x1| UINT8|0x000000A3
  364. #
  365. # Default debug level at build time configuration
  366. #
  367. gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugBuildTimeDefault | 0x8000190B| UINT32|0x000000A9
  368. gEfiCpRcPkgTokenSpaceGuid.PcdRmtMarginInCaCsTm | TRUE|BOOLEAN|0x000000AC
  369. gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault | 0| UINT8|0x000000AE
  370. #Only enable for 14nm, not a feature for 10nm and above
  371. # 0 = Disable
  372. # 1 = TA Floor
  373. # 2 = Receive Enable Average
  374. # 3 = Receive Enable Average part 1 only
  375. gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption | 0|UINT8|0x000000A4
  376. #
  377. # Timers detinitions for priority promotions
  378. #
  379. gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim | 0x100| UINT16|0x000000A5
  380. gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim | 0x100| UINT16|0x000000A6
  381. gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim | 0x100| UINT16|0x000000A7
  382. #Mrc memory default frequency
  383. gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdrFrequencyDefault | 0x0| UINT8|0x000000A8
  384. #MRC Panic Watermark default
  385. # 0 = Auto, 1 = High, 2 = Low
  386. gEfiCpRcPkgTokenSpaceGuid.PcdMrcPanicWatermarkDefault | 0x0| UINT8|0x000000AA
  387. gEfiCpRcPkgTokenSpaceGuid.PcdReserved15 | 0x2| UINT8|0x000000AB
  388. gEfiCpRcPkgTokenSpaceGuid.PcdReserved16 | 0x0| UINT8|0x000000AD
  389. # Additional Buffer Delay for Roundtrip
  390. gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk | 4| UINT8|0x000000AF
  391. # Option to enable / disable MCR Support
  392. gEfiCpRcPkgTokenSpaceGuid.PcdMcrSupport | FALSE|BOOLEAN|0x000000B0
  393. # Option to store SPD raw data to BDAT
  394. gEfiCpRcPkgTokenSpaceGuid.SaveSpdToBdat | TRUE|BOOLEAN|0x00000121
  395. # Option to store training data to BDAT
  396. gEfiCpRcPkgTokenSpaceGuid.SaveMrcTrainingDataToBdat | TRUE|BOOLEAN|0x00000122
  397. gEfiCpRcPkgTokenSpaceGuid.PcdVendorMemtestEnable | TRUE|BOOLEAN|0x00000123
  398. [PcdsDynamicEx]
  399. ## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 |
  400. gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011
  401. gEfiCpRcPkgTokenSpaceGuid.PcdSimStaticPointerTableMapPtr|{0x0}|VOID*|0x80000012
  402. ############### SVID Mapping ##################################
  403. #The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
  404. #Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
  405. #Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
  406. #and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
  407. #This information is per platform basis and can be obtained from platform schematics.
  408. #Need to map this token for MC to SVID based on platform.
  409. gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap|{0}|MEM_SVID_MAP|0x80000014 {
  410. <HeaderFiles>
  411. Library/MemVrSvidMapLib.h
  412. <Packages>
  413. WhitleySiliconPkg/WhitleySiliconPkg.dec
  414. }
  415. ############### SVID Mapping ##################################
  416. # IMON SVID VR address
  417. # Fill with IMON SVID Address
  418. # End the list with 0xFF (IMON_ADDR_LIST_END)
  419. # Assumption, all socket repeat same address
  420. #BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
  421. #BIT 0:3 => SVID ADDRESS
  422. gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr|{0xFF}|VCC_IMON|0x0000008A {
  423. <HeaderFiles>
  424. ImonVrSvid.h
  425. <Packages>
  426. WhitleySiliconPkg/WhitleySiliconPkg.dec
  427. }
  428. [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
  429. gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32|0x00000020
  430. gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x00000021
  431. gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035
  432. gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000036
  433. gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x00000118
  434. ## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor
  435. gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C
  436. gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D
  437. [PcdsDynamicEx]
  438. gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00000048
  439. gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0x00000049
  440. gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A
  441. gEfiCpRcPkgTokenSpaceGuid.PcdLtMemSize|0x00500000|UINT32|0x0000004B
  442. gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable|FALSE|BOOLEAN|0x0000004C
  443. gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size|0x0|UINT64|0x0000004D
  444. #
  445. # PCD for storing sizeof (SysHost) in PEI for later comparision in DXE
  446. #
  447. gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize|0x00000000|UINT32|0x0000004E