Cn9132Eval.dsc.inc 3.2 KB

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  1. ## @file
  2. # Component description file for the CN9132 Development Board (variant A)
  3. #
  4. # Copyright (c) 2019 Marvell International Ltd.<BR>
  5. # Copyright (c) 2021 Semihalf.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. ##
  10. ################################################################################
  11. #
  12. # Pcd Section - list of all EDK II PCD Entries defined by this Platform
  13. #
  14. ################################################################################
  15. [PcdsFixedAtBuild.common]
  16. # CP115 count
  17. gMarvellTokenSpaceGuid.PcdMaxCpCount|3
  18. # MPP
  19. gMarvellTokenSpaceGuid.PcdMppChipCount|4
  20. # CP115 #2 MPP
  21. gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
  22. gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
  23. gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
  24. gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  25. gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  26. gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 }
  27. gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF }
  28. gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  29. gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF }
  30. gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  31. # ComPhy
  32. gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
  33. # ComPhy2
  34. # 0: PCIE0 5 Gbps
  35. # 1: USB3_HOST0 5 Gbps
  36. # 2: SFI 5.15625 Gbps
  37. # 3: SATA1 5 Gbps
  38. # 4: PCIE1 5 Gbps
  39. # 5: PCIE2 5 Gbps
  40. gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
  41. gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
  42. # UtmiPhy
  43. gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
  44. gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
  45. # NET
  46. gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
  47. gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0 }
  48. gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
  49. gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
  50. gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }
  51. gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
  52. gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
  53. gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
  54. # NonDiscoverableDevices
  55. gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
  56. gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
  57. gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }