Armada80x0McBin.dsc 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. #Copyright (C) 2017 Marvell International Ltd.
  2. #
  3. #SPDX-License-Identifier: BSD-2-Clause-Patent
  4. #
  5. ################################################################################
  6. #
  7. # Defines Section - statements that will be processed to create a Makefile.
  8. #
  9. ################################################################################
  10. [Defines]
  11. PLATFORM_NAME = Armada80x0McBin
  12. PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
  13. PLATFORM_VERSION = 0.1
  14. DSC_SPECIFICATION = 0x0001001A
  15. OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
  16. SUPPORTED_ARCHITECTURES = AARCH64|ARM
  17. BUILD_TARGETS = DEBUG|RELEASE|NOOPT
  18. SKUID_IDENTIFIER = DEFAULT
  19. FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
  20. BOARD_DXE_FV_COMPONENTS = Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
  21. CAPSULE_ENABLE = TRUE
  22. #
  23. # Network definition
  24. #
  25. DEFINE NETWORK_IP6_ENABLE = FALSE
  26. DEFINE NETWORK_TLS_ENABLE = FALSE
  27. DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
  28. DEFINE NETWORK_ISCSI_ENABLE = FALSE
  29. !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
  30. !include MdePkg/MdeLibs.dsc.inc
  31. [Components.common]
  32. Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
  33. [Components.AARCH64]
  34. Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
  35. [LibraryClasses.common]
  36. ArmadaBoardDescLib|Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
  37. NonDiscoverableInitLib|Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
  38. ################################################################################
  39. #
  40. # Pcd Section - list of all EDK II PCD Entries defined by this Platform
  41. #
  42. ################################################################################
  43. [PcdsFixedAtBuild.common]
  44. #Platform description
  45. gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
  46. gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
  47. gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
  48. #MPP
  49. gMarvellTokenSpaceGuid.PcdMppChipCount|3
  50. # APN806-A0 MPP SET
  51. gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
  52. gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
  53. gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
  54. gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
  55. gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
  56. # CP110 MPP SET - master
  57. gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
  58. gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
  59. gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
  60. gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  61. gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  62. gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  63. gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
  64. gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  65. gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
  66. gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  67. # CP110 MPP SET - slave
  68. gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
  69. gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
  70. gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
  71. gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
  72. gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
  73. gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
  74. gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  75. gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  76. gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  77. gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  78. #SPI
  79. gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
  80. gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
  81. gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
  82. gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
  83. gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
  84. #ComPhy
  85. gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
  86. # ComPhy0
  87. # 0: PCIE0 5 Gbps
  88. # 1: PCIE0 5 Gbps
  89. # 2: PCIE0 5 Gbps
  90. # 3: PCIE0 5 Gbps
  91. # 4: SFI 10.31 Gbps
  92. # 5: SATA1 5 Gbps
  93. gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
  94. gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
  95. # ComPhy1
  96. # 0: SGMII1 1.25 Gbps
  97. # 1: SATA0 5 Gbps
  98. # 2: USB3_HOST0 5 Gbps
  99. # 3: SATA1 5 Gbps
  100. # 4: SFI 10.31 Gbps
  101. # 5: SGMII2 3.125 Gbps
  102. gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
  103. gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
  104. #UtmiPhy
  105. gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
  106. gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
  107. #MDIO
  108. gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
  109. #PHY
  110. gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
  111. gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
  112. gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
  113. gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
  114. #NET
  115. gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
  116. gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
  117. gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
  118. gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
  119. gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
  120. gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
  121. gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
  122. gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
  123. #PciEmulation
  124. gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
  125. gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
  126. gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
  127. #RTC
  128. gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000