U540.fdf.inc 4.5 KB

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  1. ## @file
  2. # Definitions of Flash definition file on SiFive Freedom U540 HiFive Unleashed RISC-V platform
  3. #
  4. # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. DEFINE BLOCK_SIZE = 0x1000
  11. DEFINE FW_BASE_ADDRESS = 0x80000000
  12. DEFINE FW_SIZE = 0x00900000
  13. DEFINE FW_BLOCKS = 0x900
  14. #
  15. # 0x000000-0x7DFFFF code
  16. # 0x7E0000-0x800000 variables
  17. #
  18. DEFINE CODE_BASE_ADDRESS = 0x80000000
  19. DEFINE CODE_SIZE = 0x00800000
  20. DEFINE CODE_BLOCKS = 0x800
  21. DEFINE VARS_BLOCKS = 0x20
  22. #
  23. # SEC + opensbi library is the root FW domain.
  24. # The base address must be round up to log2.
  25. #
  26. DEFINE SECFV_OFFSET = 0x00000000
  27. DEFINE SECFV_SIZE = 0x00040000
  28. DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
  29. #
  30. # Other FV regions are in the second FW domain.
  31. # The size of memory region must be power of 2.
  32. # The base address must be aligned with the size.
  33. #
  34. # FW memory region
  35. #
  36. DEFINE PEIFV_OFFSET = 0x00400000
  37. DEFINE PEIFV_SIZE = 0x00180000
  38. DEFINE FVMAIN_OFFSET = 0x00580000
  39. DEFINE FVMAIN_SIZE = 0x00280000
  40. #
  41. # EFI Variable memory region.
  42. # The total size of EFI Variable FD must include
  43. # all of sub regions of EFI Variable
  44. #
  45. DEFINE VARS_OFFSET = 0x00800000
  46. DEFINE VARS_SIZE = 0x00007000
  47. DEFINE VARS_FTW_WORKING_OFFSET = 0x00807000
  48. DEFINE VARS_FTW_WORKING_SIZE = 0x00001000
  49. DEFINE VARS_FTW_SPARE_OFFSET = 0x00808000
  50. DEFINE VARS_FTW_SPARE_SIZE = 0x00018000
  51. #
  52. # Device Tree memory region
  53. #
  54. DEFINE DTB_OFFSET = 0x00840000
  55. DEFINE DTB_SIZE = 0x00002000
  56. #
  57. # Scratch area memory region
  58. #
  59. DEFINE SCRATCH_OFFSET = 0x00880000
  60. DEFINE SCRATCH_SIZE = 0x00010000
  61. DEFINE FW_DOMAIN_SIZE = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
  62. DEFINE VARIABLE_FW_SIZE = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET)
  63. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
  64. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize = $(ROOT_FW_DOMAIN_SIZE)
  65. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
  66. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize = $(FW_DOMAIN_SIZE)
  67. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
  68. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
  69. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
  70. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
  71. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = $(VARIABLE_FW_SIZE)
  72. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
  73. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
  74. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
  75. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE)
  76. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
  77. SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
  78. SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 1000000000 # 1GHz system clock
  79. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId = 1 # Boot hart ID
  80. #
  81. # The bootable hart number the platform would like to use during boot.
  82. #
  83. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber = 4
  84. #
  85. # Only use hart ID 1, 2, 3, 4
  86. #
  87. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId = {0x1,0x2,0x3,0x4}
  88. # during boot
  89. SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores = 4 # Total U5 cores enabled on U540 platform
  90. SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported = True # E51 MC exists.
  91. SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase = 0x10010000 # Serial port base address
  92. SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode = 1 # Set PeiCore to S-Mode