fu540-c000.dtsi 14 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2018-2019 SiFive, Inc */
  3. /dts-v1/;
  4. /**@file
  5. SiFive U540 platform Device Tree
  6. Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. #include "sifive-fu540-prci.h"
  10. / {
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. compatible = "sifive,fu540-c000", "sifive,fu540";
  14. aliases {
  15. serial0 = &uart0;
  16. serial1 = &uart1;
  17. ethernet0 = &eth0;
  18. };
  19. chosen {
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu0: cpu@0 {
  25. compatible = "sifive,e51", "sifive,rocket0", "riscv";
  26. device_type = "cpu";
  27. i-cache-block-size = <64>;
  28. i-cache-sets = <128>;
  29. i-cache-size = <16384>;
  30. reg = <0>;
  31. riscv,isa = "rv64imac";
  32. status = "disabled";
  33. cpu0_intc: interrupt-controller {
  34. #interrupt-cells = <1>;
  35. compatible = "riscv,cpu-intc";
  36. interrupt-controller;
  37. };
  38. };
  39. cpu1: cpu@1 {
  40. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  41. d-cache-block-size = <64>;
  42. d-cache-sets = <64>;
  43. d-cache-size = <32768>;
  44. d-tlb-sets = <1>;
  45. d-tlb-size = <32>;
  46. device_type = "cpu";
  47. i-cache-block-size = <64>;
  48. i-cache-sets = <64>;
  49. i-cache-size = <32768>;
  50. i-tlb-sets = <1>;
  51. i-tlb-size = <32>;
  52. mmu-type = "riscv,sv39";
  53. reg = <1>;
  54. riscv,isa = "rv64imafdc";
  55. tlb-split;
  56. next-level-cache = <&l2cache>;
  57. cpu1_intc: interrupt-controller {
  58. #interrupt-cells = <1>;
  59. compatible = "riscv,cpu-intc";
  60. interrupt-controller;
  61. };
  62. };
  63. cpu2: cpu@2 {
  64. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  65. d-cache-block-size = <64>;
  66. d-cache-sets = <64>;
  67. d-cache-size = <32768>;
  68. d-tlb-sets = <1>;
  69. d-tlb-size = <32>;
  70. device_type = "cpu";
  71. i-cache-block-size = <64>;
  72. i-cache-sets = <64>;
  73. i-cache-size = <32768>;
  74. i-tlb-sets = <1>;
  75. i-tlb-size = <32>;
  76. mmu-type = "riscv,sv39";
  77. reg = <2>;
  78. riscv,isa = "rv64imafdc";
  79. tlb-split;
  80. next-level-cache = <&l2cache>;
  81. cpu2_intc: interrupt-controller {
  82. #interrupt-cells = <1>;
  83. compatible = "riscv,cpu-intc";
  84. interrupt-controller;
  85. };
  86. };
  87. cpu3: cpu@3 {
  88. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  89. d-cache-block-size = <64>;
  90. d-cache-sets = <64>;
  91. d-cache-size = <32768>;
  92. d-tlb-sets = <1>;
  93. d-tlb-size = <32>;
  94. device_type = "cpu";
  95. i-cache-block-size = <64>;
  96. i-cache-sets = <64>;
  97. i-cache-size = <32768>;
  98. i-tlb-sets = <1>;
  99. i-tlb-size = <32>;
  100. mmu-type = "riscv,sv39";
  101. reg = <3>;
  102. riscv,isa = "rv64imafdc";
  103. tlb-split;
  104. next-level-cache = <&l2cache>;
  105. cpu3_intc: interrupt-controller {
  106. #interrupt-cells = <1>;
  107. compatible = "riscv,cpu-intc";
  108. interrupt-controller;
  109. };
  110. };
  111. cpu4: cpu@4 {
  112. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  113. d-cache-block-size = <64>;
  114. d-cache-sets = <64>;
  115. d-cache-size = <32768>;
  116. d-tlb-sets = <1>;
  117. d-tlb-size = <32>;
  118. device_type = "cpu";
  119. i-cache-block-size = <64>;
  120. i-cache-sets = <64>;
  121. i-cache-size = <32768>;
  122. i-tlb-sets = <1>;
  123. i-tlb-size = <32>;
  124. mmu-type = "riscv,sv39";
  125. reg = <4>;
  126. riscv,isa = "rv64imafdc";
  127. tlb-split;
  128. next-level-cache = <&l2cache>;
  129. cpu4_intc: interrupt-controller {
  130. #interrupt-cells = <1>;
  131. compatible = "riscv,cpu-intc";
  132. interrupt-controller;
  133. };
  134. };
  135. };
  136. soc {
  137. #address-cells = <2>;
  138. #size-cells = <2>;
  139. compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
  140. ranges;
  141. plic0: interrupt-controller@c000000 {
  142. #interrupt-cells = <1>;
  143. compatible = "sifive,plic-1.0.0";
  144. reg = <0x0 0xc000000 0x0 0x4000000>;
  145. riscv,ndev = <53>;
  146. interrupt-controller;
  147. interrupts-extended = <
  148. &cpu0_intc 0xffffffff
  149. &cpu1_intc 0xffffffff &cpu1_intc 9
  150. &cpu2_intc 0xffffffff &cpu2_intc 9
  151. &cpu3_intc 0xffffffff &cpu3_intc 9
  152. &cpu4_intc 0xffffffff &cpu4_intc 9>;
  153. };
  154. prci: clock-controller@10000000 {
  155. compatible = "sifive,fu540-c000-prci";
  156. reg = <0x0 0x10000000 0x0 0x1000>;
  157. clocks = <&hfclk>, <&rtcclk>;
  158. #clock-cells = <1>;
  159. };
  160. uart0: serial@10010000 {
  161. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  162. reg = <0x0 0x10010000 0x0 0x1000>;
  163. interrupt-parent = <&plic0>;
  164. interrupts = <4>;
  165. clocks = <&prci PRCI_CLK_TLCLK>;
  166. status = "disabled";
  167. };
  168. dma: dma@3000000 {
  169. compatible = "sifive,fu540-c000-pdma";
  170. reg = <0x0 0x3000000 0x0 0x8000>;
  171. interrupt-parent = <&plic0>;
  172. interrupts = <23 24 25 26 27 28 29 30>;
  173. #dma-cells = <1>;
  174. };
  175. uart1: serial@10011000 {
  176. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  177. reg = <0x0 0x10011000 0x0 0x1000>;
  178. interrupt-parent = <&plic0>;
  179. interrupts = <5>;
  180. clocks = <&prci PRCI_CLK_TLCLK>;
  181. status = "disabled";
  182. };
  183. i2c0: i2c@10030000 {
  184. compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
  185. reg = <0x0 0x10030000 0x0 0x1000>;
  186. interrupt-parent = <&plic0>;
  187. interrupts = <50>;
  188. clocks = <&prci PRCI_CLK_TLCLK>;
  189. reg-shift = <2>;
  190. reg-io-width = <1>;
  191. #address-cells = <1>;
  192. #size-cells = <0>;
  193. status = "disabled";
  194. };
  195. qspi0: spi@10040000 {
  196. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  197. reg = <0x0 0x10040000 0x0 0x1000
  198. 0x0 0x20000000 0x0 0x10000000>;
  199. interrupt-parent = <&plic0>;
  200. interrupts = <51>;
  201. clocks = <&prci PRCI_CLK_TLCLK>;
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. status = "disabled";
  205. };
  206. qspi1: spi@10041000 {
  207. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  208. reg = <0x0 0x10041000 0x0 0x1000
  209. 0x0 0x30000000 0x0 0x10000000>;
  210. interrupt-parent = <&plic0>;
  211. interrupts = <52>;
  212. clocks = <&prci PRCI_CLK_TLCLK>;
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. status = "disabled";
  216. };
  217. qspi2: spi@10050000 {
  218. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  219. reg = <0x0 0x10050000 0x0 0x1000>;
  220. interrupt-parent = <&plic0>;
  221. interrupts = <6>;
  222. clocks = <&prci PRCI_CLK_TLCLK>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. status = "disabled";
  226. };
  227. eth0: ethernet@10090000 {
  228. compatible = "sifive,fu540-c000-gem";
  229. interrupt-parent = <&plic0>;
  230. interrupts = <53>;
  231. reg = <0x0 0x10090000 0x0 0x2000
  232. 0x0 0x100a0000 0x0 0x1000>;
  233. local-mac-address = [00 00 00 00 00 00];
  234. clock-names = "pclk", "hclk";
  235. clocks = <&prci PRCI_CLK_GEMGXLPLL>,
  236. <&prci PRCI_CLK_GEMGXLPLL>;
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. status = "disabled";
  240. };
  241. pwm0: pwm@10020000 {
  242. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  243. reg = <0x0 0x10020000 0x0 0x1000>;
  244. interrupt-parent = <&plic0>;
  245. interrupts = <42 43 44 45>;
  246. clocks = <&prci PRCI_CLK_TLCLK>;
  247. #pwm-cells = <3>;
  248. status = "disabled";
  249. };
  250. pwm1: pwm@10021000 {
  251. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  252. reg = <0x0 0x10021000 0x0 0x1000>;
  253. interrupt-parent = <&plic0>;
  254. interrupts = <46 47 48 49>;
  255. clocks = <&prci PRCI_CLK_TLCLK>;
  256. #pwm-cells = <3>;
  257. status = "disabled";
  258. };
  259. l2cache: cache-controller@2010000 {
  260. compatible = "sifive,fu540-c000-ccache", "cache";
  261. cache-block-size = <64>;
  262. cache-level = <2>;
  263. cache-sets = <1024>;
  264. cache-size = <2097152>;
  265. cache-unified;
  266. interrupt-parent = <&plic0>;
  267. interrupts = <1 2 3>;
  268. reg = <0x0 0x2010000 0x0 0x1000>;
  269. };
  270. gpio: gpio@10060000 {
  271. compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
  272. interrupt-parent = <&plic0>;
  273. interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
  274. <14>, <15>, <16>, <17>, <18>, <19>, <20>,
  275. <21>, <22>;
  276. reg = <0x0 0x10060000 0x0 0x1000>;
  277. gpio-controller;
  278. #gpio-cells = <2>;
  279. interrupt-controller;
  280. #interrupt-cells = <2>;
  281. clocks = <&prci PRCI_CLK_TLCLK>;
  282. status = "disabled";
  283. };
  284. clint: clint@2000000 {
  285. compatible = "riscv,clint0";
  286. interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
  287. &cpu1_intc 3 &cpu1_intc 7
  288. &cpu2_intc 3 &cpu2_intc 7
  289. &cpu3_intc 3 &cpu3_intc 7
  290. &cpu4_intc 3 &cpu4_intc 7>;
  291. reg = <0x0 0x2000000 0x0 0xc0000>;
  292. };
  293. };
  294. };