Pci.asl 5.9 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2019 Linaro, Limited. All rights reserved.
  4. * Copyright (c) 2021 Arm
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #include <IndustryStandard/Bcm2711.h>
  10. #include "AcpiTables.h"
  11. /*
  12. * The following can be used to remove parenthesis from
  13. * defined macros that the compiler complains about.
  14. */
  15. #define ISOLATE_ARGS(...) __VA_ARGS__
  16. #define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
  17. #define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
  18. #define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
  19. #define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
  20. DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
  21. {
  22. Scope (\_SB_)
  23. {
  24. Device(PCI0)
  25. {
  26. Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
  27. Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
  28. Name(_SEG, Zero) // PCI Segment Group number
  29. Name(_BBN, Zero) // PCI Base Bus Number
  30. Name(_CCA, 0) // Mark the PCI noncoherent
  31. // PCIe can only DMA to first 3GB with early SOC's
  32. // But we keep the restriction on the later ones
  33. // To avoid DMA translation problems.
  34. Name (_DMA, ResourceTemplate() {
  35. QWordMemory (ResourceProducer,
  36. ,
  37. MinFixed,
  38. MaxFixed,
  39. NonCacheable,
  40. ReadWrite,
  41. 0x0,
  42. 0x0, // MIN
  43. 0xbfffffff, // MAX
  44. 0x0, // TRA
  45. 0xc0000000, // LEN
  46. ,
  47. ,
  48. )
  49. })
  50. // PCI Routing Table
  51. Name(_PRT, Package() {
  52. Package (4) { 0x0000FFFF, 0, zero, 175 },
  53. Package (4) { 0x0000FFFF, 1, zero, 176 },
  54. Package (4) { 0x0000FFFF, 2, zero, 177 },
  55. Package (4) { 0x0000FFFF, 3, zero, 178 }
  56. })
  57. Name (_DSD, Package () {
  58. ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
  59. Package () {
  60. Package () { "linux-ecam-quirk-id", "bcm2711" },
  61. }
  62. })
  63. // Root complex resources
  64. Method (_CRS, 0, Serialized) {
  65. Name (RBUF, ResourceTemplate () {
  66. // bus numbers assigned to this root
  67. WordBusNumber (
  68. ResourceProducer,
  69. MinFixed, MaxFixed, PosDecode,
  70. 0, // AddressGranularity
  71. 0, // AddressMinimum - Minimum Bus Number
  72. 255, // AddressMaximum - Maximum Bus Number
  73. 0, // AddressTranslation - Set to 0
  74. 256 // RangeLength - Number of Busses
  75. )
  76. // 32-bit mmio window in 64-bit addr
  77. QWordMemory (
  78. ResourceProducer, PosDecode,
  79. MinFixed, MaxFixed,
  80. NonCacheable, ReadWrite, // cacheable
  81. 0x00000000, // Granularity
  82. 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
  83. 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
  84. SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
  85. 2 // SANITIZED_PCIE_MMIO_LEN + 1
  86. ,,,MMI1
  87. )
  88. // root port registers, not to be used if SMCCC is utilized
  89. QWordMemory (
  90. ResourceConsumer, ,
  91. MinFixed, MaxFixed,
  92. NonCacheable, ReadWrite, // cacheable
  93. 0x00000000, // Granularity
  94. 0xFD500000, // Root port begin
  95. 0xFD509FFF, // Root port end
  96. 0x00000000, // no translation
  97. 0x0000A000, // size
  98. ,,
  99. )
  100. }) // end Name(RBUF)
  101. // Work around ASL's inability to add in a resource definition
  102. // or for that matter compute the min,max,len properly
  103. CreateQwordField (RBUF, MMI1._MIN, MMIB)
  104. CreateQwordField (RBUF, MMI1._MAX, MMIE)
  105. CreateQwordField (RBUF, MMI1._TRA, MMIT)
  106. CreateQwordField (RBUF, MMI1._LEN, MMIL)
  107. Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
  108. Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
  109. Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
  110. Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
  111. Return (RBUF)
  112. } // end Method(_CRS)
  113. // OS Control Handoff
  114. Name(SUPP, Zero) // PCI _OSC Support Field value
  115. Name(CTRL, Zero) // PCI _OSC Control Field value
  116. // See [1] 6.2.10, [2] 4.5
  117. Method(_OSC,4) {
  118. // Note, This code is very similar to the code in the PCIe firmware
  119. // specification which can be used as a reference
  120. // Check for proper UUID
  121. If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  122. // Create DWord-adressable fields from the Capabilities Buffer
  123. CreateDWordField(Arg3,0,CDW1)
  124. CreateDWordField(Arg3,4,CDW2)
  125. CreateDWordField(Arg3,8,CDW3)
  126. // Save Capabilities DWord2 & 3
  127. Store(CDW2,SUPP)
  128. Store(CDW3,CTRL)
  129. // Mask out Native HotPlug
  130. And(CTRL,0x1E,CTRL)
  131. // Always allow native PME, AER (no dependencies)
  132. // Never allow SHPC (no SHPC controller in this system)
  133. And(CTRL,0x1D,CTRL)
  134. If(LNotEqual(Arg1,One)) { // Unknown revision
  135. Or(CDW1,0x08,CDW1)
  136. }
  137. If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
  138. Or(CDW1,0x10,CDW1)
  139. }
  140. // Update DWORD3 in the buffer
  141. Store(CTRL,CDW3)
  142. Return(Arg3)
  143. } Else {
  144. Or(CDW1,4,CDW1) // Unrecognized UUID
  145. Return(Arg3)
  146. }
  147. } // End _OSC
  148. } // PCI0
  149. } //end scope sb
  150. } //end definition block