PciCpuIo2Dxe.h 9.9 KB

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  1. /** @file
  2. Internal include file for the CPU I/O 2 Protocol.
  3. Copyright (c) 2022 Loongson Technology Corporation Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef PCI_CPU_IO2_DXE_H_
  7. #define PCI_CPU_IO2_DXE_H_
  8. #define MAX_IO_PORT_ADDRESS 0xFFFF
  9. /**
  10. Reads memory-mapped registers.
  11. The I/O operations are carried out exactly as requested. The caller is responsible
  12. for satisfying any alignment and I/O width restrictions that a PI System on a
  13. platform might require. For example on some platforms, width requests of
  14. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  15. be handled by the driver.
  16. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  17. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  18. each of the Count operations that is performed.
  19. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  20. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  21. incremented for each of the Count operations that is performed. The read or
  22. write operation is performed Count times on the same Address.
  23. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  24. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  25. incremented for each of the Count operations that is performed. The read or
  26. write operation is performed Count times from the first element of Buffer.
  27. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  28. @param[in] Width Signifies the width of the I/O or Memory operation.
  29. @param[in] Address The base address of the I/O operation.
  30. @param[in] Count The number of I/O operations to perform. The number of
  31. bytes moved is Width size * Count, starting at Address.
  32. @param[out] Buffer For read operations, the destination buffer to store the results.
  33. For write operations, the source buffer from which to write data.
  34. @retval EFI_SUCCESS The data was read from or written to the PI system.
  35. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  36. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  37. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  38. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  39. and Count is not valid for this PI system.
  40. **/
  41. EFI_STATUS
  42. EFIAPI
  43. CpuMemoryServiceRead (
  44. IN EFI_CPU_IO2_PROTOCOL *This,
  45. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  46. IN UINT64 Address,
  47. IN UINTN Count,
  48. OUT VOID *Buffer
  49. );
  50. /**
  51. Writes memory-mapped registers.
  52. The I/O operations are carried out exactly as requested. The caller is responsible
  53. for satisfying any alignment and I/O width restrictions that a PI System on a
  54. platform might require. For example on some platforms, width requests of
  55. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  56. be handled by the driver.
  57. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  58. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  59. each of the Count operations that is performed.
  60. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  61. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  62. incremented for each of the Count operations that is performed. The read or
  63. write operation is performed Count times on the same Address.
  64. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  65. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  66. incremented for each of the Count operations that is performed. The read or
  67. write operation is performed Count times from the first element of Buffer.
  68. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  69. @param[in] Width Signifies the width of the I/O or Memory operation.
  70. @param[in] Address The base address of the I/O operation.
  71. @param[in] Count The number of I/O operations to perform. The number of
  72. bytes moved is Width size * Count, starting at Address.
  73. @param[in] Buffer For read operations, the destination buffer to store the results.
  74. For write operations, the source buffer from which to write data.
  75. @retval EFI_SUCCESS The data was read from or written to the PI system.
  76. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  77. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  78. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  79. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  80. and Count is not valid for this PI system.
  81. **/
  82. EFI_STATUS
  83. EFIAPI
  84. CpuMemoryServiceWrite (
  85. IN EFI_CPU_IO2_PROTOCOL *This,
  86. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  87. IN UINT64 Address,
  88. IN UINTN Count,
  89. IN VOID *Buffer
  90. );
  91. /**
  92. Reads I/O registers.
  93. The I/O operations are carried out exactly as requested. The caller is responsible
  94. for satisfying any alignment and I/O width restrictions that a PI System on a
  95. platform might require. For example on some platforms, width requests of
  96. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  97. be handled by the driver.
  98. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  99. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  100. each of the Count operations that is performed.
  101. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  102. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  103. incremented for each of the Count operations that is performed. The read or
  104. write operation is performed Count times on the same Address.
  105. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  106. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  107. incremented for each of the Count operations that is performed. The read or
  108. write operation is performed Count times from the first element of Buffer.
  109. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  110. @param[in] Width Signifies the width of the I/O or Memory operation.
  111. @param[in] Address The base address of the I/O operation.
  112. @param[in] Count The number of I/O operations to perform. The number of
  113. bytes moved is Width size * Count, starting at Address.
  114. @param[out] Buffer For read operations, the destination buffer to store the results.
  115. For write operations, the source buffer from which to write data.
  116. @retval EFI_SUCCESS The data was read from or written to the PI system.
  117. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  118. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  119. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  120. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  121. and Count is not valid for this PI system.
  122. **/
  123. EFI_STATUS
  124. EFIAPI
  125. CpuIoServiceRead (
  126. IN EFI_CPU_IO2_PROTOCOL *This,
  127. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  128. IN UINT64 Address,
  129. IN UINTN Count,
  130. OUT VOID *Buffer
  131. );
  132. /**
  133. Write I/O registers.
  134. The I/O operations are carried out exactly as requested. The caller is responsible
  135. for satisfying any alignment and I/O width restrictions that a PI System on a
  136. platform might require. For example on some platforms, width requests of
  137. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  138. be handled by the driver.
  139. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  140. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  141. each of the Count operations that is performed.
  142. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  143. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  144. incremented for each of the Count operations that is performed. The read or
  145. write operation is performed Count times on the same Address.
  146. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  147. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  148. incremented for each of the Count operations that is performed. The read or
  149. write operation is performed Count times from the first element of Buffer.
  150. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  151. @param[in] Width Signifies the width of the I/O or Memory operation.
  152. @param[in] Address The base address of the I/O operation.
  153. @param[in] Count The number of I/O operations to perform. The number of
  154. bytes moved is Width size * Count, starting at Address.
  155. @param[in] Buffer For read operations, the destination buffer to store the results.
  156. For write operations, the source buffer from which to write data.
  157. @retval EFI_SUCCESS The data was read from or written to the PI system.
  158. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  159. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  160. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  161. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  162. and Count is not valid for this PI system.
  163. **/
  164. EFI_STATUS
  165. EFIAPI
  166. CpuIoServiceWrite (
  167. IN EFI_CPU_IO2_PROTOCOL *This,
  168. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  169. IN UINT64 Address,
  170. IN UINTN Count,
  171. IN VOID *Buffer
  172. );
  173. #endif // PCI_CPU_IO2_DXE_H_