SecTempRamDone.c 3.2 KB

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  1. /** @file
  2. Sample to provide SecTemporaryRamDone function.
  3. @copyright
  4. Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <PiPei.h>
  8. #include <Ppi/TemporaryRamDone.h>
  9. #include <Ppi/PlatformInitTempRamExitPpi.h>
  10. #include <Library/DebugLib.h>
  11. #include <Library/PcdLib.h>
  12. #include <Library/FspWrapperPlatformLib.h>
  13. #include <Library/FspWrapperApiLib.h>
  14. #include <Library/PeiServicesTablePointerLib.h>
  15. #include <Guid/FspHeaderFile.h>
  16. #include <Register/ArchitecturalMsr.h>
  17. #define MSR_NEM 0x000002E0
  18. /**
  19. This interface disables temporary memory in SEC Phase.
  20. This is for dispatch mode use. We should properly produce the FSP_TEMP_RAM_EXIT_PPI and then call
  21. that instead, but the FSP does not produce that PPI
  22. **/
  23. VOID
  24. EFIAPI
  25. SecPlatformDisableTemporaryMemoryDispatchHack (
  26. VOID
  27. )
  28. {
  29. UINT64 MsrValue;
  30. UINT64 MtrrDefaultType;
  31. MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
  32. //
  33. // Force and INVD.
  34. //
  35. AsmInvd ();
  36. //
  37. // Disable MTRRs.
  38. //
  39. DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
  40. MtrrDefaultType = DefType.Uint64;
  41. DefType.Bits.E = 0;
  42. AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
  43. //
  44. // Force and INVD to prevent MCA error.
  45. //
  46. AsmInvd ();
  47. //
  48. // Clear NEM Run and NEM Setup bits individually.
  49. //
  50. MsrValue = AsmReadMsr64 (MSR_NEM);
  51. MsrValue &= ~((UINT64) BIT1);
  52. AsmWriteMsr64 (MSR_NEM, MsrValue);
  53. MsrValue &= ~((UINT64) BIT0);
  54. AsmWriteMsr64 (MSR_NEM, MsrValue);
  55. //
  56. // Restore MTRR default setting
  57. //
  58. AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrDefaultType);
  59. }
  60. /**
  61. This interface disables temporary memory in SEC Phase.
  62. **/
  63. VOID
  64. EFIAPI
  65. SecPlatformDisableTemporaryMemory (
  66. VOID
  67. )
  68. {
  69. EFI_STATUS Status;
  70. VOID *TempRamExitParam;
  71. CONST EFI_PEI_SERVICES **PeiServices;
  72. PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
  73. DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
  74. PeiServices = GetPeiServicesTablePointer ();
  75. ASSERT (PeiServices != NULL);
  76. if (PeiServices == NULL) {
  77. return ;
  78. }
  79. ASSERT ((*PeiServices) != NULL);
  80. if ((*PeiServices) == NULL) {
  81. return;
  82. }
  83. Status = (*PeiServices)->LocatePpi (
  84. PeiServices,
  85. &gPlatformInitTempRamExitPpiGuid,
  86. 0,
  87. NULL,
  88. (VOID **) &PlatformInitTempRamExitPpi
  89. );
  90. ASSERT_EFI_ERROR (Status);
  91. if (EFI_ERROR (Status)) {
  92. return;
  93. }
  94. Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
  95. ASSERT_EFI_ERROR (Status);
  96. if (PcdGet8 (PcdFspModeSelection) == 1) {
  97. //
  98. // FSP API mode
  99. //
  100. TempRamExitParam = UpdateTempRamExitParam ();
  101. Status = CallTempRamExit (TempRamExitParam);
  102. DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
  103. ASSERT_EFI_ERROR (Status);
  104. } else {
  105. SecPlatformDisableTemporaryMemoryDispatchHack ();
  106. }
  107. Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
  108. ASSERT_EFI_ERROR(Status);
  109. return ;
  110. }