SioRegs.h 7.8 KB

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  1. /** @file
  2. @copyright
  3. Copyright 2017 - 2021 Intel Corporation. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _SIO_REG_H_
  7. #define _SIO_REG_H_
  8. typedef struct {
  9. UINT8 Index;
  10. UINT8 Value;
  11. } SIO_INDEX_DATA;
  12. #define REG_LOGICAL_DEVICE 0x07
  13. #define ACTIVATE 0x30
  14. //
  15. // COM (Serial) Port Base address
  16. //
  17. #define SIO_BASE_COM1 0x3F8
  18. #define SIO_BASE_COM2 0x2F8
  19. #define BASE_ADDRESS_HIGH0 0x60
  20. #define BASE_ADDRESS_LOW0 0x61
  21. #define PRIMARY_INTERRUPT_SELECT 0x70
  22. #define INTERRUPT_TYPE 0x71
  23. //
  24. //ASPEED AST2500 register
  25. //
  26. #define ASPEED2500_SIO_INDEX_PORT 0x2E
  27. #define ASPEED2500_SIO_DATA_PORT (ASPEED2500_SIO_INDEX_PORT+1)
  28. #define ASPEED2500_SIO_UART1 0x02
  29. #define ASPEED2500_SIO_UART2 0x03
  30. #define ASPEED2500_SIO_SMI 0x0D
  31. #define ASPEED2500_SIO_MAILBOX 0x0E
  32. #define SCU7C 0x1e6e207c
  33. #define ASPEED2500_SIO_UNLOCK 0xA5
  34. #define ASPEED2500_SIO_LOCK 0xAA
  35. //
  36. // Port address for PILOT-IV
  37. //
  38. #define PILOTIV_CHIP_ID 0x03
  39. #define PILOTIV_SIO_INDEX_PORT 0x2E
  40. #define PILOTIV_SIO_DATA_PORT (PILOTIV_SIO_INDEX_PORT+1)
  41. #define PILOTIV_SIO_UNLOCK 0x5A
  42. #define PILOTIV_SIO_LOCK 0xA5
  43. #define PILOTIV_UNLOCK 0x5A
  44. #define PILOTIV_LOCK 0xA5
  45. #define PILOTIV_SIO_PSR 0x00
  46. #define PILOTIV_SIO_COM2 0x01
  47. #define PILOTIV_SIO_COM1 0x02
  48. #define PILOTIV_SIO_SWCP 0x03
  49. #define PILOTIV_SIO_GPIO 0x04
  50. #define PILOTIV_SIO_WDT 0x05
  51. #define PILOTIV_SIO_KCS3 0x08
  52. #define PILOTIV_SIO_KCS4 0x09
  53. #define PILOTIV_SIO_KCS5 0x0A
  54. #define PILOTIV_SIO_BT 0x0B
  55. #define PILOTIV_SIO_SMIC 0x0C
  56. #define PILOTIV_SIO_MAILBOX 0x0D
  57. #define PILOTIV_SIO_RTC 0x0E
  58. #define PILOTIV_SIO_SPI 0x0F
  59. #define PILOTIV_SIO_TAP 0x10
  60. //
  61. // Register for Pilot IV
  62. //
  63. #define PILOTIV_CHIP_ID_REG 0x20
  64. #define PILOTIV_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  65. #define PILOTIV_ACTIVATE ACTIVATE
  66. #define PILOTIV_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
  67. #define PILOTIV_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
  68. #define PILOTIV_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
  69. #define PILOTIV_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
  70. #define PILOTIV_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
  71. //
  72. // Port address for PC8374
  73. //
  74. #define PC8374_CHIP_ID 0xF1
  75. #define PC8374_SIO_INDEX_PORT 0x02E
  76. #define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
  77. //
  78. // Logical device in PC8374
  79. //
  80. #define PC8374_SIO_FLOPPY 0x00
  81. #define PC8374_SIO_PARA 0x01
  82. #define PC8374_SIO_COM2 0x02
  83. #define PC8374_SIO_COM1 0x03
  84. #define PC8374_SIO_MOUSE 0x05
  85. #define PC8374_SIO_KYBD 0x06
  86. #define PC8374_SIO_GPIO 0x07
  87. //
  88. // Registers specific for PC8374
  89. //
  90. #define PC8374_CLOCK_SELECT 0x2D
  91. #define PC8374_CLOCK_CONFIG 0x29
  92. //
  93. // Registers for PC8374
  94. //
  95. #define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  96. #define PC8374_ACTIVATE ACTIVATE
  97. #define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
  98. #define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
  99. #define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
  100. #define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
  101. #define PC8374_CHIP_ID_REG 0x20
  102. #define PC87427_SERVERIO_CNF2 0x22
  103. //
  104. // Port address for NCT5104D
  105. //
  106. #define NCT5104D_SIO_INDEX_PORT 0x4E
  107. #define NCT5104D_SIO_DATA_PORT (NCT5104D_SIO_INDEX_PORT+1)
  108. //
  109. // Registers for NCT5104D
  110. //
  111. #define NCT5104D_CHIP_ID_REG 0x20
  112. #define NCT5104D_CHIP_ID 0xC4
  113. #define NCT5104D_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  114. #define NCT5104D_ACTIVATE ACTIVATE
  115. #define NCT5104D_SIO_UARTA 2
  116. #define NCT5104D_SIO_COM1 3
  117. #define NCT5104D_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
  118. #define NCT5104D_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
  119. #define NCT5104D_WAKEUP_ON_IRQ_EN 0x70
  120. #define NCT5104D_ENTER_THE_EXTENDED_FUNCTION_MODE 0x87
  121. #define NCT5104D_EXIT_THE_EXTENDED_FUNCTION_MODE 0xAA
  122. //
  123. // Port address for W83527
  124. //
  125. #define W83527_SIO_INDEX_PORT 0x02E
  126. #define W83527_SIO_DATA_PORT (W83527_SIO_INDEX_PORT+1)
  127. //
  128. // Logical device in W83527
  129. //
  130. #define W83527_SIO_KYBD 0x05
  131. #define W83527_SIO_WDTO 0x08
  132. #define W83527_SIO_GPIO 0x09
  133. #define W83527_SIO_ACPI 0x0A
  134. #define W83527_SIO_HWM 0x0B
  135. #define W83527_SIO_PCEI 0x0C
  136. //
  137. // Registers for W83527
  138. //
  139. #define W83527_EXT_MODE_START 0x87
  140. #define W83527_EXT_MODE_STOP 0xAA
  141. #define W83527_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  142. #define W83527_ACTIVATE_REG 0x30
  143. #define W83527_ACTIVATE ACTIVATE
  144. #define W83527_CHIP_ID_REG 0x20
  145. #define W83527_CHIP_ID 0xB0
  146. #define W83527_CLOCK_REG 0x24
  147. #define W83527_KBC_BASE1_HI_ADDR_REG 0x60
  148. #define W83527_KBC_BASE1_LO_ADDR_REG 0x61
  149. #define W83527_KBC_BASE2_HI_ADDR_REG 0x62
  150. #define W83527_KBC_BASE2_LO_ADDR_REG 0x63
  151. #define W83527_KBC_BASE1_HI_ADDR 0x00
  152. #define W83527_KBC_BASE1_LO_ADDR 0x60
  153. #define W83527_KBC_BASE2_HI_ADDR 0x00
  154. #define W83527_KBC_BASE2_LO_ADDR 0x64
  155. #define W83527_KBC_KB_IRQ_REG 0x70
  156. #define W83527_KBC_KB_IRQ 0x01
  157. #define W83527_KBC_MS_IRQ_REG 0x72
  158. #define W83527_KBC_MS_IRQ 0x0C
  159. #define W83527_KBC_CFG_REG 0xF0
  160. #define W83527_KBC_CFG 0x83
  161. #define W83527_KBC_CLOCK 0x01
  162. #define W83527_EXT_MODE_START 0x87
  163. #define W83527_EXT_MODE_END 0xAA
  164. //
  165. // Select Clock for W83527, 0 / 1 for 24MHz / 48MHz
  166. //
  167. #define W83527_CLOCK_BIT 0x06
  168. #define W83527_CLOCK 0x01
  169. //
  170. // Initialize Key Board Controller
  171. //
  172. #define W83527_KeyBoard 1
  173. //
  174. // Pilot II Mailbox Data Register definitions
  175. //
  176. #define MBDAT00_OFFSET 0x00
  177. #define MBDAT01_OFFSET 0x01
  178. #define MBDAT02_OFFSET 0x02
  179. #define MBDAT03_OFFSET 0x03
  180. #define MBDAT04_OFFSET 0x04
  181. #define MBDAT05_OFFSET 0x05
  182. #define MBDAT06_OFFSET 0x06
  183. #define MBDAT07_OFFSET 0x07
  184. #define MBDAT08_OFFSET 0x08
  185. #define MBDAT09_OFFSET 0x09
  186. #define MBDAT10_OFFSET 0x0A
  187. #define MBDAT11_OFFSET 0x0B
  188. #define MBDAT12_OFFSET 0x0C
  189. #define MBDAT13_OFFSET 0x0D
  190. #define MBDAT14_OFFSET 0x0E
  191. #define MBDAT15_OFFSET 0x0F
  192. #define MBST0_OFFSET 0x10
  193. #define MBST1_OFFSET 0x11
  194. //
  195. // If both are there, use the default one
  196. //
  197. #define ASPEED_EXIST BIT4
  198. #define NCT5104D_EXIST BIT3
  199. #define W83527_EXIST BIT2
  200. #define PC8374_EXIST BIT1
  201. #define PILOTIV_EXIST BIT0
  202. #define DEFAULT_SIO PILOTIV_EXIST
  203. #define DEFAULT_KDB PC8374_EXIST
  204. #define IPMI_DEFAULT_SMM_IO_BASE 0xca2
  205. #define PILOTIV_SWC_BASE_ADDRESS 0xA00
  206. #define PILOTIV_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
  207. #define PILOTIV_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
  208. #define PILOTIV_GPE1_BLK_BASE_ADDRESS 0x0A86
  209. #define PILOTIV_KCS3_DATA_BASE_ADDRESS 0x0CA4
  210. #define PILOTIV_KCS3_CMD_BASE_ADDRESS 0x0CA5
  211. #define PILOTIV_KCS4_DATA_BASE_ADDRESS 0x0CA2
  212. #define PILOTIV_KCS4_CMD_BASE_ADDRESS 0x0CA3
  213. #define PILOTIV_MAILBOX_BASE_ADDRESS 0x0600
  214. #define PILOTIV_MAILBOX_MASK 0xFFE0
  215. #endif