UbaIioConfigLib.h 9.2 KB

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  1. /** @file
  2. UBA IIO Config Library Header File.
  3. @copyright
  4. Copyright 2012 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _UBA_IIO_CONFIG_LIB_H
  8. #define _UBA_IIO_CONFIG_LIB_H
  9. #include <Base.h>
  10. #include <Uefi.h>
  11. #include <IioPlatformData.h>
  12. #define PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'I', 'O')
  13. #define PLATFORM_IIO_CONFIG_UPDATE_VERSION 01
  14. #define PLATFORM_IIO_CONFIG_UPDATE_VERSION_2 02
  15. #define PLATFORM_IIO_CONFIG_UPDATE_VERSION_3 03
  16. #define PLATFORM_IIO_CONFIG_UPDATE_VERSION_UNSUPPORTED 0x20
  17. // {EB35ED63-EACA-4e29-9516-7EDF1F818837}
  18. #define PLATFORM_IIO_CONFIG_DATA_GUID \
  19. { 0xeb35ed63, 0xeaca, 0x4e29, { 0x95, 0x16, 0x7e, 0xdf, 0x1f, 0x81, 0x88, 0x37 } }
  20. // {3093F83B-5934-473e-8523-24BF297EE684}
  21. #define PLATFORM_IIO_CONFIG_DATA_GUID_1 \
  22. { 0x3093f83b, 0x5934, 0x473e, { 0x85, 0x23, 0x24, 0xbf, 0x29, 0x7e, 0xe6, 0x84 } }
  23. // {1C5267A4-634B-4bf2-BFF8-9A1164E6D198}
  24. #define PLATFORM_IIO_CONFIG_DATA_GUID_2 \
  25. { 0x1c5267a4, 0x634b, 0x4bf2, { 0xbf, 0xf8, 0x9a, 0x11, 0x64, 0xe6, 0xd1, 0x98 } }
  26. // {1E486CCA-048E-4702-B28C-0B677201683A}
  27. #define PLATFORM_IIO_CONFIG_DATA_GUID_3 \
  28. { 0x1e486cca, 0x48e, 0x4702, { 0xb2, 0x8c, 0xb, 0x67, 0x72, 0x1, 0x68, 0x3a } }
  29. // {6FE6C559-4F35-4111-98E1-332A251512F3}
  30. #define PLATFORM_IIO_CONFIG_DATA_DXE_GUID \
  31. { 0x6fe6c559, 0x4f35, 0x4111, { 0x98, 0xe1, 0x33, 0x2a, 0x25, 0x15, 0x12, 0xf3 } }
  32. // {0F722F2A-650F-448a-ABB7-04EECD75BB30}
  33. #define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_1 \
  34. { 0xf722f2a, 0x650f, 0x448a, { 0xab, 0xb7, 0x4, 0xee, 0xcd, 0x75, 0xbb, 0x30 } }
  35. // {EBD11A00-8C5C-4f71-BB9E-5394032B01F4}
  36. #define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_2 \
  37. { 0xebd11a00, 0x8c5c, 0x4f71, { 0xbb, 0x9e, 0x53, 0x94, 0x3, 0x2b, 0x1, 0xf4 } }
  38. // {123BD082-3201-465c-B139-0CB8C77208F8}
  39. #define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_3 \
  40. { 0x123bd082, 0x3201, 0x465c, { 0xb1, 0x39, 0xc, 0xb8, 0xc7, 0x72, 0x8, 0xf8 } }
  41. #define ENABLE 1
  42. #define DISABLE 0
  43. #define NO_SLT_IMP 0xFF
  44. #define SLT_IMP 1
  45. #define HIDE 1
  46. #define NOT_HIDE 0
  47. #define VPP_PORT_MAX 0xFF
  48. #define VPP_ADDR_MAX 0xFF
  49. #define PWR_VAL_MAX 0xFF
  50. #define PWR_SCL_MAX 0xFF
  51. #define SMB_ADDR_MAX 0xFF
  52. #define SMB_DATA_MAX 0xFF
  53. #define NO_BIF_INPUT 0xFF
  54. #define NOT_EXIST 0xFF
  55. typedef
  56. EFI_STATUS
  57. (*IIO_VAR_UPDATE_CALLBACK) (
  58. IN IIO_GLOBALS *IioGlobalData
  59. );
  60. typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY {
  61. UINT8 Socket;
  62. UINT8 IouNumber;
  63. UINT8 Bifurcation;
  64. } IIO_BIFURCATION_DATA_ENTRY;
  65. typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY_EX {
  66. UINT8 Socket;
  67. UINT8 IouNumber;
  68. UINT8 Bifurcation;
  69. UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card - use to dynamically determine PCIe bifurcation
  70. UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension card - use to dynamically determine PCIe bifurcation
  71. UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to communicate to different group of devices
  72. UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to select the channel that will be used to communicate to the different group of devices.
  73. } IIO_BIFURCATION_DATA_ENTRY_EX;
  74. typedef struct _PLATFORM_IIO_SLOT_ENTRY {
  75. UINT8 PortIndex;
  76. UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented
  77. BOOLEAN InterLockPresent;
  78. UINT8 SlotPowerLimitScale;
  79. UINT8 SlotPowerLimitValue;
  80. BOOLEAN HotPlugCapable;
  81. UINT8 VppPort; // 0xff if Vpp not enabled
  82. UINT8 VppAddress;
  83. BOOLEAN PcieSSDCapable;
  84. UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled
  85. UINT8 PcieSSDVppAddress;
  86. BOOLEAN Hidden;
  87. } IIO_SLOT_CONFIG_DATA_ENTRY;
  88. typedef struct _PLATFORM_IIO_SLOT_ENTRY_EX {
  89. UINT8 PortIndex; //( {1,2,3,4} = {1A,,1B,,1C,1D} ), ( {5,6,7,8} = {2A,2B,2C,2D} ), ( {9,10,11,12} = {3A,3B,3C,3D}),...
  90. UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented
  91. BOOLEAN InterLockPresent; // Yes / No
  92. UINT8 SlotPowerLimitScale;
  93. UINT8 SlotPowerLimitValue;
  94. BOOLEAN HotPlugCapable; // Yes / No
  95. UINT8 VppPort; // 0xff if Vpp not enabled
  96. UINT8 VppAddress;
  97. BOOLEAN PcieSSDCapable; // Yes / No
  98. UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled
  99. UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled
  100. BOOLEAN Hidden; // deprecate this as it should be purely based on bifurcation
  101. BOOLEAN CommonClock; // Yes / No - whether the both side of the link are in same clock domain or not
  102. BOOLEAN SRIS; // Yes / No - in case of distinct clocking whether the separate ref. clk supports SSC or not
  103. BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is connected to Uplink port of another chip
  104. BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to bifurcate the retimers explicitly
  105. UINT8 RetimerSMBusAddress; // SMBus address to read the retimer status and bifurcate if required
  106. UINT8 RetimerSMBusChannel; // SMBus Mux channel to read the retimer status and bifurcate if required
  107. UINT8 RetimerWidth; // Retimer width to determine adjacent Retimers for the same PCIe slot
  108. UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to communicate to different group of devices
  109. UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to select the channel that will be used to communicate to the different group of devices.
  110. BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension card which are supported in board thro' SMBus address (typically BW5)
  111. UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card - use to dynamically determine PCIe bifurcation
  112. UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension card - use to dynamically determine PCIe bifurcation
  113. BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension card (BW5), or No
  114. UINT8 ExtnCardRetimerSMBusAddress; // SMBus address to read the retimer status and bifurcate if required
  115. UINT8 ExtnCardRetimerWidth; // use to determine adjacent Retimers to the x16 PCIe slot on which this Riser is mounted
  116. BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indicates slot in which this PCIe extn. Card is mounted
  117. UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled
  118. UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled
  119. UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercepted between the PCIe port and the slot device. Retimer may appear mutually exclusive.
  120. } IIO_SLOT_CONFIG_DATA_ENTRY_EX;
  121. typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE {
  122. UINT32 Signature;
  123. UINT32 Version;
  124. IIO_BIFURCATION_DATA_ENTRY *IioBifurcationTablePtr;
  125. UINTN IioBifurcationTableSize;
  126. IIO_VAR_UPDATE_CALLBACK CallUpdate;
  127. IIO_SLOT_CONFIG_DATA_ENTRY *IioSlotTablePtr;
  128. UINTN IioSlotTableSize;
  129. } PLATFORM_IIO_CONFIG_UPDATE_TABLE;
  130. typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX {
  131. UINT32 Signature;
  132. UINT32 Version;
  133. IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr;
  134. UINTN IioBifurcationTableSize;
  135. IIO_VAR_UPDATE_CALLBACK CallUpdate;
  136. IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr;
  137. UINTN IioSlotTableSize;
  138. } PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX;
  139. typedef struct {
  140. UINT8 MuxSmbAddress;
  141. UINT8 MuxSmbChannel;
  142. UINT8 SmbAddress0;
  143. UINT8 SmbAddress1;
  144. UINT8 RegOffset;
  145. UINT8 RegValue;
  146. } MUX_SMB_ADDR;
  147. typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_3 {
  148. UINT32 Signature;
  149. UINT32 Version;
  150. IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr;
  151. UINTN IioBifurcationTableSize;
  152. IIO_VAR_UPDATE_CALLBACK CallUpdate;
  153. IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr;
  154. UINTN IioSlotTableSize;
  155. MUX_SMB_ADDR *RetimerInitTablePtr;
  156. } PLATFORM_IIO_CONFIG_UPDATE_TABLE_3;
  157. typedef struct {
  158. UINT8 PortHide[8];
  159. } PCIE_PORT_HIDE_TABLE;
  160. EFI_STATUS
  161. PlatformIioConfigInit (
  162. IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable,
  163. IN OUT UINT8 *BifurcationEntries,
  164. IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable,
  165. IN OUT UINT8 *SlotEntries
  166. );
  167. EFI_STATUS
  168. PlatformIioConfigInit2 (
  169. IN UINT8 SkuPersonalityType,
  170. IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable,
  171. IN OUT UINT8 *BifurcationEntries,
  172. IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable,
  173. IN OUT UINT8 *SlotEntries
  174. );
  175. EFI_STATUS
  176. PlatformUpdateIioConfig (
  177. IN IIO_GLOBALS *IioGlobalData
  178. );
  179. EFI_STATUS
  180. PlatformUpdateIioConfig_EX (
  181. IN IIO_GLOBALS *IioGlobalData
  182. );
  183. #endif //_UBA_IIO_CONFIG_LIB_H