GopConfigLib.h 63 KB

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  1. /** @file
  2. Header file for GOP Configuration Library
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _GOP_CONFIG_LIB_H_
  7. #define _GOP_CONFIG_LIB_H_
  8. #include <Library/DebugLib.h>
  9. #include <Uefi/UefiBaseType.h>
  10. #pragma pack(1)
  11. #define GOP_CONFIG_VBT_REVISION 0xC1
  12. #define ChildStruct_MAX 8 ///< Maximum number of child structures in VBT
  13. #define CompressionStruct_MAX 2 ///< Maximum number of compression parameter structures in VBT.
  14. #define NO_DEVICE 0x00 ///< Defines a null display class.
  15. #define DISPLAY_PORT_ONLY 0x68C6 ///< Defines a display class of Integrated Display Port Only
  16. #define DISPLAY_PORT_HDMI_DVI_COMPATIBLE 0x60D6 ///< Defines a display class of Integrated DisplayPort with HDMI/DVI Compatible
  17. #define DISPLAY_PORT_DVI_COMPATIBLE 0x68D6 ///< Defines a display class of Integrated DisplayPort with DVI Compatible
  18. #define HDMI_DVI 0x60D2 ///< Defines a display class of Integrated HDMI/DVI
  19. #define DVI_ONLY 0x68D2 ///< Defines a display class of Integrated DVI Only
  20. #define MIPI_ONLY 0x1400
  21. #define eDP_ONLY 0x1806 ///< Defines a display class of eDP only
  22. #define AUX_CHANNEL_A 0x40
  23. #define AUX_CHANNEL_B 0x10
  24. #define AUX_CHANNEL_C 0x20
  25. #define AUX_CHANNEL_D 0x30
  26. #define NO_PORT 0x00 ///< Defines a output port NA
  27. #define HDMI_B 0x01 ///< Defines a output port HDMI-B
  28. #define HDMI_C 0x02 ///< Defines a output port HDMI-C
  29. #define HDMI_D 0x03 ///< Defines a output port HDMI-D
  30. #define HDMI_F 0x0E ///< Defines a output port HDMI-D
  31. #define DISPLAY_PORT_A 0x0A ///< Defines a output port DisplayPort A
  32. #define DISPLAY_PORT_B 0x07 ///< Defines a output port DisplayPort B
  33. #define DISPLAY_PORT_C 0x08 ///< Defines a output port DisplayPort C
  34. #define DISPLAY_PORT_D 0x09 ///< Defines a output port DisplayPort D
  35. #define DISPLAY_PORT_E 0x0B ///< Defines a output port DisplayPort E
  36. #define DISPLAY_PORT_F 0x0D ///< Defines a output port DisplayPort F
  37. #define PORT_MIPI_A 0x15 ///< Mipi Port A
  38. #define PORT_MIPI_C 0x17 ///< Mipi Port C
  39. typedef struct {
  40. UINT16 Dclk; // DClk in 10 KHz
  41. UINT8 HActive; // HActive [7:0]
  42. UINT8 HBlank; // HBlank [7:0]
  43. UINT8 HA_HB_UpperNibble; // Upper nibble = HActive [11:8]
  44. UINT8 VActive; // VActive [7:0]
  45. UINT8 VBlank; // VBlank [7:0]
  46. UINT8 VA_VB_UpperNibble; // Upper nibble = VActive [11:8]
  47. UINT8 HSyncOffset; // HSync offset from blank start LSB
  48. UINT8 HPulseWidth; // HSync Pulse Width, LSB
  49. UINT8 VsyncOffset_VpulseWidth_LSB; // Bits 7:4 = VSync offset [3:0]
  50. UINT8 HSO_HSPW_V_High; // Bits 7:6 = HSync Offset [9:8]
  51. UINT8 HorImageSize; // Horizontal Image Size
  52. UINT8 VerImageSize; // Vertical Image Size
  53. UINT8 HIS_VIS_High; // UpperLmtH_V Upper limits of H. and V. image size
  54. UINT8 HBorder; // Horizontal Border
  55. UINT8 VBorder; // Vertical Border
  56. UINT8 Flags; // Flags
  57. } DTD_STRUCTURE; // 18 Bytes
  58. typedef struct {
  59. UINT16 XRes;
  60. UINT16 YRes;
  61. UINT32 SerialNo;
  62. UINT8 Week;
  63. UINT8 Year;
  64. } PID_DATA; // 10 Bytes
  65. //
  66. // VBT Header
  67. //
  68. /**
  69. This structure defines the VBT Header.
  70. **/
  71. typedef struct {
  72. UINT8 Product_String[20]; ///< "$VBT_Cannonlake" is the product string
  73. UINT16 Version_Num; ///< Defines the VBT Header version number.
  74. UINT16 Header_Size; ///< Defines the size of VBT Header.
  75. UINT16 Table_Size; ///< Defines the size of complete VBT.
  76. UINT8 Checksum; ///< Defines the checksum of entire VBT
  77. UINT8 Reserved1; ///< Reserved field 1 of 1 byte.
  78. UINT32 Bios_Data_Offset; ///< Defines the offset of VBT Data block.
  79. UINT32 Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks.
  80. } VBT_HEADER;
  81. /**
  82. This structure defines the VBT BIOS Data Block Header
  83. **/
  84. typedef struct {
  85. UINT8 BDB_Signature[16]; ///< Defines the Bios Data Block signature "BIOS_DATA_BLOCK".
  86. UINT16 BDB_Version; ///< Defines the VBT (data) version.
  87. UINT16 BDB_Header_Size; ///< Defines the size of VBT Bios data block header.
  88. UINT16 BDB_Size; ///< Defines the size of Bios data block.
  89. } VBT_BIOS_DATA_HEADER;
  90. /**
  91. This structure defines the BMP Signon Message and Copyright Message Structure
  92. **/
  93. typedef struct {
  94. UINT8 BlockId; ///< Defines Block ID : 254
  95. UINT16 BlockSize; ///< Defines the size of BMP Signon block.
  96. UINT16 Bmp_BIOS_Size; ///< Defines the BIOS size 32k/48k/64k.
  97. UINT8 BIOS_Type; ///< Defines the type of BIOS desktop or mobile.
  98. UINT8 RelStatus; ///< Defines the release status of the current GOP driver.
  99. UINT8 BIOS_HW; ///< Defines the Hardware i.e. Cannonlake.
  100. UINT8 INT_HW; ///< Defines the integrated hardware supported eDP/HDMI/DP.
  101. UINT8 Build_Number[4]; ///< Defines the build number string.
  102. UINT8 SignOn[155]; ///< Defines the sign on message.
  103. UINT8 CopyRight[61]; ///< Defines the copyright message.
  104. } BMP_STRUCTURE_SIGNON;
  105. /**
  106. This structure defines the BMP General Bits
  107. **/
  108. typedef struct {
  109. UINT16 bmp_BIOS_CS; ///< Defines the start of BIOS code segment
  110. UINT8 bmp_DOS_Boot_Mode; ///< Defines the mode number to set when DOS is boot
  111. UINT8 bmp_BW_Percent; ///< Set percentage of total memory BW
  112. UINT8 bmp_Popup_Mem_Size; ///< Default Popup memory size in KB
  113. UINT8 bmp_Resize_PCI_BIOS; ///< BIOS size granularity in 0.5 KB
  114. UINT8 Switch_CRT_To_DDC2; ///< Obsolete field: Is the CRT already switched to DDC2
  115. UINT8 bmp_Allow_Config; ///< Bit 1 : 1, Enable aspect ratio for DOS
  116. ///< Bit 0 : 1, Allow boot to DVI even if it is not attached.
  117. } BMPGEN;
  118. /**
  119. This structure defines Block 254 (BMP structure)
  120. **/
  121. typedef struct {
  122. BMP_STRUCTURE_SIGNON bmp_Signon_Message; ///< Instance of signon and copyright message structure
  123. BMPGEN bmp_General_Bytes; ///< Instance of BMP General Bits structure.
  124. } BLOCK254_BMP_Structure;
  125. /**
  126. This structure defines Block 1 (General Bytes Definitions)
  127. **/
  128. typedef struct {
  129. UINT8 BlockId; ///< Defines the Block ID (1)
  130. UINT16 BlockSize; ///< Defines the size of General bytes definition block.
  131. /**
  132. BMP General Bit Definitions 1\n
  133. Bit 7 = DVO A color flip bit
  134. = 0, No DVO A color flip
  135. = 1, Flip DVO A color
  136. Bits 6:4 = Clear screen (CLS) after Signon
  137. = 000, No CLS
  138. = 001, 0.5 sec pause and then CLS
  139. = 010, 1.0 sec pause and then CLS
  140. = 011, 1.5 sec pause and then CLS
  141. = 100, 2.0 sec pause and then CLS
  142. = 101, 2.5 sec pause and then CLS
  143. = 110, 3.0 sec pause and then CLS
  144. = 111, 3.5 sec pause and then CLS
  145. Bit 3 = 1 Enable Display Signon
  146. Bit 2 = 1 Enable Flex-aim Support
  147. Bits 1:0 = Flat panel fitting enabling
  148. = 00, Centering
  149. = 01, Reserved
  150. = 10, Aspect scaling
  151. = 11, Fullscreen
  152. **/
  153. union {
  154. UINT8 Value;
  155. struct {
  156. UINT8 PanelFitterEnabling:2;
  157. UINT8 FlexAimSupportEnable:1;
  158. UINT8 DisplaySignonEnable:1;
  159. UINT8 ClearScreenTime:3;
  160. UINT8 DvoAColorFlipEnable:1;
  161. } Bits;
  162. } bmp_Bits_1;
  163. /**
  164. BMP General Bit Definitions\n
  165. Bit 7 = Hot plug support
  166. = 0, Hot plug disabled
  167. = 1, Hot plug enabled
  168. Bit 6 = Dynamic CD clock feature
  169. = 0, Dynamic CD clock feature is disabled
  170. = 1, Dynamic CD clock feature is enabled
  171. Bit 5 = Underscan support for VGA timings
  172. Bit 4 = Disable SSC in Dual Display Twin Mode. (This field is obsolete now. Kept for VBIOS only.)
  173. = 0, No
  174. = 1, Yes
  175. Bit 3 = LFP power state on override by 5f64h,08h
  176. = 0, No Override
  177. = 1, Override
  178. Bit 2 = Internal LVDS SSC frequency. (This field is obsolete now. Kept for VBIOS only.)
  179. = 0, 96/120MHz
  180. = 1, 100MHz
  181. Bit 1 = internal LVDS SSC (Spread Spectrum Clock) (This field is obsolete now. Kept for VBIOS only.)
  182. = 0, Disabled
  183. = 1, Enabled
  184. Bit 0 = KvmrSessionEnable.
  185. = 0, Disabled
  186. = 1, Enabled
  187. **/
  188. union {
  189. UINT8 Value;
  190. struct {
  191. UINT8 KvmrSessionEnable:1;
  192. UINT8 Reserved_1:5;
  193. UINT8 DynamicCdClockEnable:1;
  194. UINT8 HotPlugEnable:1;
  195. } Bits;
  196. } bmp_Bits_2;
  197. /**
  198. BMP General Bit Definitions 3\n
  199. Bit 7 = Ignore strap status
  200. = 0 Do not ignore
  201. = 1 Ignore
  202. Bit 6 = Panel Timing algorithm
  203. = 0 Preferred timings
  204. = 1 Best fit timings
  205. Bit 5 Copy iLFP DTD to SDVO LVDS DTD
  206. = 0 Don't copy DTD
  207. = 1 Copy DTD to
  208. Bit 4 = VBIOS normal/extd. DT mode
  209. = 0 Normal mode
  210. = 1 DUAL mode
  211. Bit 3 = FDI RX Polarity
  212. = 0 Normal
  213. = 1 Inverted
  214. Bit 2 = Enable 180 Degree Rotation
  215. = 0 Disable
  216. = 1 Enable
  217. Bit 1 = Single DVI-I connector for CRT and DVI display: Obsolete field
  218. = 0 Disabled
  219. = 1 Enabled
  220. Bit 0 = Smooth Vision
  221. = 0 Disabled
  222. = 1 Enabled
  223. **/
  224. union {
  225. UINT8 Value;
  226. struct {
  227. UINT8 Reserved1:1;
  228. UINT8 SingleDviiCrtConnector:1;
  229. UINT8 Enable180DegRotation:1;
  230. UINT8 FdiRxPolarity:1;
  231. UINT8 Reserved2:4;
  232. } Bits;
  233. } bmp_Bits_3;
  234. UINT8 Reserved; ///< Reserved field. It was Legacy_Monitor_Detect in previous platforms.
  235. /**
  236. Integrated display device support\n
  237. Bits 7:6 = Reserved
  238. Bit 5 = DP SSC Dongle Enable/Disable
  239. Bit 4 = DP SSC Frequency. (This field is obsolete now. Kept for VBIOS only.)
  240. = 0, 96 MHz
  241. = 1, 100 MHz
  242. Bit 3 = DP SSC Enable
  243. = 0, Disable
  244. = 1, Enable
  245. Bit 2 = Integrated EFP support
  246. = 0, Disable
  247. = 1, Enable
  248. Bit 1 = Integrated TV support. (This field is obsolete now. Kept for VBIOS only.)
  249. = 0, Disable
  250. = 1, Enable
  251. Bit 0 = Integrated CRT support: Obsolete field
  252. = 0, Disable
  253. = 1, Enable
  254. **/
  255. union {
  256. UINT8 Value;
  257. struct {
  258. UINT8 CrtSupported:1;
  259. UINT8 TvSupported:1;
  260. UINT8 EfpSupported:1;
  261. UINT8 DpSscEnable:1;
  262. UINT8 DpSscFrequency:1;
  263. UINT8 DpDongleSscEnable:1;
  264. UINT8 Reserved1:2;
  265. } Bits;
  266. } Int_Displays_Support;
  267. } VBT_GENERAL1_INFO;
  268. /**
  269. This defines the Structure of PRD Boot Table Entry
  270. **/
  271. typedef struct {
  272. UINT8 AttachBits; ///< Bitmap representing the displays attached currently.
  273. UINT8 BootDev_PipeA; ///< Bitmap representing the display to boot on Pipe A.
  274. UINT8 BootDev_PipeB; ///< Bitmap representing the display to boot on Pipe B.
  275. } PRD_TABLE;
  276. /**
  277. This defines the structure of Block 254 (PRD Boot Table/Child Device List)
  278. **/
  279. typedef struct {
  280. UINT8 BlockId; ///< Defines the Block ID (254)
  281. UINT16 BlockSize; ///< Defines the size of Block 254
  282. PRD_TABLE PRDTable[16]; ///< Defines the Child device list for enumerating child handles.
  283. UINT16 PRD_Boot_Table_Number_Of_Entries; ///< Number of entries in child device list.
  284. } PRD_BOOT_TABLE;
  285. /**
  286. This defines the Structure for a CHILD_STRUCT (used for all the displays).
  287. **/
  288. typedef struct {
  289. UINT16 DeviceHandle; ///< Unique ID indicating the group of display device (LFP/EFP1/EFP2/EFP3/EFP4).
  290. UINT16 DeviceClass; ///< Indicates the class of display device.
  291. UINT8 I2CSpeed; ///< Defines the I2C speed to be used for I2C transaction.
  292. /**
  293. Defines the DP on board redriver configuration.
  294. BIT[7] : Reserved
  295. BIT[6] : Is On Board DP Redriver Present
  296. 0 : No
  297. 1 : Yes
  298. BIT[5:3] : On Board Redriver VSwing Level
  299. 0 : Level 0
  300. 1 : Level 1
  301. 2 : Level 2
  302. 3 : Level 3
  303. Others : Reserved
  304. BIT[2:0] : On Board Redriver PreEmph Level
  305. 0 : Level 0
  306. 1 : Level 1
  307. 2 : Level 2
  308. 3 : Level 3
  309. Others : Reserved
  310. **/
  311. union{
  312. UINT8 Value;
  313. struct {
  314. UINT8 OnBoardPreEmphLevel:3;
  315. UINT8 OnBoardVSwingLevel:3;
  316. UINT8 OnBoardRedriverPresent:1;
  317. UINT8 Reserved:1;
  318. } Bits;
  319. } DpOnBoardRedriver;
  320. /**
  321. Defines the DP on dock redriver configuration.
  322. BIT[7] : Reserved
  323. BIT[6] : Is On Dock DP Redriver Present
  324. 0 : No
  325. 1 : Yes
  326. BIT[5:3] : On Dock Redriver VSwing Level
  327. 0 : Level 0
  328. 1 : Level 1
  329. 2 : Level 2
  330. 3 : Level 3
  331. Others : Reserved
  332. BIT[2:0] : On Dock Redriver PreEmph Level
  333. 0 : Level 0
  334. 1 : Level 1
  335. 2 : Level 2
  336. 3 : Level 3
  337. Others : Reserved
  338. **/
  339. union {
  340. UINT8 Value;
  341. struct {
  342. UINT8 OnDockPreEmphLevel:3;
  343. UINT8 OnDockVSwingLevel:3;
  344. UINT8 OnDockRedriverPresent:1;
  345. UINT8 Reserved:1;
  346. } Bits;
  347. } DpOnDockRedriver;
  348. /**
  349. Defines the HDMI level shifter configuration.
  350. BIT[7:5] : Hdmi Maximum data rate
  351. BIT[4:0] : Hdmi Level shifter value
  352. **/
  353. union{
  354. UINT8 Value;
  355. struct {
  356. UINT8 HdmiLevelShifterValue:5;
  357. UINT8 HdmiMaxDataRateBits:3;
  358. } Bits;
  359. } HdmiLevelShifterConfig;
  360. UINT16 EFPDTDBufferPointer; ///< Pointer to the DTD timing to be used in case of edidless EFP.
  361. /**
  362. Defines the first set of flags.
  363. BIT[7-4] : Reserved
  364. BIT[3] : Dual pipe ganged display support
  365. 0 : Display uses a single pipe/port
  366. 1 : Display uses two distinct pipes/ports.
  367. BIT[2] : Compression Method Select
  368. 0 : Compression using picture parameter set (PPS)
  369. 1 : Compression using Capability parameter set (CPS)
  370. BIT[1] : Compression enable/disable for this display.
  371. 0 : Disabled
  372. 1 : Enabled
  373. BIT[0] : EDID less EFP Enable
  374. 0 : Enable support for EDID less EFP.
  375. 1 : Disable support for EDID less EFP.
  376. **/
  377. union {
  378. UINT8 Value;
  379. struct {
  380. UINT8 EdidlessEfpEnable:1;
  381. UINT8 CompressionEnable:1;
  382. UINT8 CompressionMethod:1;
  383. UINT8 IsDualPortEnabled:1;
  384. UINT8 Reserved:4;
  385. } Bits;
  386. } Flags0;
  387. /**
  388. Defines the compression index field for the display.
  389. BITS[7-4] : Reserved
  390. BITS[3-0] : Compression Structure index in the block 55.
  391. 0x0 : Index 0 in block 55
  392. 0x1 : Index 1 in block 55
  393. 0xF : Not Applicable.
  394. Others : Reserved
  395. **/
  396. union {
  397. UINT8 Value;
  398. struct {
  399. UINT8 IndexInBlock55:4;
  400. UINT8 Reserved:4;
  401. } Bits;
  402. } CompressionStructureIndex;
  403. UINT8 SlaveDdiPort; ///< The DVO port number of slave DDI to be used in case Flags0[3] = 1.
  404. UINT8 Reserved_1; ///< Reserved and might be used in other platforms.
  405. UINT16 AddInOffset; ///< Obsolete field.
  406. UINT8 DVOPort; ///< Specifies the port number of the display device represented in the device class.
  407. UINT8 I2CBus; ///< Specifies the GMBUS or I2C pin pair for add in card.
  408. UINT8 SlaveAddr; ///< Specifies the I2C address of the add in card.
  409. UINT8 DDCBus; ///< Specifies the GMBUS pin pair for EDID read.
  410. UINT16 TimingInfoPtr; ///< Pointer to the buffer where VBIOS stores the EDID of device.
  411. UINT8 DVOCfg; ///< Obsolete field.
  412. /**
  413. Flags 1\n
  414. Bits 7:5 : Reserved
  415. Bit 4 : HPD Sense Invert
  416. 0 : Invert not required (default)
  417. 1 : Invert required
  418. Bit 3 : IBoost feature enable/disable.
  419. 0 : IBoost feature is disabled.
  420. 1 : IBoost feature is enabled.
  421. Bit 2 : Hdmi 2.0 Motherboard Downsuppotred options
  422. 0 : Motherboard Down chip not supported
  423. 1 : Motherboard Down Chip Supported on the Board
  424. Bit 1 : Lane Reversal feature.
  425. 0 : Disable
  426. 1 : Enable
  427. Bit 0 : DP/HDMI routed to dock.
  428. 0 : Disable
  429. 1 : Enable
  430. **/
  431. union {
  432. UINT8 Value;
  433. struct {
  434. UINT8 DockablePort:1;
  435. UINT8 EnableLaneReversal:1;
  436. UINT8 OnBoardLsPconDonglePresent:1;
  437. UINT8 IBoostEnable:1;
  438. UINT8 IsHpdInverted:1;
  439. UINT8 Reserved:3;
  440. } Bits;
  441. } Flags_1;
  442. UINT8 Compatibility; ///< Compatibility is used in VBIOS only. It was used before device class was defined.
  443. UINT8 AUX_Channel; ///< Specifies the aux channel to be used for display port devices.
  444. UINT8 Dongle_Detect; ///< Indicates whether dongle detect is enabled or not.
  445. UINT8 Capabilities; ///< Bits 1-0 indicate pipe capabilities whether display can be used on one pipe or both the pipes.
  446. UINT8 DVOWiring; ///< Obsolete field.
  447. UINT8 MipiBridgeType; ///< MIPI bridge type
  448. UINT16 DeviceClassExtension; ///< Obsolete.
  449. UINT8 DVOFunction; ///< Obsolete.
  450. /**
  451. Flags 2
  452. Bits 7:4 : DP Port trace length from silicon to output port on the board
  453. 0 : Default RVP length
  454. 1 : Short trace length
  455. 2 : Long trace length
  456. Bits 3:2 : Reserved
  457. Bit 1 : Indicates whether this port is Thunderbolt port or not.
  458. 0 : No
  459. 1 : Yes
  460. Bit 0 : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP display
  461. 0 : Disable
  462. 1 : Enable
  463. **/
  464. union {
  465. UINT8 Value;
  466. struct {
  467. UINT8 UsbTypeCDongleEnabled:1; ///< Indicates whether this port is USB type C.
  468. UINT8 IsThunderboltPort:1; ///< Indicates whether this port is Thunderbolt. (ICL+)
  469. UINT8 Reserved:2; ///< Reserved for future use.
  470. UINT8 DpPortTraceLength:4; ///< Dp port trace length from silicon to port.
  471. } Bits;
  472. } Flags_2;
  473. UINT8 DP2XGpioIndex; ///< GPIO index number for the USB type C.
  474. UINT16 DP2XGpioNumber; ///< GPIO number for USB type C.
  475. /**
  476. IBoost magnitude field.
  477. Bits 7:4 : DP Boost magnitude
  478. 0 : 1
  479. 1 : 3
  480. 2 : 7
  481. Others : Reserved for WHL.
  482. Bits 3:0 : HDMI Boost magnitude
  483. 0 : 1
  484. 1 : 3
  485. 2 : 7
  486. Others : Reserved.
  487. **/
  488. union {
  489. UINT8 Value;
  490. struct {
  491. UINT8 DpEdpBoostMagnitude:4;
  492. UINT8 HdmiBoostMagnitude:4;
  493. } Bits;
  494. } BoostMagnitude;
  495. } CHILD_STRUCT;
  496. /**
  497. This structure defines Block 2 (General Bytes Definitions)
  498. **/
  499. typedef struct {
  500. UINT8 BlockId; ///< Defines the Block ID : 2.
  501. UINT16 BlockSize; ///< Defines the size of VBT General Info 2 Block.
  502. UINT8 bmp_CRT_DDC_GMBUS_Pin; ///< Obsolete field: Selects the CRT DDC GMBUS pin pair.
  503. UINT8 bmp_DPMS_Bits; ///< BMP DPMS Bit Definitions.
  504. UINT16 bmp_Boot_Dev_Bits; ///< BMP Boot Device Bit Definitions.
  505. UINT8 SizeChild_Struct; ///< Size of the ChildStruc structure.
  506. CHILD_STRUCT Child_Struct[ChildStruct_MAX]; ///< This array defines all the supported child structures.
  507. } VBT_GENERAL2_INFO;
  508. /**
  509. This defines the structure of Block 3 (Original Display Toggle List)
  510. **/
  511. typedef struct {
  512. UINT8 BlockId; ///< Defines the Block ID : 3
  513. UINT16 BlockSize; ///< Defines the size of Original Display Toggle List Block
  514. UINT8 bmp_Display_Detect; ///< Display must be attached or not
  515. } BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST;
  516. /**
  517. This defines structure of a pointer table.
  518. **/
  519. typedef struct {
  520. UINT16 Offset; ///< Defines the offset of the table from start of BIOS Data block.
  521. UINT16 Size; ///< Defines the size of an entry of the table.
  522. } BMP_TABLE_PTR;
  523. /**
  524. This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers).
  525. **/
  526. typedef struct {
  527. UINT8 BlockId; ///< Defines the Block ID : 252.
  528. UINT16 BlockSize; ///< Defines the size of SBIOS Hooks block.
  529. UINT8 SbiosHooks[18]; ///< This array defines a series of SBIOS hooks. Each entry represents one hook.
  530. BMP_TABLE_PTR BmpTablePtr[26]; ///< This array defines pointers to all the important tables in the VBT.
  531. } BLOCK252_SBIOS_Hook;
  532. /**
  533. This defines the structure of MMIO boot table entry
  534. **/
  535. typedef struct {
  536. UINT32 Register; ///< Defines the MMIO offset of the register.
  537. UINT32 Value; ///< Defines the default value of the register.
  538. } MMIO_BOOT_TABLE;
  539. /**
  540. This structure defines Block 6 (MMIO Register Block)
  541. **/
  542. typedef struct {
  543. UINT8 BlockId; ///< Defines the Block ID : 6
  544. UINT16 BlockSize; ///< Defines the size of MMIO Register Table block.
  545. UINT16 RegTableId; ///< Defines the ID for MMIO register table (0xFFFC).
  546. UINT8 AccessFlag; ///< Defines the flag for data access size (02 for 4 byte read/write).
  547. MMIO_BOOT_TABLE MMIOBootTable[14]; ///< Array containing the MMIO register table.
  548. UINT16 TableEnd; ///< Special value describing End of table (0xFFFF).
  549. } BLOCK06_MMIO_REG_TABLE;
  550. /**
  551. This structure defines Block 7 (IO SW Flag Register Table)
  552. **/
  553. typedef struct {
  554. UINT8 BlockId; ///< Defines Block ID (7).
  555. UINT16 BlockSize; ///< Defines the size of IO SW Flag register table block.
  556. UINT16 RegTableId; ///< Defines the ID for IO SW Flag register table (0xFFFE).
  557. UINT8 GRIndexRegLsb; ///< Defines the read/write size. Value is 0xCE meaning 1 byte without mask.
  558. UINT8 IOSWFlagReg; ///< Defines the offset for the IO SW Flag register.
  559. UINT8 Value; ///< Defines the data/value for the register.
  560. UINT16 TableEnd; ///< Special value describing the end of table (0xFFFF).
  561. } BLOCK07_IOSWFLAG_REG_TABLE;
  562. /**
  563. This structure defines the entry of SWF table.
  564. **/
  565. typedef struct {
  566. UINT32 Register; ///< Defines the MMIO offset of the SWF register.
  567. UINT32 Value; ///< Defines the default value for the SWF register.
  568. } SWF_TABLE;
  569. /**
  570. This defines the structure of Block 8 (MMIO SW Flag Block).
  571. **/
  572. typedef struct {
  573. UINT8 BlockId; ///< Defines the Block ID : 8.
  574. UINT16 BlockSize; ///< Defines the size of MMIO SWF register table block.
  575. UINT16 RegTableId; ///< Defines the ID for MMIO SWF register table (0xFFFC).
  576. UINT8 AccessFlag; ///< Defines the data access size. Value is 0x02 meaning 4 bytes read/write.
  577. SWF_TABLE SWFTable[7]; ///< Array containing the MMIO SWF register table.
  578. UINT16 TableEnd; ///< Special value describing end of table (0xFFFF).
  579. } BLOCK08_MMIOSWFLAG_REG_TABLE;
  580. /**
  581. This structure defines the PSR feature table entry.
  582. **/
  583. typedef struct {
  584. UINT8 SRD_Enables; ///< Defines PSR features such as full link enable/disable and whether aux is required to wake up.
  585. UINT8 SRD_WaitTimes; ///< Defines lines to wait before link standby and idle frames to wait before SRD enable.
  586. UINT16 SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of 100.
  587. UINT16 SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples of 100
  588. } PSR_FEATURE_TABLE;
  589. /**
  590. This defines the structure of Block 9 (PSR Features Block)
  591. **/
  592. typedef struct {
  593. UINT8 BlockId; ///< Defines the block ID : 9
  594. UINT16 BlockSize; ///< Defines the size of PSR Feature block.
  595. PSR_FEATURE_TABLE PSRFeatureTable[16]; ///< Array containing the PSR Feature table.
  596. } BLOCK09_PSR_FEATURE;
  597. /**
  598. This structure defines an entry of Mode Removal table.
  599. **/
  600. typedef struct {
  601. UINT16 XRes; ///< X resolution of the mode.
  602. UINT16 YRes; ///< Y resolution of the mode.
  603. UINT8 Bpp; ///< Bits per pixel of the mode.
  604. UINT16 RRate; ///< Refresh rate of the mode.
  605. UINT8 RFlags; ///< Flags specifying display type and functional area where the mode is to be removed.
  606. UINT16 PanelFlags; ///< Applicable to LFP only. Indicates which LFP panels the mode is to be removed.
  607. } MODE_REMOVAL_TABLE_ENTRY;
  608. /**
  609. This defines the structure of Block 10 (Mode Removal Block)
  610. **/
  611. typedef struct {
  612. UINT8 BlockId; ///< Defines the Block ID : 10.
  613. UINT16 BlockSize; ///< Defines the size of Mode Removal table block.
  614. UINT8 EntrySize; ///< Defines the size of one entry of mode removal table.
  615. MODE_REMOVAL_TABLE_ENTRY ModeRemovalTable[20]; ///< Array containing the mode removal table.
  616. UINT16 Terminator; ///< Special value indicating end of mode removal table (0xFFFF).
  617. } BLOCK10_MODE_REMOVAL_TABLE;
  618. /**
  619. This defines the structure of Block 12 (Driver Features Data Block)
  620. **/
  621. typedef struct {
  622. UINT8 BlockId; ///< Defines the unique Block ID : 12
  623. UINT16 BlockSize; ///< Defines the size of Driver features block.
  624. /**
  625. This field defines the various driver related bits:\n
  626. Bit 7 = Use 00000110h ID for Primary LFP
  627. = 0, No
  628. = 1, Yes
  629. Bit 6 = Enable/Disable Sprite in Clone Mode
  630. = 0, Disable
  631. = 1, Enable
  632. Bit 5 = Driver INT 15h hook
  633. = 0, Disable
  634. = 1, Enable
  635. Bit 4 = Dual View Zoom
  636. = 0, Disable
  637. = 1, Enable
  638. Bit 3 = Hot Plug DVO
  639. = 0, Disable
  640. = 1, Enable
  641. Bit 2 = Allow display switching when in Full Screen DOS.
  642. = 0, Block Display Switching
  643. = 1, Allow Display Switching
  644. Bit 1 = Block display switching when DVD active
  645. = 0, No Block Display Switching
  646. = 1, Block Display Switching
  647. Bit 0 = Boot device algorithm
  648. = 0, OS Default
  649. = 1, Driver Default
  650. **/
  651. UINT8 bmp_Driver_Bits;
  652. UINT16 bmp_Driver_Boot_Mode_X; ///< X resolution of driver boot mode.
  653. UINT16 bmp_Driver_Boot_Mode_Y; ///< Y resolution of driver boot mode.
  654. UINT8 bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot mode.
  655. UINT8 bmp_Driver_Boot_Mode_RR; ///< Refresh rate of driver boot mode.
  656. /**
  657. This field defines the extended driver bits 1.\n
  658. Bits [15:14] = Integrated HDMI configuration
  659. = 00b, No Integrated HDMI
  660. = 01b, Port-B Only
  661. = 10b, Port-C Only
  662. = 11b, Both Port-B and Port-C
  663. Bits 13 = TV Hotplug
  664. Bits [12:11] = LFP configuration
  665. = 00b, No LVDS
  666. = 01b, Integrated LVDS
  667. = 10b, SDVO LVDS
  668. = 11b, eDP
  669. Bit 10 = Obsolete field: CRT hotplug
  670. = 0, Disabled
  671. = 1, Enabled (Default)
  672. Bit 9 = SDVO device power down
  673. = 0, Disabled (Default)
  674. = 1, Enabled
  675. Bit 8 = Preserve Aspect Ratio
  676. = 0, Disabled (Default)
  677. = 1, Enabled
  678. Bit 7 = Display "Maintain Aspect Scaling" via CUI
  679. = 0, No
  680. = 1, Yes (Default)
  681. Bit 6 = Sprite Display Assignment when Overlay is Active in Clone Mode:
  682. = 0, Secondary
  683. = 1, Primary
  684. Bit 5 = Default Power Scheme user interface
  685. = 0, CUI
  686. = 1, 3rd Party Application
  687. Bit 4 = NT 4.0 Dual Display Clone Support
  688. = 0, Disable
  689. = 1, Enable
  690. Bit 3 = Default Render Clock Frequency
  691. = 0, High Frequency
  692. = 1, Low Frequency
  693. Bit 2 = Dual-Frequency Graphics Technology
  694. = 0, No
  695. = 1, Yes
  696. Bit 1 = Selective Mode Pruning
  697. = 0, No
  698. = 1, Yes
  699. Bit 0 = Enable LFP as primary
  700. = 0, Disable
  701. = 1, Enable
  702. **/
  703. UINT16 bmp_Ext_Driver_Bits;
  704. /**
  705. This defines the driver flags related to CUI Hot key.\n
  706. Bits [7:3] - Reserved
  707. Bit 2 = Display Subsystem Enable/Disable
  708. = 0, Enable (default Value)
  709. = 1, Disable
  710. Bit 1 = Embedded Platform
  711. = 0, False
  712. = 1, True
  713. Bit 0 = Define CUI HotK Displays Statically
  714. = 0, No
  715. = 1, Yes
  716. **/
  717. UINT8 bmp_Display_Detect_CUIHotK;
  718. UINT16 bmp_Legacy_CRT_Max_X; ///< Obsolete field: Defines the legacy CRT X resolution for driver boot mode.
  719. UINT16 bmp_Legacy_CRT_Max_Y; ///< Obsolete field: Defines the legacy CRT Y resolution for driver boot mode.
  720. UINT8 bmp_Legacy_CRT_Max_RR; ///< Obsolete field: Defines the legacy CRT refresh rate for driver boot mode.
  721. /**
  722. This field defines the extended driver bits 2.\n
  723. Bits [7:1] - Reserved
  724. Bit 0 = Enable Internal Source Termination for HDMI
  725. = 0, External Termination
  726. = 1, Internal Termination
  727. **/
  728. UINT8 bmp_Ext2_Driver_Bits;
  729. UINT8 bmp_VBT_Customization_Version; ///< Defines the customized VBT version number.
  730. /**
  731. This field defines all the driver feature flags.\n
  732. Bit 15 = PC Features Field's Validity
  733. = 0, Invalid
  734. = 1, Valid
  735. Bit 14 = Hpd_wake - HPD events are routed to display driver when system is in S0ix/DC9
  736. = 0, Disable
  737. = 1, Enable
  738. Bit 13 = Assertive Display Technology (ADT)
  739. = 0, Disable
  740. = 1, Enable
  741. Bit 12 = Dynamic Media Refresh Rate Switching (DMRRS)
  742. = 0, Disable
  743. = 1, Enable
  744. Bit 11 = Dynamic Frames Per Second (DFPS)
  745. = 0, Disable
  746. = 1, Enable
  747. Bit 10 = Intermediate Pixel Storage (IPS)
  748. = 0, Disable
  749. = 1, Enable
  750. Bit 9 = Panel Self Refresh (PSR)
  751. = 0, Disable
  752. = 1, Enable
  753. Bit 8 = Intel Turbo Boost Technology
  754. = 0, Disable
  755. = 1, Enable
  756. Bit 7 = Graphics Power Modulation Technology (GPMT)
  757. = 0, Disable
  758. = 1, Enable
  759. Bit 6 = Graphics Render Standby (RS)
  760. = 0, Disable
  761. = 1, Enable
  762. Bit 5 = Intel Display Refresh Rate Switching (DRRS)
  763. = 0, Disable
  764. = 1, Enable
  765. Bit 4 = Intel Automatic Display Brightness (ADB)
  766. = 0, Disable
  767. = 1, Enable
  768. Bit 3 = DxgkDDI Backlight Control (DxgkDdiBLC)
  769. = 0, Disable
  770. = 1, Enable
  771. Bit 2 = Intel Display Power Saving Technology (DPST)
  772. = 0, Disable
  773. = 1, Enable
  774. Bit 1 = Intel Smart 2D Display Technology (S2DDT)
  775. = 0, Disable
  776. = 1, Enable
  777. Bit 0 = Intel Rapid Memory Power Management (RMPM)
  778. = 0, Disable
  779. = 1, Enable
  780. **/
  781. UINT16 bmp_Driver_Feature_Flags;
  782. } BLOCK12_DRIVER_FEATURES;
  783. /**
  784. This defines the structure of Block 13 (Driver Persistence Options)
  785. **/
  786. typedef struct {
  787. UINT8 BlockId; ///< Defines the unique Block ID : 13
  788. UINT16 BlockSize; ///< Defines the size of Driver Persistence options block.
  789. /**
  790. Defines the various persistence options.\n
  791. Bits [15:10] - Reserved
  792. Bit 9 = Docking Persistence Algorithm
  793. = 0, OS Default
  794. = 1, Driver Default
  795. Bit 8 = DVO Hot Plug Persistence on Mode
  796. Bit 7 = EDID Persistence on Mode
  797. Bit 6 = Hot Key Persistence on Mode
  798. = 0, No
  799. = 1, Yes
  800. Bit 5 = Hot Key Persistence on RestorePipe
  801. = 0, No
  802. = 1, Yes
  803. Bit 4 = Hot Key Persistence on RefreshRate
  804. = 0, No
  805. = 1, Yes
  806. Bit 3 = Hot Key Persistence on MDS/Twin
  807. = 0, No
  808. = 1, Yes
  809. Bit 2 = Power Management Persistence Algorithm
  810. = 0, OS Default
  811. = 1, Driver Default
  812. Bit 1 = Lid Switch Persistence Algorithm
  813. = 0, OS Default
  814. = 1, Driver Default
  815. Bit 0 = Hot Key Persistence Algorithm
  816. = 0, OS Default
  817. = 1, Driver Default
  818. **/
  819. UINT16 PersistenceAlgorithm;
  820. UINT8 PersistMaxconfig; ///< Maximum mode persistence configurations (10-200)
  821. } BLOCK13_DRIVER_PERSISTENCE;
  822. /**
  823. This defines the structure of Block 17 (SV Bits)
  824. **/
  825. typedef struct {
  826. UINT8 BlockId; ///< Defnies the unique Block ID : 17
  827. UINT16 BlockSize; ///< Defines the size of SV Bits block.
  828. /**
  829. Bits [7:4] = Reserved
  830. Bit3 = Allow VBlank/VblankScanline timeout hang
  831. = 0, Disable
  832. = 1, Enable
  833. Bit2 = Special GMBus support
  834. = 0, Disable
  835. = 1, Enable
  836. Bit1 = Skip program pipe timings when set VGA modes
  837. = 0, Setmode skip DVO Update
  838. = 1, Setmode updates DVO
  839. Bit0 = Disable VGA fast arbiter
  840. = 0, Enabled
  841. = 1, Disabled
  842. **/
  843. UINT8 SvBits1;
  844. UINT8 SvBits2; ///< Reserved for future use.
  845. UINT8 SvBits3; ///< Reserved for future use.
  846. UINT8 SvBits4; ///< Reserved for future use.
  847. UINT8 SvBits5; ///< Reserved for future use.
  848. UINT8 SvBits6; ///< Reserved for future use.
  849. UINT8 SvBits7; ///< Reserved for future use.
  850. UINT8 SvBits8; ///< Reserved for future use.
  851. } BLOCK17_SV_BITS;
  852. /**
  853. This defines the structure of Block 18 (Driver Rotation)
  854. **/
  855. typedef struct {
  856. UINT8 BlockId; ///< Defines the unique Block ID : 18
  857. UINT16 BlockSize; ///< Defines the size of Driver Rotation block.
  858. UINT8 RotationFeatureSupport; ///< Rotation feature support field used by driver.
  859. UINT8 Reserved1; ///< Reserved for future use.
  860. UINT16 Reserved2; ///< Reserved for future use.
  861. UINT32 Reserved3; ///< Reserved for future use.
  862. UINT32 Reserved4; ///< Reserved for future use.
  863. } BLOCK18_DRIVER_ROTATION;
  864. /**
  865. This structure defines an entry of OEM mode table.
  866. **/
  867. typedef struct {
  868. /**
  869. Mode Flags:
  870. Bits[7:3] = Reserved
  871. Bit 2 = Enable/disable this OEM mode in GOP driver.
  872. Bit 1 = Enable/disable this mode in Driver
  873. Bit 0 = Enable/disable this mode in VBIOS
  874. **/
  875. UINT8 ModeFlags;
  876. /**
  877. Display Device Flags:
  878. Bit 7 = LFP2
  879. Bit 6 = EFP2
  880. Bit 5 = EFP3
  881. Bit 4 = EFP4
  882. Bit 3 = LFP
  883. Bit 2 = EFP
  884. Bit 1 = Rsvd
  885. Bit 0 = Rsvd
  886. **/
  887. UINT8 DisplayFlags;
  888. UINT16 XRes; ///< Defines the X resolution of the mode.
  889. UINT16 YRes; ///< Defines the Y resolution of the mode.
  890. /**
  891. Defines the bits per pixel of the mode.
  892. Bit 7:3 = Reserved
  893. Bit 2 = 32 BPP
  894. Bit 1 = 16 BPP
  895. Bit 0 = 8 BPP
  896. **/
  897. UINT8 Bpp;
  898. UINT8 RRate; ///< Defines the refresh rate of the mode.
  899. DTD_STRUCTURE Dtd; ///< Defines the 18 byte timing config for the mode.
  900. } OEM_MODE_ENTRY;
  901. /**
  902. This defines the structure of Block 20 (OEM Mode Customization Block)
  903. **/
  904. typedef struct {
  905. UINT8 BlockId; ///< Defines the unique block ID : 20
  906. UINT16 BlockSize; ///< Defines the size of OEM customization block.
  907. UINT8 NumOfEntry; ///< Defines the number of entries in OEM Mode table.
  908. UINT8 EntrySize; ///< Defines the size of one entry of OEM Mode table.
  909. OEM_MODE_ENTRY OemModeTable[6]; ///< Array defining the OEM mode table.
  910. } BLOCK20_OEM_CUSTOMIZATION;
  911. /**
  912. This defines the structure of Block 26 (TV options)
  913. **/
  914. typedef struct {
  915. UINT8 BlockId; ///< Defines the unique Block ID : 26
  916. UINT16 BlockSize; ///< Defines the size of TV Options block.
  917. /**
  918. Defines the TV options:
  919. Bit 15 = D-Conector Support
  920. = 0, Disable
  921. = 1, Enable
  922. Bit 14 = Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected
  923. = 0, Disable
  924. = 1, Enable
  925. Bit 13:12 Underscan/overscan for HDTV via DVI
  926. = 00b, Enable Underscan and Overscan modes (Default)
  927. = 01b, Enable only overscan modes
  928. = 10b, Enable only underscan modes
  929. Bits 11:2 = Reserved
  930. Bit 1:0 = Underscan/overscan for HDTV via Component (YPrPb)
  931. = 00b, Enable Underscan and Overscan modes (Default)
  932. = 01b, Enable only overscan modes
  933. = 10b, Enable only underscan modes
  934. **/
  935. UINT16 bmp_TV_Options_1;
  936. } BLOCK26_TV_OPTIONS;
  937. /**
  938. This structure defines the eDP panel power sequencing parameters.
  939. **/
  940. typedef struct {
  941. UINT16 T3; ///< Panel Power-Up Delay.
  942. UINT16 T8; ///< Panel Power-On to backlight Enable Delay.
  943. UINT16 T9; ///< Backlight-Off to Power-Down Delay.
  944. UINT16 T10; ///< Power-Down Delay.
  945. UINT16 T12; ///< Power Cycle Delay.
  946. } EDP_PWR_SEQ;
  947. /**
  948. This structure defines the PWM<-->Backlight delays for a single eDP panel.
  949. **/
  950. typedef struct {
  951. UINT16 PwmOnToBacklightEnableDelay; ///< PWM on to backight enable delay.
  952. UINT16 BacklightDisableToPwmOffDelay; ///< Backlight disable to PWM off delay.
  953. } EDP_PWM_BACKLIGHT_DELAYS;
  954. /**
  955. This defines FLT parameters for a single eDP panel.
  956. Bits[15:12] : VSwing level
  957. 0 : 0.4V (default)
  958. 1 : 0.6V
  959. 2 : 0.8V
  960. 3 : 1.2V
  961. Others : Reserved
  962. Bits[11:8] : Pre-emphasis level
  963. 0 : no pre-emphasis (default)
  964. 1 : 3.5dB
  965. 2 : 6dB
  966. 3 : 9.5dB
  967. Others : Reserved
  968. Bits[7:4] : Lane count (port width)
  969. 0 : x1 mode (default)
  970. 1 : x2 mode
  971. 2 : Reserved
  972. 3 : x4 mode
  973. Others : Reserved
  974. Bits[3:0] : data rate
  975. 0 : 1.62 Gbps
  976. 1 : 2.7 Gbps
  977. 2 : 5.4 Gbps
  978. Others : Reserved
  979. **/
  980. typedef union {
  981. UINT16 Value;
  982. struct {
  983. UINT16 DataRate:4;
  984. UINT16 LaneCount:4;
  985. UINT16 PreEmphasisLevel:4;
  986. UINT16 VSwingLevel:4;
  987. } Bits;
  988. } EDP_FAST_LINK_TRAINING_PARAMS;
  989. /**
  990. This defines Full link training parameters for a single eDP panel.
  991. Bits[7:4] : VSwing level
  992. 0 : 0.4V (default)
  993. 1 : 0.6V
  994. 2 : 0.8V
  995. 3 : 1.2V
  996. Others : Reserved
  997. Bits[3:0] : Pre-emphasis level
  998. 0 : no pre-emphasis (default)
  999. 1 : 3.5dB
  1000. 2 : 6dB
  1001. 3 : 9.5dB
  1002. Others : Reserved
  1003. **/
  1004. typedef union {
  1005. UINT8 Value;
  1006. struct {
  1007. UINT8 PreEmphasisLevel:4;
  1008. UINT8 VSwingLevel:4;
  1009. } Bits;
  1010. } EDP_FULL_LINK_TRAINING_PARAMS;
  1011. /**
  1012. This defines the structure of Apical Parameters for a single eDP panel.
  1013. **/
  1014. typedef struct {
  1015. UINT32 PanelOui; ///< Apical IP specific field for Panel OUI
  1016. UINT32 DPCDBaseAddress; ///< Apical IP specific field for DPCD Base address
  1017. UINT32 DPCDIrdidixControl0; ///< Apical IP specific field for DPCD Idridix Control 0
  1018. UINT32 DPCDOptionSelect; ///< Apical IP specific field for DPCD option select
  1019. UINT32 DPCDBacklight; ///< Apical IP specific field for DPCD backlight
  1020. UINT32 AmbientLight; ///< Apical IP specific field for Ambient light
  1021. UINT32 BacklightScale; ///< Apical IP specific field for backlight scale
  1022. } EDP_APICAL_PARAMS;
  1023. /**
  1024. This defines the structure of Block 27 (eDP Display Block)
  1025. **/
  1026. typedef struct {
  1027. UINT8 BlockId; ///< Defines the unique Block ID : 27
  1028. UINT16 BlockSize; ///< Defines the size of eDP display VBT block.
  1029. EDP_PWR_SEQ eDP_PWR_SEQ[16]; ///< Array defining the panel power sequencing for all 16 eDP panels.
  1030. /**
  1031. Defines the panel color depth in bits per pixel. 2 Bits for each Panel.
  1032. Bits[1:0] Panel color depth for Panel #1
  1033. = 00, 18bpp
  1034. = 01, 24bpp
  1035. = 10, 30bpp
  1036. = 11, 36bpp
  1037. **/
  1038. UINT32 eDP_Panel_Color_Depth;
  1039. /**
  1040. Array containing the FLT parameters of 16 eDP panels.
  1041. **/
  1042. EDP_FAST_LINK_TRAINING_PARAMS eDP_Fast_Link_Training_Params[16];
  1043. /**
  1044. This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels. 2 Bits for Each Panel.
  1045. Bits[1:0] for Panel #1
  1046. = 00, Line 1
  1047. = 01, Line 2
  1048. = 10, Line 3
  1049. = 11, Line 4
  1050. **/
  1051. UINT32 eDP_sDRRS_MSA_Delay;
  1052. /**
  1053. Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for Each Panel.
  1054. Bits[0] for Panel #1
  1055. = 0, S3D disabled for this panel
  1056. = 1, S3D enabled for this panel
  1057. **/
  1058. UINT16 eDP_S3D_Feature;
  1059. /**
  1060. Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for each panel.
  1061. Bits[0] = Panel #1
  1062. = 0, T3 optimization disabled for this panel
  1063. = 1, T3 optimization enabled for this panel
  1064. **/
  1065. UINT16 eDP_T3_Optmization;
  1066. /**
  1067. Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Each Panel
  1068. Bits[3:0] = Panel #1
  1069. = 0, Use table 1 for this panel.
  1070. = 1, Use table 2 for this panel.
  1071. **/
  1072. UINT64 VswingPreEmphasisTableNum;
  1073. /**
  1074. Defines the Edp fast link training support on all 16 panels. 1 Bit for Each Panel
  1075. Bits[0] = Panel #1
  1076. = 0, FastLinkTraining feature is disabled for this panel
  1077. = 1, FastLinkTraining feature is enabled for this panel
  1078. **/
  1079. UINT16 EdpFastLinkTrainingSupportOnPanel;
  1080. /**
  1081. Defines whether the Set power state at DPCD 600h is to be done in eDP enable/disable sequence.
  1082. Bits[0] = Panel #1
  1083. = 0, Set power state at DPCD 600h feature is disabled for this panel
  1084. = 1, Set power state at DPCD 600h feature is enabled for this panel
  1085. **/
  1086. UINT16 SetPowerStateAtDPCD600h; //This is not used currently
  1087. /**
  1088. Array defining the PWM <--> Backlight related delays for 16 panels.
  1089. **/
  1090. EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16];
  1091. /**
  1092. Defines the Edp full link training support on all 16 panels. 1 Bit for Each Panel.
  1093. \verbatim
  1094. Bits[0] : Panel #1
  1095. 0 : Initial vswing and pre-emphasis levels are not provided for Full link training
  1096. 1 : Initial vswing and pre-emphasis levels are provided for Full link training
  1097. Bits 1 to 15 are for panel # 2 to 16.
  1098. \endverbatim
  1099. **/
  1100. UINT16 InitialFullLinkTrainingParamsProvidedInVbt;
  1101. /**
  1102. Array containing the initial Vswing and Pre-emphasis parameters for Full link training.
  1103. **/
  1104. EDP_FULL_LINK_TRAINING_PARAMS eDP_Full_Link_Training_Params[16];
  1105. /**
  1106. Defines the Edp Apical assertive display IP support on all 16 panels. 1 Bit for Each Panel.
  1107. Bit 0 : Panel #1
  1108. 0 : Apical assertive display IP is disabled for this panel.
  1109. 1 : Apical assertive display IP is enabled for this panel.
  1110. Bits 1 to 15 are for panel # 2 to 16.
  1111. **/
  1112. UINT16 IsApicalAssertiveDisplayIpEnable;
  1113. /**
  1114. Array containing the Apical parameters for all 16 panels
  1115. **/
  1116. EDP_APICAL_PARAMS eDP_Apcial_Params[16];
  1117. } BLOCK27_EDP_FEATURES;
  1118. /**
  1119. This defines the structure of Block 28 (Edidless EFP support DTD timings)
  1120. **/
  1121. typedef struct {
  1122. UINT8 BlockId; ///< Defines the unique Block ID : 28
  1123. UINT16 BlockSize; ///< Defines the size of Edidless EFP support block.
  1124. DTD_STRUCTURE Edidless_EFP_DTD_Struc[4]; ///< Array defining the DTD timing for 3 EFP devices.
  1125. } BLOCK28_EDIDLESS_EFP;
  1126. /**
  1127. This defines the structure of toggle list entry.
  1128. **/
  1129. typedef struct {
  1130. /**
  1131. Defines the display device selection for toggling
  1132. Bit 15 = EFP4.3 (Reserved for WHL)
  1133. Bit 14 = EFP3.3
  1134. Bit 13 = EFP2.3
  1135. Bit 12 = EFP1.3
  1136. Bit 11 = EFP4.2 (Reserved for WHL)
  1137. Bit 10 = EFP3.2
  1138. Bit 9 = EFP2.2
  1139. Bit 8 = EFP1.2
  1140. Bit 7 = LFP2
  1141. Bit 6 = EFP2
  1142. Bit 5 = EFP3
  1143. Bit 4 = EFP4
  1144. Bit 3 = LFP
  1145. Bit 2 = EFP
  1146. Bit 1 = TV
  1147. Bit 0 = CRT
  1148. **/
  1149. UINT16 DisplayDevice;
  1150. } CNL_TOGGLE_LIST_ENTRY;
  1151. /**
  1152. This defines the structure of Block 31 (Toggle Lists for Cannonlake)
  1153. **/
  1154. typedef struct {
  1155. UINT8 BlockId; ///< Defines the unique Block ID : 31
  1156. UINT16 BlockSize; ///< Defines the size of Toggle List Block.
  1157. UINT16 NumOfEntry1; ///< Defines the number of entries in toggle list 1.
  1158. UINT8 EntrySize1; ///< Defines the size of toggle list entry present in list 1.
  1159. CNL_TOGGLE_LIST_ENTRY ToggleList1Entry[16]; ///< Array defining the toggle list 1.
  1160. UINT16 NumOfEntry2; ///< Defines the number of entries in toggle list 2.
  1161. UINT8 EntrySize2; ///< Defines the size of toggle list entry present in list 2.
  1162. CNL_TOGGLE_LIST_ENTRY ToggleList2Entry[8]; ///< Array defining the toggle list 2.
  1163. UINT16 NumOfEntry3; ///< Defines the number of entries in toggle list 3.
  1164. UINT8 EntrySize3; ///< Defines the size of toggle list entry present in list 3.
  1165. CNL_TOGGLE_LIST_ENTRY ToggleList3Entry[8]; ///< Array defining the toggle list 3.
  1166. UINT16 NumOfEntry4; ///< Defines the number of entries in toggle list 4.
  1167. UINT8 EntrySize4; ///< Defines the size of toggle list entry present in list 4.
  1168. CNL_TOGGLE_LIST_ENTRY ToggleList4Entry[8]; ///< Array defining the toggle list 4.
  1169. } BLOCK31_TOGGLE_LIST;
  1170. /**
  1171. This defines the structure of Display device removal configuration entry.
  1172. **/
  1173. typedef struct {
  1174. /**
  1175. Defines the display device configuration to be removed.
  1176. Bit 15 = EFP4.3 (Reserved for WHL)
  1177. Bit 14 = EFP3.3
  1178. Bit 13 = EFP2.3
  1179. Bit 12 = EFP1.3
  1180. Bit 11 = EFP4.2 (Reserved for WHL)
  1181. Bit 10 = EFP3.2
  1182. Bit 9 = EFP2.2
  1183. Bit 8 = EFP1.2
  1184. Bit 7 = LFP2
  1185. Bit 6 = EFP2
  1186. Bit 5 = EFP3
  1187. Bit 4 = EFP4
  1188. Bit 3 = LFP
  1189. Bit 2 = EFP
  1190. Bit 1 = TV
  1191. Bit 0 = CRT
  1192. **/
  1193. UINT16 DisplayDeviceConfiguration;
  1194. } CNL_DISPLAY_CONFIGURATION_ENTRY;
  1195. /**
  1196. This defines the structure of Block 32 (Display removal configuration Block)
  1197. **/
  1198. typedef struct {
  1199. UINT8 BlockId; ///< Defines the unique Block ID = 32
  1200. UINT16 BlockSize; ///< Defines the size of Display removal configuration block.
  1201. UINT8 NumOfEntry; ///< Defines the number of entries in display removal configuraion table.
  1202. UINT8 EntrySize; ///< Defines the size of 1 entry in display removal configuration table.
  1203. CNL_DISPLAY_CONFIGURATION_ENTRY RemoveDisplayConfiguration[15]; ///< Array defining the display removal configuration table.
  1204. }BLOCK32_DISPLAY_CONFIGURATION_REMOVAL;
  1205. /**
  1206. This defines the Local Flat panel basic details such as resolution and the various registers.
  1207. **/
  1208. typedef struct {
  1209. UINT16 XRes; ///< X resolution of the panel.
  1210. UINT16 YRes; ///< Y resolution of the panel.
  1211. UINT32 LVDSDigDisReg; ///< MMIO offset of LFP digital display port register.
  1212. UINT32 LVDSDigDisVal; ///< Value of LFP digital display port register.
  1213. UINT32 OnSeqDelayReg; ///< MMIO offset of Panel power on sequencing delay register.
  1214. UINT32 OnSeqDelayVal; ///< Value of Panel power on sequencing delay register.
  1215. UINT32 OffSeqDelayReg; ///< MMIO offset of Panel power off sequencing delay register.
  1216. UINT32 OffSeqDelayVal; ///< Value of Panel power off sequencing delay register.
  1217. UINT32 CycleDelay_RefDivReg; ///< MMIO offset of Panel power cycle delay and reference divider register.
  1218. UINT32 CycleDelay_RefDivVal; ///< Value of Panel power cycle delay and reference divider register.
  1219. UINT16 Terminate; ///< Special value 0xFFFF indicating end of data.
  1220. } FP_DATA;
  1221. /**
  1222. This defines the structure consisting of all details for a single Local Flat panel.
  1223. **/
  1224. typedef struct {
  1225. FP_DATA FP_Data; ///< Instance of ::FP_DATA structure.
  1226. DTD_STRUCTURE DTD_Data; ///< Instance of ::DTD_STRUCTURE which contains the DTD timings for the panel.
  1227. PID_DATA PID_Data; ///< Instance of ::PID_DATA structure which contains panel related information used by driver.
  1228. } LVDS_FP_TABLE;
  1229. /**
  1230. This structure defines all the details regarding Backlight control for LFP.
  1231. **/
  1232. typedef struct {
  1233. /**
  1234. Defines the backlight features for the panel.
  1235. Bits 7:6 = GMBus Speed:
  1236. = 00, 100 KHz
  1237. = 01, 50 KHz
  1238. = 10, 400 KHz
  1239. = 11, 1 MHz
  1240. Bits 5:3 = Inverter GPIO Pins
  1241. = 0, None
  1242. = 1, I2C GPIO pins
  1243. = 2, Analog CRT DDC pins
  1244. = 3, DVI/LVDS DDC GPIO pins
  1245. = 5, sDVO I2C GPIO pins
  1246. Bit 2 = Inverter Polarity (i2c & PWM)
  1247. = 0, Normal (0 = Minimum brightness)
  1248. = 1, Inverted (0 = Maximum brightness)
  1249. Bits 1:0 = BLC Inverter Type
  1250. = 00, None/External
  1251. = 01, i2c
  1252. = 10, PWM
  1253. = 11, Reserved
  1254. **/
  1255. UINT8 BLC_Ftr;
  1256. UINT16 PWM_Freq; ///< PWM inverter frequency in KHz
  1257. UINT8 Min_Brightness; ///< Minimum brightness in the range 0-255
  1258. UINT8 I2C_Add; ///< I2C Inverter Slave Address
  1259. UINT8 I2C_Command; ///< I2C Inverter command code
  1260. } BLC;
  1261. /**
  1262. This defines the structure of Block 40 (LFP Features)
  1263. **/
  1264. typedef struct {
  1265. UINT8 BlockId; ///< Defines the unique Block ID : 40
  1266. UINT16 BlockSize; ///< Defines the size of LFP Features block.
  1267. UINT8 bmp_Panel_type; ///< Defines the panel type of LFP.
  1268. UINT8 Skip1; ///< Obsoleted.
  1269. /**
  1270. Capabilities byte:
  1271. Bit 15:7 = SW Workaround bits
  1272. Bit 6 = Panel EDID support
  1273. = 0, Disable
  1274. = 1, Enable
  1275. Bit 5 = Pixel dithering
  1276. = 0, Disable
  1277. = 1, Enable
  1278. Bit 4 = Panel Fitting ratio calc.
  1279. = 0 - Manual
  1280. = 1 - Automatic
  1281. Bit 3 = Panel Fitting Graphics mode
  1282. = 0, Bilinear
  1283. = 1, Enhanced
  1284. Bit 2 = Panel Fitting Text mode
  1285. = 0, Bilinear
  1286. = 1, Enhanced
  1287. Bit 1:0 = Panel Fitting Support
  1288. = 00, No panel fitting
  1289. = 01, Text panel fitting
  1290. = 10, GFX panel fitting
  1291. = 11, Text+GFX panel fitting
  1292. **/
  1293. UINT16 bmp_LVDS_Capabilities;
  1294. /**
  1295. Defines the channel type of LFP. 2 Bits for each Panel.
  1296. Bits [0:1] for Panel #1
  1297. = 00, Automatic (algorithm)
  1298. = 01, Single Channel
  1299. = 10, Dual Channel
  1300. = 11, Reserved
  1301. **/
  1302. UINT32 INT_LVDS_Panel_Channel_Bits;
  1303. UINT16 Enable_SSC_Bit; ///< LVDS Spread Spectrum Clock
  1304. UINT16 SSC_Freq_Bit; ///< LVDS Spread Spectrum Clock Frequency
  1305. UINT16 Disable_SSC_DDT_Bit; ///< Disable SSC in Dual Display Twin
  1306. /**
  1307. Defines the panel color depth. 1 Bits for each Panel.
  1308. Bits[0] for Panel #01
  1309. = 0, 18bpp
  1310. = 1, 24bpp
  1311. **/
  1312. UINT16 INT_Panel_Color_Depth;
  1313. /**
  1314. Defines the Panel type. 2 Bits for each Panel.
  1315. Bits [0:1] for Panel #1
  1316. = 00, Static DRRS
  1317. = 01, D2PO
  1318. = 10, Seamless
  1319. = 11, Reserved
  1320. **/
  1321. UINT32 DPS_Panel_Type_Bits;
  1322. /**
  1323. Defines the type of backlight control for the LFP. 2 bits for each Panel.
  1324. Bits [0:1] for Panel #1
  1325. = 00, Default
  1326. = 01, CCFL backlight
  1327. = 10, LED backlight
  1328. = 11, Reserved
  1329. **/
  1330. UINT32 BLT_Control_Type_Bits;
  1331. /**
  1332. Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit for Each Panel.
  1333. Bits[0] : Panel #1
  1334. 0 : Do not keep LCDVCC on during S0 state.
  1335. 1 : Keep LCDVCC on during S0 state.
  1336. Bits 1 to 15 are for panel # 2 to 16.
  1337. **/
  1338. UINT16 LcdvccOnDuringS0State;
  1339. } BLOCK40_LVDS_FEATURES;
  1340. /**
  1341. This structure defines the second type of BMP table pointers.
  1342. This is used to store pointers to LFP Flat panel data, DTD and PID information.
  1343. **/
  1344. typedef struct {
  1345. UINT16 Offset; ///< Offset of the table.
  1346. UINT8 Size; ///< Size of the table.
  1347. } BMP_TABLE_TYPE2_PTR;
  1348. /**
  1349. This structure defines a set of 3 pointers for LFP display.
  1350. These pointers point to FP data, DTD and PID information respectively.
  1351. **/
  1352. typedef struct {
  1353. BMP_TABLE_TYPE2_PTR FpTablePtr; ///< Pointer to FP Data of the LFP panel.
  1354. BMP_TABLE_TYPE2_PTR DtdTablePtr; ///< Pointer to DTD of the LFP panel.
  1355. BMP_TABLE_TYPE2_PTR PidTablePtr; ///< Pointer to the PID data of the LFP panel.
  1356. } LFP_TABLE_POINTERS;
  1357. /**
  1358. This defines the structure of Block 41 (LFP Table Pointers for FPDATA, DTD and PID)
  1359. **/
  1360. typedef struct {
  1361. UINT8 BlockId; ///< Defines the unique Block ID:41
  1362. UINT16 BlockSize; ///< Defines the size of LFP Table Pointer Block.
  1363. UINT8 NumOfEntries; ///< Defines the number of entries in the Table.
  1364. LFP_TABLE_POINTERS LfpTablePointers[16]; ///< Array of ::LFP_TABLE_POINTERS for all 16 panels.
  1365. UINT16 LfpPanelNameTableOffset; ///< Offset of LFP panel names table.
  1366. UINT8 LfpPanelNameLength; ///< Length of a single LFP panel's name.
  1367. } BLOCK41_LFP_TABLE_POINTERS;
  1368. /**
  1369. This defines the structure of Block 42 (Complete LFP Panel Information)
  1370. **/
  1371. typedef struct {
  1372. UINT8 BlockId; ///< Defines the unique block ID : 42
  1373. UINT16 BlockSize; ///< Defines the size of Complete LFP panel information for all 16 panels.
  1374. LVDS_FP_TABLE LVDS_FP_Table[16]; ///< Array of ::LVDS_FP_TABLE containing data of 16 panels.
  1375. UINT8 LFP_PANEL_NAMES[16][13];///< Array defining the panel names for all 16 panels.
  1376. /**
  1377. 1 Bit for Each Panel
  1378. Bit0 = Scaling feature for panel 1.
  1379. = 0, Scaling feature is disabled for this panel.
  1380. = 1, Scaling feature is enabled for this panel.
  1381. **/
  1382. UINT16 EnableScaling; //This is not used currently
  1383. /**
  1384. Array defining DRRS minimum refresh rate. 1 Byte for Each Panel.
  1385. **/
  1386. UINT8 Seamless_DRRS_Min_RR[16];
  1387. /**
  1388. Array defining Pixel Overlap Count. 1 Byte for Each Panel.
  1389. **/
  1390. UINT8 PixelOverlapCount[16];
  1391. } BLOCK42_LVDS_PANEL_INFO;
  1392. typedef union {
  1393. /**
  1394. Backlight control parameters.\n
  1395. Bits 7:4 : PWM Controller Selection
  1396. 0 : Controller 0
  1397. 1 : Controller 1
  1398. 2 : Controller 2
  1399. 3 : Controller 3
  1400. Others : Reserved.
  1401. Bits 3:0 : PWM Source Selection
  1402. 0 : PMIC PWM
  1403. 1 : LPSS PWM
  1404. 2 : DISPLAY PWM
  1405. 3 : CABC PWM
  1406. Others : Reserved.
  1407. **/
  1408. UINT8 Value;
  1409. struct {
  1410. UINT8 PwmSourceSelection:4;
  1411. UINT8 PwmControllerSelection:4;
  1412. } Bits;
  1413. } BKLT_CTRL_PARAMS;
  1414. /**
  1415. This defines the structure of Block 43 (LFP Brightness Control)
  1416. **/
  1417. typedef struct {
  1418. UINT8 BlockId; ///< Defines the unique Block ID : 43
  1419. UINT16 BlockSize; ///< Defines the size of Brightness control block.
  1420. UINT8 SIZE_BLCStruc; ///< Defines the size of single entry in Backlight control table for LFP.
  1421. BLC BLC_Struct[16]; ///< Array defining the backlight control for 16 LFP panels.
  1422. UINT8 Post_Brightness[16]; ///< Array defining the initial brightness for all 16 panels.
  1423. BKLT_CTRL_PARAMS Brightness_Control[16]; ///< Array defining the brightness control method for all 16 panels
  1424. } BLOCK43_LVDS_BLC;
  1425. /**
  1426. This defines the structure of Block 44 (LFP Power Conservation Features)
  1427. **/
  1428. typedef struct {
  1429. UINT8 BlockId; ///< Defines the unique block ID : 44
  1430. UINT16 BlockSize; ///< Defines the size of LFP Power Conservation Features block.
  1431. union {
  1432. /**
  1433. Bit[7] : ALS Enable/Disable
  1434. 0 - Disable
  1435. 1 - Enable
  1436. Bit[6] : Display LACE support
  1437. 0 - Not supported
  1438. 1 - Supported
  1439. Bit[5] : Default Display LACE enabled status
  1440. 0 - Disabled
  1441. 1 - Enabled
  1442. Bit[4] : Reserved
  1443. Bit[3:1] : Power conservation preference level.
  1444. 4 is default in a range of 1 to 6.
  1445. Bit[0] : Reserved
  1446. **/
  1447. UINT8 Value;
  1448. struct {
  1449. UINT8 Reserved:1;
  1450. UINT8 PwrConservation:3;
  1451. UINT8 Reserved_1:1;
  1452. UINT8 DefalutDisplayLaceEnable:1;
  1453. UINT8 DisplayLaceSupport:1;
  1454. UINT8 AlsEnable:1;
  1455. } Bits;
  1456. } LfpFeatureBits;
  1457. UINT16 AlsData[10]; ///< Defines the main ALS data.
  1458. union {
  1459. /**
  1460. Bit[7:3] : Reserved
  1461. Bit[2:0] : Aggressiveness Level Profile.
  1462. 000 - Minimum
  1463. 001 - Moderate
  1464. 010 - High
  1465. **/
  1466. UINT8 Value;
  1467. struct {
  1468. UINT8 AggressionProfileLevel:3;
  1469. UINT8 Reserved:5;
  1470. } Bits;
  1471. } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile
  1472. } BLOCK44_ALS;
  1473. /**
  1474. This defines the structure of Black Frame Insertion table entry.
  1475. **/
  1476. typedef struct {
  1477. /**
  1478. BFI Features\n
  1479. Bit[7-2] : Reserved\n
  1480. Bit[1] : Enable Brightness control in CUI\n
  1481. Bit[0] : Enable BFI in driver
  1482. **/
  1483. UINT8 EnableBits;
  1484. UINT8 BrightnessNonBFI; ///< Brightness percentage in non BFI mode
  1485. } BFI;
  1486. /**
  1487. This defines the structure of Block 45 (Black Frame insertion Support for LFP)
  1488. **/
  1489. typedef struct {
  1490. UINT8 BlockId; ///< Defines the unique Block ID : 45
  1491. UINT16 BlockSize; ///< Defines the size of Black frame insertion support block.
  1492. UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of black frame data.
  1493. BFI BFI_Struct[16]; ///< Array defining the data of black frame insertion for all 16 panels.
  1494. } BLOCK45_BFI_SUPPORT;
  1495. /**
  1496. This structure defines the chromaticity information for a single LFP panel.
  1497. **/
  1498. typedef struct {
  1499. /**
  1500. Defines the chromaticity feature enable bits
  1501. Bits 7:2 = Reserved
  1502. Bit 1 = Override EDID values for chromaticity if enabled, Instead Use VBT values
  1503. = 0, Disable, Use the EDID values
  1504. = 1, Enable, Use the values from the VBT
  1505. Bit 0 = Enable chromaticity feature. EDID values will be used when this feature is enabled.
  1506. = 0, Disable
  1507. = 1, Enable
  1508. **/
  1509. UINT8 EnableBits;
  1510. UINT8 Red_Green_1; ///< Red/green chormaticity coordinates at EDID offset 19h
  1511. UINT8 Blue_White_1; ///< Blue/white chromatiity coordinates at EDID offset 1Ah
  1512. UINT8 Red_X1; ///< Red x coordinate at EDID offset 1Bh
  1513. UINT8 Red_Y1; ///< Red x coordinate at EDID offset 1Ch
  1514. UINT8 Green_X1; ///< Green x coordinate at EDID offset 1Dh
  1515. UINT8 Green_Y1; ///< Green x coordinate at EDID offset 1Eh
  1516. UINT8 Blue_X1; ///< Blue x coordinate at EDID offset 1Fh
  1517. UINT8 Blue_Y1; ///< Blue x coordinate at EDID offset 20h
  1518. UINT8 White_X1; ///< White x coordinate at EDID offset 21h
  1519. UINT8 White_Y1; ///< White x coordinate at EDID offset 22h
  1520. } CHROMATICITY;
  1521. /**
  1522. This structure defines the Luminance information for a single LFP panel.
  1523. **/
  1524. typedef struct {
  1525. /**
  1526. Defines the chromaticity feature enable bits
  1527. Bits 7:2 : Reserved
  1528. Bit 1 : Enable Gamma feature.
  1529. : if enabled, use gamma values from this block.
  1530. 0 : Disable
  1531. 1 : Enable
  1532. Bit 0 : Enable Luminance feature.
  1533. : if enabled, use values from this block.
  1534. 0 : Disable
  1535. 1 : Enable
  1536. **/
  1537. UINT8 EnableBits;
  1538. /**
  1539. Luminance info (refer DisplayID 2.0)
  1540. 2 byte value, encoded in IEEE 754 half-precision binary floating point format
  1541. **/
  1542. UINT16 MinLuminance; ///< Native minimum luminance
  1543. UINT16 MaxFullFrameLuminance; ///< Native maximum luminance (Full Frame)
  1544. UINT16 MaxLuminance; ///< Native Maximum Luminance (1% Rectangular Coverage)
  1545. /**
  1546. Gamma EOTF
  1547. Gamma values range from 00h through FFh which will come from VBT.
  1548. Value shall define the gamma range, from 1.00 to 3.54.
  1549. Field Value = (Gamma (value from VBT) + 100) / 100
  1550. FFh = No gamma information shall be provided
  1551. **/
  1552. UINT8 Gamma;
  1553. }LUMINANCE_AND_GAMMA;
  1554. /**
  1555. This defines the structure of Block 46 (Chromaticity Support)
  1556. **/
  1557. typedef struct {
  1558. UINT8 BlockId; ///< Defines the unique Block ID : 46
  1559. UINT16 BlockSize; ///< Defines the size of Chromaticity Block.
  1560. CHROMATICITY Chromaticity_Struct[16]; ///< Defines the chromaticity information for all 16 panels.
  1561. LUMINANCE_AND_GAMMA Luminance_Gamma_Struct[16]; ///< Defines the lumianance information for all 16 panels.
  1562. } BLOCK46_CHROMATICITY_SUPPORT;
  1563. /**
  1564. This defines the structure of Block 51 (Fixed Mode Set)
  1565. **/
  1566. typedef struct{
  1567. UINT8 BlockId; ///< Defines the unique block ID : 51.
  1568. UINT16 BlockSize; ///< Defines the size of Fixed mode set feature block.
  1569. UINT8 FeatureEnable; ///< Whether the fixed mode set feature is enabled/disabled.
  1570. UINT32 XRes; ///< X resolution of the fixed mode.
  1571. UINT32 YRes; ///< Y resolution of the fixed mode.
  1572. } BLOCK51_FIXED_MODE_SET;
  1573. /**
  1574. This defines the Complete VBT Structure for generation purpose
  1575. **/
  1576. typedef struct {
  1577. VBT_HEADER VbtHeader;
  1578. VBT_BIOS_DATA_HEADER VbtBdbHeader;
  1579. BLOCK254_BMP_Structure Block254BMPStructure;
  1580. VBT_GENERAL1_INFO VbtGen1Info;
  1581. PRD_BOOT_TABLE PrdBootTable;
  1582. VBT_GENERAL2_INFO VbtGen2Info;
  1583. BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST Block03OriginalDisplayToggleList;
  1584. BLOCK252_SBIOS_Hook Block252SbiosHook;
  1585. BLOCK06_MMIO_REG_TABLE Block06MmioRegTable;
  1586. BLOCK07_IOSWFLAG_REG_TABLE Block07IoswflagRegTable;
  1587. BLOCK08_MMIOSWFLAG_REG_TABLE Block08MmioswflagRegTable;
  1588. BLOCK09_PSR_FEATURE Block09PsrFeature;
  1589. BLOCK10_MODE_REMOVAL_TABLE Block10ModeRemovalTable;
  1590. BLOCK12_DRIVER_FEATURES Block12DriverFeatures;
  1591. BLOCK13_DRIVER_PERSISTENCE Block13DriverPersistence;
  1592. BLOCK17_SV_BITS Block17SvBits;
  1593. BLOCK18_DRIVER_ROTATION Block18DriverRotation;
  1594. BLOCK20_OEM_CUSTOMIZATION Block20OemCustomization;
  1595. BLOCK26_TV_OPTIONS Block26TVOptions;
  1596. BLOCK27_EDP_FEATURES Block27EDPFeatures;
  1597. BLOCK28_EDIDLESS_EFP Block28EdidlessEFP;
  1598. BLOCK31_TOGGLE_LIST Block31ToggleList;
  1599. BLOCK32_DISPLAY_CONFIGURATION_REMOVAL Block32DisplayConfigurationRemoval;
  1600. BLOCK40_LVDS_FEATURES Block40LVDSFeatures;
  1601. BLOCK41_LFP_TABLE_POINTERS Block41LfpTablePointers;
  1602. BLOCK42_LVDS_PANEL_INFO Block42LvdsPanelInfo;
  1603. BLOCK43_LVDS_BLC Block43LVDSBlc;
  1604. BLOCK44_ALS Block44Als;
  1605. BLOCK46_CHROMATICITY_SUPPORT Block46ChromaticitySupport;
  1606. BLOCK51_FIXED_MODE_SET Block51FixedModeSet;
  1607. } VBT_TABLE_DATA;
  1608. #pragma pack()
  1609. /**
  1610. This function will update the VBT checksum.
  1611. @param[in out] VbtPtr - Pointer to VBT table
  1612. @retval none
  1613. **/
  1614. VOID
  1615. UpdateVbtChecksum(
  1616. VBT_TABLE_DATA *VbtPtr
  1617. );
  1618. /**
  1619. This function will update the VBT.
  1620. @param[in] VbtPtr - Pointer to VBT Table
  1621. @retval none
  1622. **/
  1623. VOID
  1624. UpdateGopVbt (
  1625. IN VBT_TABLE_DATA *VbtPtr
  1626. );
  1627. #endif