VlvPlatformInit.c 7.4 KB

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  1. /*++
  2. Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. VlvPlatformInit.c
  6. Abstract:
  7. This is the driver that initializes the Intel ValleyView.
  8. --*/
  9. #include "VlvPlatformInit.h"
  10. #include <Protocol/VlvPlatformPolicy.h>
  11. extern DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
  12. UINT64 GTTMMADR;
  13. DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
  14. /**
  15. "Poll Status" for GT Readiness
  16. @param Base Base address of MMIO
  17. @param Offset MMIO Offset
  18. @param Mask Mask
  19. @param Result Value to wait for
  20. @retval None
  21. **/
  22. VOID
  23. PollGtReady_hang (
  24. UINT64 Base,
  25. UINT32 Offset,
  26. UINT32 Mask,
  27. UINT32 Result
  28. )
  29. {
  30. UINT32 GtStatus;
  31. //
  32. // Register read
  33. //
  34. GtStatus = MmioRead32 ((UINTN)Base+ Offset);
  35. while (((GtStatus & Mask) != Result)) {
  36. GtStatus = MmioRead32 ((UINTN)Base + Offset);
  37. }
  38. }
  39. /**
  40. Do Post GT PM Init Steps after VBIOS Initialization.
  41. @param Event A pointer to the Event that triggered the callback.
  42. @param Context A pointer to private data registered with the callback function.
  43. @retval EFI_SUCCESS GC_TODO
  44. **/
  45. EFI_STATUS
  46. EFIAPI
  47. PostPmInitCallBack (
  48. IN EFI_EVENT Event,
  49. IN VOID *Context
  50. )
  51. {
  52. UINT64 OriginalGTTMMADR;
  53. UINT32 LoGTBaseAddress;
  54. UINT32 HiGTBaseAddress;
  55. //
  56. // Enable Bus Master, I/O and Memory access on 0:2:0
  57. //
  58. PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
  59. //
  60. // only 32bit read/write is legal for device 0:2:0
  61. //
  62. OriginalGTTMMADR = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));
  63. OriginalGTTMMADR = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
  64. //
  65. // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
  66. // Program temporarily 32bits GTTMMADR for POST and S3 resume
  67. //
  68. LoGTBaseAddress = (UINT32) (GTTMMADR & 0xFFFFFFFF);
  69. HiGTBaseAddress = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);
  70. S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
  71. S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
  72. //
  73. // Restore original GTTMMADR
  74. //
  75. LoGTBaseAddress = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
  76. HiGTBaseAddress = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);
  77. S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
  78. S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
  79. //
  80. // Lock the following registers, GGC, BDSM, BGSM
  81. //
  82. PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
  83. PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
  84. PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
  85. gBS->CloseEvent (Event);
  86. //
  87. // Return final status
  88. //
  89. return EFI_SUCCESS;
  90. }
  91. /**
  92. Routine Description:
  93. Initialize GT Post Routines.
  94. @param ImageHandle Handle for the image of this driver
  95. @param DxePlatformSaPolicy SA DxePlatformPolicy protocol
  96. @retval EFI_SUCCESS GT POST initialization complete
  97. **/
  98. EFI_STATUS
  99. IgdPmHook (
  100. IN EFI_HANDLE ImageHandle,
  101. IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicyParam
  102. )
  103. {
  104. EFI_EVENT mConOutEvent;
  105. VOID *gConOutNotifyReg;
  106. EFI_STATUS Status;
  107. EFI_PHYSICAL_ADDRESS MemBaseAddress;
  108. UINT32 LoGTBaseAddress;
  109. UINT32 HiGTBaseAddress;
  110. GTTMMADR = 0;
  111. Status = EFI_SUCCESS;
  112. //
  113. // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
  114. //
  115. if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID)) != 0xFFFF) {
  116. ASSERT (gDS!=NULL);
  117. //
  118. // Enable Bus Master, I/O and Memory access on 0:2:0
  119. //
  120. PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));
  121. //
  122. // Means Allocate 4MB for GTTMADDR
  123. //
  124. MemBaseAddress = 0x0ffffffff;
  125. Status = gDS->AllocateMemorySpace (
  126. EfiGcdAllocateMaxAddressSearchBottomUp,
  127. EfiGcdMemoryTypeMemoryMappedIo,
  128. GTT_MEM_ALIGN,
  129. GTTMMADR_SIZE_4MB,
  130. &MemBaseAddress,
  131. ImageHandle,
  132. NULL
  133. );
  134. ASSERT_EFI_ERROR (Status);
  135. //
  136. // Program GT PM Settings if GTTMMADR allocation is Successful
  137. //
  138. GTTMMADR = (UINTN) MemBaseAddress;
  139. LoGTBaseAddress = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
  140. HiGTBaseAddress = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);
  141. PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);
  142. PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);
  143. S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));
  144. S3MmioRead32(IGD_R_GTTMMADR + 4);
  145. S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));
  146. //
  147. // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack
  148. //
  149. Status = gBS->CreateEvent (
  150. EVT_NOTIFY_SIGNAL,
  151. TPL_CALLBACK,
  152. (EFI_EVENT_NOTIFY)PostPmInitCallBack,
  153. NULL,
  154. &mConOutEvent
  155. );
  156. ASSERT_EFI_ERROR (Status);
  157. if (EFI_ERROR (Status)) {
  158. return Status;
  159. }
  160. Status = gBS->RegisterProtocolNotify (
  161. &gEfiGraphicsOutputProtocolGuid,
  162. mConOutEvent,
  163. &gConOutNotifyReg
  164. );
  165. MmioWrite64 (IGD_R_GTTMMADR, 0);
  166. //
  167. // Free allocated resources
  168. //
  169. gDS->FreeMemorySpace (
  170. MemBaseAddress,
  171. GTTMMADR_SIZE_4MB
  172. );
  173. }
  174. return EFI_SUCCESS;
  175. }
  176. /**
  177. This is the standard EFI driver point that detects
  178. whether there is an ICH southbridge in the system
  179. and if so, initializes the chip.
  180. @param ImageHandle Handle for the image of this driver
  181. @param SystemTable Pointer to the EFI System Table
  182. @retval EFI_SUCCESS The function completed successfully
  183. **/
  184. EFI_STATUS
  185. EFIAPI
  186. VlvPlatformInitEntryPoint (
  187. IN EFI_HANDLE ImageHandle,
  188. IN EFI_SYSTEM_TABLE *SystemTable
  189. )
  190. {
  191. EFI_STATUS Status;
  192. Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);
  193. ASSERT_EFI_ERROR (Status);
  194. //
  195. // GtPostInit Initialization
  196. //
  197. DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));
  198. IgdPmHook (ImageHandle, DxePlatformSaPolicy);
  199. //
  200. // IgdOpRegion Install Initialization
  201. //
  202. DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));
  203. IgdOpRegionInit ();
  204. return EFI_SUCCESS;
  205. }