S3Save.c 7.2 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. IchS3Save.c
  6. Abstract:
  7. SMM S3 handler Driver implementation file
  8. Revision History
  9. **/
  10. #include "SmmPlatform.h"
  11. extern UINT16 mAcpiBaseAddr;
  12. EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;
  13. EFI_STATUS
  14. SaveRuntimeScriptTable (
  15. VOID
  16. )
  17. {
  18. SMM_PCI_IO_ADDRESS PciAddress;
  19. UINT32 Data32;
  20. UINT16 Data16;
  21. UINT8 Data8;
  22. UINT8 Mask;
  23. UINTN Index;
  24. UINTN Offset;
  25. UINT8 RegTable[] = {
  26. //
  27. //Bus , Dev, Func, DMI
  28. //
  29. 0x00 , 0x00, 0x00,
  30. //
  31. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  32. //
  33. 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,
  34. //
  35. //Bus , Dev, Func, LPC device
  36. //
  37. 0x00 , 0x1F, 0x00,
  38. //
  39. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  40. //
  41. 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,
  42. //
  43. //Bus , Dev, Func, PCIE device
  44. //
  45. 0x00 , 0x1C, 0x00,
  46. //
  47. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  48. //
  49. 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
  50. //
  51. //Bus , Dev, Func, PCIE device
  52. //
  53. 0x00 , 0x1C, 0x00,
  54. //
  55. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  56. //
  57. 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  58. //
  59. //Bus , Dev, Func, SATA device
  60. //
  61. 0x00 , 0x13, 0x00,
  62. //
  63. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  64. //
  65. 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,
  66. //
  67. //Bus , Dev, Func, EHCI device
  68. //
  69. 0x00 , 0x1D, 0x00,
  70. //
  71. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  72. //
  73. 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  74. //
  75. //Bus , Dev, Func, SMBUS device
  76. //
  77. 0x00 , 0x1f, 0x03,
  78. //
  79. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  80. //
  81. 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  82. //
  83. //Bus , Dev, Func, SMBUS device
  84. //
  85. 0x00 , 0x1f, 0x03,
  86. //
  87. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  88. //
  89. 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  90. //
  91. //Bus , Dev, Func, VGA bus1
  92. //
  93. 0x01 , 0x00, 0x00,
  94. //
  95. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  96. //
  97. 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,
  98. //
  99. //Bus , Dev, Func, VGA bus1
  100. //
  101. 0x01 , 0x00, 0x00,
  102. //
  103. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  104. //
  105. 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  106. //
  107. //Bus , Dev, Func, VGA bus1 function 1
  108. //
  109. 0x01 , 0x00, 0x01,
  110. //
  111. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  112. //
  113. 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
  114. //
  115. //Bus , Dev, Func, VGA bus1 function 1
  116. //
  117. 0x01 , 0x00, 0x01,
  118. //
  119. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  120. //
  121. 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  122. //
  123. //Bus , Dev, Func, IGD bus0 function 0
  124. //
  125. 0x00 , 0x02, 0x00,
  126. //
  127. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  128. //
  129. 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
  130. //
  131. //Bus , Dev, Func, USB bus0 function 0
  132. //
  133. 0x00 , 0x16, 0x00,
  134. //
  135. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  136. //
  137. 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  138. //
  139. //Bus , Dev, Func, HD Audio bus0 function 0
  140. //
  141. 0x00 , 0x1B, 0x00,
  142. //
  143. //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  144. //
  145. 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
  146. //
  147. //0xFF indicates the end of the table
  148. //
  149. 0xFF
  150. };
  151. //
  152. // These registers have to set in byte order
  153. //
  154. UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings
  155. //
  156. // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
  157. // and vital to S3 resume. That's why we put save code here
  158. //
  159. PciAddress.Bus = 0;
  160. PciAddress.Device = 0;
  161. PciAddress.Function = 0;
  162. PciAddress.ExtendedRegister = 0;
  163. for (Index = 0; Index < 2; Index++) {
  164. //
  165. // Read SRAM setting from Pci(0, 0, 0)
  166. //
  167. PciAddress.Register = ExtReg[Index];
  168. Data8 = MmioRead8 (
  169. MmPciAddress (0,
  170. PciAddress.Bus,
  171. PciAddress.Device,
  172. PciAddress.Function,
  173. PciAddress.Register
  174. )
  175. );
  176. //
  177. // Save latest settings to runtime script table
  178. //
  179. S3BootScriptSavePciCfgWrite(
  180. S3BootScriptWidthUint8,
  181. *(UINT64*)&PciAddress,
  182. 1,
  183. &Data8
  184. );
  185. }
  186. //
  187. // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
  188. // and vital to S3 resume. That's why we put save code here
  189. //
  190. Index = 0;
  191. while (RegTable[Index] != 0xFF) {
  192. PciAddress.Bus = RegTable[Index++];
  193. PciAddress.Device = RegTable[Index++];
  194. PciAddress.Function = RegTable[Index++];
  195. PciAddress.Register = 0;
  196. PciAddress.ExtendedRegister = 0;
  197. Data16 = MmioRead16 (
  198. MmPciAddress (0,
  199. PciAddress.Bus,
  200. PciAddress.Device,
  201. PciAddress.Function,
  202. PciAddress.Register
  203. )
  204. );
  205. if (Data16 == 0xFFFF) {
  206. Index+=8;
  207. continue;
  208. }
  209. for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {
  210. if (Mask == 0x00) {
  211. Mask = 0x01;
  212. }
  213. if (RegTable[Index + Offset/32] & Mask ) {
  214. PciAddress.Register = (UINT8)Offset;
  215. Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));
  216. //
  217. // Save latest settings to runtime script table
  218. //
  219. S3BootScriptSavePciCfgWrite (
  220. S3BootScriptWidthUint32,
  221. *(UINT64*)&PciAddress,
  222. 1,
  223. &Data32
  224. );
  225. }
  226. }
  227. Index += 8;
  228. }
  229. //
  230. // Save I/O ports to S3 script table
  231. //
  232. //
  233. // Selftest KBC
  234. //
  235. Data8 = 0xAA;
  236. S3BootScriptSaveIoWrite (
  237. S3BootScriptWidthUint8,
  238. 0x64,
  239. (UINTN)1,
  240. &Data8
  241. );
  242. Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
  243. S3BootScriptSaveIoWrite (
  244. S3BootScriptWidthUint32,
  245. (mAcpiBaseAddr + R_PCH_SMI_EN),
  246. 1,
  247. &Data32
  248. );
  249. //
  250. // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
  251. //
  252. Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);
  253. S3BootScriptSaveIoWrite (
  254. S3BootScriptWidthUint16,
  255. mAcpiBaseAddr + R_PCH_TCO_CNT,
  256. 1,
  257. &Data16
  258. );
  259. return EFI_SUCCESS;
  260. }