Platform.c 34 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. Platform.c
  6. Abstract:
  7. Platform Initialization Driver.
  8. --*/
  9. #include "PlatformDxe.h"
  10. #include "Platform.h"
  11. #include "PchCommonDefinitions.h"
  12. #include <Protocol/PchPlatformPolicy.h>
  13. #include <Protocol/CpuIo2.h>
  14. #include <Library/S3BootScriptLib.h>
  15. #include <Guid/PciLanInfo.h>
  16. #include <Guid/ItkData.h>
  17. #include <Library/PciLib.h>
  18. #include <PlatformBootMode.h>
  19. #include <Guid/EventGroup.h>
  20. #include <Guid/Vlv2Variable.h>
  21. #include <Protocol/GlobalNvsArea.h>
  22. #include <Protocol/IgdOpRegion.h>
  23. #include <Library/PcdLib.h>
  24. #include <Protocol/VariableLock.h>
  25. //
  26. // VLV2 GPIO GROUP OFFSET
  27. //
  28. #define GPIO_SCORE_OFFSET 0x0000
  29. #define GPIO_NCORE_OFFSET 0x1000
  30. #define GPIO_SSUS_OFFSET 0x2000
  31. typedef struct {
  32. UINT32 offset;
  33. UINT32 val;
  34. } CFIO_PNP_INIT;
  35. GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
  36. {
  37. // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
  38. GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
  39. GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
  40. };
  41. EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
  42. SYSTEM_CONFIGURATION mSystemConfiguration;
  43. EFI_HANDLE mImageHandle;
  44. BOOLEAN mMfgMode = FALSE;
  45. UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
  46. extern CHAR16 gItkDataVarName[];
  47. EFI_PLATFORM_INFO_HOB mPlatformInfo;
  48. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
  49. EFI_EVENT mReadyToBootEvent;
  50. UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  51. UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
  52. UINTN mPciLanCount = 0;
  53. VOID *mPciLanInfo = NULL;
  54. UINTN SpiBase;
  55. static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
  56. ProgramToneFrequency,
  57. GenerateBeepTone
  58. };
  59. CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
  60. {
  61. {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
  62. {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
  63. {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
  64. {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
  65. {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
  66. {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
  67. {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
  68. {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
  69. {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
  70. {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
  71. {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
  72. {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
  73. {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
  74. {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
  75. {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
  76. {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
  77. {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
  78. {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
  79. };
  80. VOID
  81. EfiOrMem (
  82. IN VOID *Destination,
  83. IN VOID *Source,
  84. IN UINTN Length
  85. );
  86. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  87. STATIC
  88. VOID
  89. InitFirmwareId();
  90. #endif
  91. VOID
  92. InitializeClockRouting(
  93. );
  94. VOID
  95. InitializeSlotInfo (
  96. );
  97. #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
  98. VOID
  99. InitializeSensorInfoVariable (
  100. );
  101. #endif
  102. VOID
  103. InitTcoReset (
  104. );
  105. VOID
  106. InitExI ();
  107. VOID
  108. InitItk();
  109. VOID
  110. InitPlatformBootMode();
  111. VOID
  112. InitMfgAndConfigModeStateVar();
  113. VOID
  114. InitPchPlatformPolicy (
  115. IN EFI_PLATFORM_INFO_HOB *PlatformInfo
  116. );
  117. VOID
  118. InitVlvPlatformPolicy (
  119. );
  120. VOID
  121. PchInitBeforeBoot(
  122. );
  123. VOID
  124. UpdateDVMTSetup(
  125. );
  126. VOID
  127. InitRC6Policy(
  128. VOID
  129. );
  130. EFI_STATUS
  131. EFIAPI
  132. SaveSetupRecoveryVar(
  133. VOID
  134. )
  135. {
  136. EFI_STATUS Status = EFI_SUCCESS;
  137. UINTN SizeOfNvStore = 0;
  138. UINTN SizeOfSetupVar = 0;
  139. SYSTEM_CONFIGURATION *SetupData = NULL;
  140. SYSTEM_CONFIGURATION *RecoveryNvData = NULL;
  141. EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;
  142. DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));
  143. SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
  144. RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
  145. if (NULL == RecoveryNvData) {
  146. Status = EFI_OUT_OF_RESOURCES;
  147. goto Exit;
  148. }
  149. Status = gRT->GetVariable(
  150. L"SetupRecovery",
  151. &gEfiNormalSetupGuid,
  152. NULL,
  153. &SizeOfNvStore,
  154. RecoveryNvData
  155. );
  156. if (EFI_ERROR (Status)) {
  157. // Don't find the "SetupRecovery" variable.
  158. // have to copy "Setup" variable to "SetupRecovery" variable.
  159. SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
  160. if (NULL == SetupData) {
  161. Status = EFI_OUT_OF_RESOURCES;
  162. goto Exit;
  163. }
  164. SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);
  165. Status = gRT->GetVariable(
  166. NORMAL_SETUP_NAME,
  167. &gEfiNormalSetupGuid,
  168. NULL,
  169. &SizeOfSetupVar,
  170. SetupData
  171. );
  172. ASSERT_EFI_ERROR (Status);
  173. Status = gRT->SetVariable (
  174. L"SetupRecovery",
  175. &gEfiNormalSetupGuid,
  176. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  177. sizeof(SYSTEM_CONFIGURATION),
  178. SetupData
  179. );
  180. ASSERT_EFI_ERROR (Status);
  181. Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
  182. if (!EFI_ERROR (Status)) {
  183. Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery", &gEfiNormalSetupGuid);
  184. ASSERT_EFI_ERROR (Status);
  185. }
  186. }
  187. Exit:
  188. if (RecoveryNvData)
  189. FreePool (RecoveryNvData);
  190. if (SetupData)
  191. FreePool (SetupData);
  192. return Status;
  193. }
  194. VOID
  195. TristateLpcGpioConfig (
  196. IN UINT32 Gpio_Mmio_Offset,
  197. IN UINT32 Gpio_Pin_Num,
  198. GPIO_CONF_PAD_INIT* Gpio_Conf_Data
  199. )
  200. {
  201. UINT32 index;
  202. UINT32 mmio_conf0;
  203. UINT32 mmio_padval;
  204. PAD_CONF0 conf0_val;
  205. PAD_VAL pad_val;
  206. //
  207. // GPIO WELL -- Memory base registers
  208. //
  209. //
  210. // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
  211. // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
  212. //
  213. for(index=0; index < Gpio_Pin_Num; index++)
  214. {
  215. //
  216. // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
  217. //
  218. mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
  219. mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
  220. #ifdef EFI_DEBUG
  221. DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
  222. #endif
  223. DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
  224. Gpio_Conf_Data[index].usage,
  225. Gpio_Conf_Data[index].func,
  226. Gpio_Conf_Data[index].int_type,
  227. Gpio_Conf_Data[index].pull,
  228. mmio_conf0));
  229. //
  230. // Step 1: PadVal Programming
  231. //
  232. pad_val.dw = MmioRead32(mmio_padval);
  233. //
  234. // Config PAD_VAL only for GPIO (Non-Native) Pin
  235. //
  236. if(Native != Gpio_Conf_Data[index].usage)
  237. {
  238. pad_val.dw &= ~0x6; // Clear bits 1:2
  239. pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
  240. //
  241. // set GPO default value
  242. //
  243. if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
  244. {
  245. pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
  246. }
  247. }
  248. DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
  249. MmioWrite32(mmio_padval, pad_val.dw);
  250. //
  251. // Step 2: CONF0 Programming
  252. // Read GPIO default CONF0 value, which is assumed to be default value after reset.
  253. //
  254. conf0_val.dw = MmioRead32(mmio_conf0);
  255. //
  256. // Set Function #
  257. //
  258. conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
  259. if(GPO == Gpio_Conf_Data[index].usage)
  260. {
  261. //
  262. // If used as GPO, then internal pull need to be disabled
  263. //
  264. conf0_val.r.Pull_assign = 0; // Non-pull
  265. }
  266. else
  267. {
  268. //
  269. // Set PullUp / PullDown
  270. //
  271. if(P_20K_H == Gpio_Conf_Data[index].pull)
  272. {
  273. conf0_val.r.Pull_assign = 0x1; // PullUp
  274. conf0_val.r.Pull_strength = 0x2;// 20K
  275. }
  276. else if(P_20K_L == Gpio_Conf_Data[index].pull)
  277. {
  278. conf0_val.r.Pull_assign = 0x2; // PullDown
  279. conf0_val.r.Pull_strength = 0x2;// 20K
  280. }
  281. else if(P_NONE == Gpio_Conf_Data[index].pull)
  282. {
  283. conf0_val.r.Pull_assign = 0; // Non-pull
  284. }
  285. else
  286. {
  287. ASSERT(FALSE); // Invalid value
  288. }
  289. }
  290. //
  291. // Set INT Trigger Type
  292. //
  293. conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
  294. //
  295. // Set INT Trigger Type
  296. //
  297. if(TRIG_ == Gpio_Conf_Data[index].int_type)
  298. {
  299. //
  300. // Interrupt not capable, clear bits 27:24
  301. //
  302. }
  303. else
  304. {
  305. conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
  306. }
  307. DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
  308. //
  309. // Write back the targeted GPIO config value according to platform (board) GPIO setting
  310. //
  311. MmioWrite32 (mmio_conf0, conf0_val.dw);
  312. }
  313. // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
  314. // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
  315. //
  316. }
  317. VOID
  318. EFIAPI
  319. SpiBiosProtectionFunction(
  320. EFI_EVENT Event,
  321. VOID *Context
  322. )
  323. {
  324. UINTN mPciD31F0RegBase;
  325. UINTN BiosFlaLower0;
  326. UINTN BiosFlaLimit0;
  327. UINTN BiosFlaLower1;
  328. UINTN BiosFlaLimit1;
  329. BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
  330. BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
  331. BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
  332. BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
  333. mPciD31F0RegBase = MmPciAddress (0,
  334. DEFAULT_PCI_BUS_NUMBER_PCH,
  335. PCI_DEVICE_NUMBER_PCH_LPC,
  336. PCI_FUNCTION_NUMBER_PCH_LPC,
  337. 0
  338. );
  339. SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
  340. //
  341. //Set SMM_BWP, WPD and LE bit
  342. //
  343. MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
  344. MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
  345. MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
  346. //
  347. //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
  348. //
  349. if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
  350. (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
  351. //
  352. //Already locked. we could take no action here
  353. //
  354. DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
  355. return;
  356. }
  357. //
  358. //Set PR0
  359. //
  360. MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
  361. B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
  362. (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
  363. //
  364. //Set PR1
  365. //
  366. MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
  367. B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
  368. (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
  369. //
  370. //Lock down PRx
  371. //
  372. MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
  373. //
  374. // Verify if it's really locked.
  375. //
  376. if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
  377. DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));
  378. }
  379. return;
  380. }
  381. VOID
  382. EFIAPI
  383. InitPciDevPME (
  384. EFI_EVENT Event,
  385. VOID *Context
  386. )
  387. {
  388. UINTN VarSize;
  389. VarSize = sizeof(SYSTEM_CONFIGURATION);
  390. gRT->GetVariable(
  391. NORMAL_SETUP_NAME,
  392. &gEfiNormalSetupGuid,
  393. NULL,
  394. &VarSize,
  395. &mSystemConfiguration
  396. );
  397. //
  398. //Program HDA PME_EN
  399. //
  400. PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
  401. //
  402. //Program SATA PME_EN
  403. //
  404. PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
  405. DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
  406. if (mSystemConfiguration.EhciPllCfgEnable != 1) {
  407. //
  408. //Program EHCI PME_EN
  409. //
  410. PchMmPci32Or (
  411. 0,
  412. 0,
  413. PCI_DEVICE_NUMBER_PCH_USB,
  414. PCI_FUNCTION_NUMBER_PCH_EHCI,
  415. R_PCH_EHCI_PWR_CNTL_STS,
  416. B_PCH_EHCI_PWR_CNTL_STS_PME_EN
  417. );
  418. }
  419. {
  420. UINTN EhciPciMmBase;
  421. UINT32 Buffer32 = 0;
  422. EhciPciMmBase = MmPciAddress (0,
  423. 0,
  424. PCI_DEVICE_NUMBER_PCH_USB,
  425. PCI_FUNCTION_NUMBER_PCH_EHCI,
  426. 0
  427. );
  428. DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
  429. Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
  430. DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
  431. }
  432. }
  433. VOID
  434. EFIAPI
  435. InitThermalZone (
  436. EFI_EVENT Event,
  437. VOID *Context
  438. )
  439. {
  440. UINTN VarSize;
  441. EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
  442. VarSize = sizeof(SYSTEM_CONFIGURATION);
  443. gRT->GetVariable(
  444. NORMAL_SETUP_NAME,
  445. &gEfiNormalSetupGuid,
  446. NULL,
  447. &VarSize,
  448. &mSystemConfiguration
  449. );
  450. gBS->LocateProtocol (
  451. &gEfiGlobalNvsAreaProtocolGuid,
  452. NULL,
  453. (void **)&GlobalNvsArea
  454. );
  455. GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
  456. GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
  457. }
  458. #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
  459. #endif
  460. EFI_STATUS
  461. EFIAPI
  462. TristateLpcGpioS0i3Config (
  463. UINT32 Gpio_Mmio_Offset,
  464. UINT32 Gpio_Pin_Num,
  465. CFIO_PNP_INIT* Gpio_Conf_Data
  466. )
  467. {
  468. UINT32 index;
  469. UINT32 mmio_reg;
  470. UINT32 mmio_val;
  471. DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
  472. for(index=0; index < Gpio_Pin_Num; index++)
  473. {
  474. mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
  475. MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
  476. mmio_val = 0;
  477. mmio_val = MmioRead32(mmio_reg);
  478. DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
  479. }
  480. return EFI_SUCCESS;
  481. }
  482. /**
  483. Event Notification during exit boot service to enabel ACPI mode
  484. Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
  485. Clear all ACPI event status and disable all ACPI events
  486. Disable PM sources except power button
  487. Clear status bits
  488. Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
  489. Update EC to disable SMI and enable SCI
  490. Enable SCI
  491. Enable PME_B0_EN in GPE0a_EN
  492. @param Event - EFI Event Handle
  493. @param Context - Pointer to Notify Context
  494. @retval Nothing
  495. **/
  496. VOID
  497. EFIAPI
  498. EnableAcpiCallback (
  499. IN EFI_EVENT Event,
  500. IN VOID *Context
  501. )
  502. {
  503. UINT32 RegData32;
  504. UINT16 Pm1Cnt;
  505. UINT16 AcpiBase;
  506. UINT32 Gpe0aEn;
  507. AcpiBase = MmioRead16 (
  508. PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
  509. PCI_DEVICE_NUMBER_PCH_LPC,
  510. PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
  511. ) & B_PCH_LPC_ACPI_BASE_BAR;
  512. DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
  513. //
  514. // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
  515. //
  516. RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
  517. RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
  518. IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
  519. RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
  520. RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
  521. IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
  522. //
  523. // Disable PM sources except power button
  524. // power button is enabled only for PCAT. Disabled it on Tablet platform
  525. //
  526. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
  527. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
  528. //
  529. // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
  530. // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
  531. //
  532. IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
  533. IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
  534. RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
  535. RegData32 &= ~(BIT7);
  536. IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
  537. //
  538. // Enable SCI
  539. //
  540. Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
  541. Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
  542. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  543. IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
  544. //
  545. // Enable PME_B0_EN in GPE0a_EN
  546. // Caution: Enable PME_B0_EN must be placed after enabling SCI.
  547. // Otherwise, USB PME could not be handled as SMI event since no handler is there.
  548. //
  549. Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
  550. Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
  551. IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
  552. }
  553. /**
  554. Routine Description:
  555. This is the standard EFI driver point for the Driver. This
  556. driver is responsible for setting up any platform specific policy or
  557. initialization information.
  558. @param ImageHandle Handle for the image of this driver.
  559. @param SystemTable Pointer to the EFI System Table.
  560. @retval EFI_SUCCESS Policy decisions set.
  561. **/
  562. EFI_STATUS
  563. EFIAPI
  564. InitializePlatform (
  565. IN EFI_HANDLE ImageHandle,
  566. IN EFI_SYSTEM_TABLE *SystemTable
  567. )
  568. {
  569. EFI_STATUS Status;
  570. UINTN VarSize;
  571. EFI_HANDLE Handle = NULL;
  572. EFI_EVENT mEfiExitBootServicesEvent;
  573. EFI_EVENT RtcEvent;
  574. VOID *RtcCallbackReg = NULL;
  575. mImageHandle = ImageHandle;
  576. Status = gBS->InstallProtocolInterface (
  577. &Handle,
  578. &gEfiSpeakerInterfaceProtocolGuid,
  579. EFI_NATIVE_INTERFACE,
  580. &mSpeakerInterface
  581. );
  582. Status = gBS->LocateProtocol (
  583. &gEfiPciRootBridgeIoProtocolGuid,
  584. NULL,
  585. (VOID **) &mPciRootBridgeIo
  586. );
  587. ASSERT_EFI_ERROR (Status);
  588. VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
  589. Status = gRT->GetVariable(
  590. L"PlatformInfo",
  591. &gEfiVlv2VariableGuid,
  592. NULL,
  593. &VarSize,
  594. &mPlatformInfo
  595. );
  596. //
  597. // Initialize Product Board ID variable
  598. //
  599. InitMfgAndConfigModeStateVar();
  600. InitPlatformBootMode();
  601. //
  602. // Install Observable protocol
  603. //
  604. InitializeObservableProtocol();
  605. Status = SaveSetupRecoveryVar();
  606. if (EFI_ERROR (Status)) {
  607. DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable failed \n"));
  608. }
  609. VarSize = sizeof(SYSTEM_CONFIGURATION);
  610. Status = gRT->GetVariable(
  611. NORMAL_SETUP_NAME,
  612. &gEfiNormalSetupGuid,
  613. NULL,
  614. &VarSize,
  615. &mSystemConfiguration
  616. );
  617. if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
  618. //The setup variable is corrupted
  619. VarSize = sizeof(SYSTEM_CONFIGURATION);
  620. Status = gRT->GetVariable(
  621. L"SetupRecovery",
  622. &gEfiNormalSetupGuid,
  623. NULL,
  624. &VarSize,
  625. &mSystemConfiguration
  626. );
  627. ASSERT_EFI_ERROR (Status);
  628. Status = gRT->SetVariable (
  629. NORMAL_SETUP_NAME,
  630. &gEfiNormalSetupGuid,
  631. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  632. sizeof(SYSTEM_CONFIGURATION),
  633. &mSystemConfiguration
  634. );
  635. }
  636. Status = EfiCreateEventReadyToBootEx (
  637. TPL_CALLBACK,
  638. ReadyToBootFunction,
  639. NULL,
  640. &mReadyToBootEvent
  641. );
  642. //
  643. // Create a ReadyToBoot Event to run the PME init process
  644. //
  645. Status = EfiCreateEventReadyToBootEx (
  646. TPL_CALLBACK,
  647. InitPciDevPME,
  648. NULL,
  649. &mReadyToBootEvent
  650. );
  651. //
  652. // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
  653. //
  654. if(mSystemConfiguration.SpiRwProtect==1) {
  655. Status = EfiCreateEventReadyToBootEx (
  656. TPL_CALLBACK,
  657. SpiBiosProtectionFunction,
  658. NULL,
  659. &mReadyToBootEvent
  660. );
  661. }
  662. //
  663. // Create a ReadyToBoot Event to run the thermalzone init process
  664. //
  665. Status = EfiCreateEventReadyToBootEx (
  666. TPL_CALLBACK,
  667. InitThermalZone,
  668. NULL,
  669. &mReadyToBootEvent
  670. );
  671. ReportStatusCodeEx (
  672. EFI_PROGRESS_CODE,
  673. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
  674. 0,
  675. &gEfiCallerIdGuid,
  676. NULL,
  677. NULL,
  678. 0
  679. );
  680. #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
  681. //
  682. // Initialize Sensor Info variable
  683. //
  684. InitializeSensorInfoVariable();
  685. #endif
  686. InitPchPlatformPolicy(&mPlatformInfo);
  687. InitVlvPlatformPolicy();
  688. //
  689. // Add usb policy
  690. //
  691. InitializeClockRouting();
  692. InitializeSlotInfo();
  693. InitTcoReset();
  694. //
  695. //Init ExI
  696. //
  697. InitExI();
  698. ReportStatusCodeEx (
  699. EFI_PROGRESS_CODE,
  700. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
  701. 0,
  702. &gEfiCallerIdGuid,
  703. NULL,
  704. NULL,
  705. 0
  706. );
  707. //
  708. // Install PCI Bus Driver Hook
  709. //
  710. PciBusDriverHook();
  711. InitItk();
  712. ReportStatusCodeEx (
  713. EFI_PROGRESS_CODE,
  714. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
  715. 0,
  716. &gEfiCallerIdGuid,
  717. NULL,
  718. NULL,
  719. 0
  720. );
  721. //
  722. // Initialize Password States and Callbacks
  723. //
  724. PchInitBeforeBoot();
  725. #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
  726. #endif
  727. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  728. //
  729. // Re-write Firmware ID if it is changed
  730. //
  731. InitFirmwareId();
  732. #endif
  733. ReportStatusCodeEx (
  734. EFI_PROGRESS_CODE,
  735. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
  736. 0,
  737. &gEfiCallerIdGuid,
  738. NULL,
  739. NULL,
  740. 0
  741. );
  742. Status = gBS->CreateEventEx (
  743. EVT_NOTIFY_SIGNAL,
  744. TPL_NOTIFY,
  745. EnableAcpiCallback,
  746. NULL,
  747. &gEfiEventExitBootServicesGuid,
  748. &mEfiExitBootServicesEvent
  749. );
  750. //
  751. // Adjust RTC deafult time to be BIOS-built time.
  752. //
  753. Status = gBS->CreateEvent (
  754. EVT_NOTIFY_SIGNAL,
  755. TPL_CALLBACK,
  756. AdjustDefaultRtcTimeCallback,
  757. NULL,
  758. &RtcEvent
  759. );
  760. if (!EFI_ERROR (Status)) {
  761. Status = gBS->RegisterProtocolNotify (
  762. &gEfiEndOfDxeEventGroupGuid,
  763. RtcEvent,
  764. &RtcCallbackReg
  765. );
  766. }
  767. return EFI_SUCCESS;
  768. }
  769. /**
  770. Source Or Destination with Length bytes.
  771. @param[in] Destination Target memory
  772. @param[in] Source Source memory
  773. @param[in] Length Number of bytes
  774. @retval None
  775. **/
  776. VOID
  777. EfiOrMem (
  778. IN VOID *Destination,
  779. IN VOID *Source,
  780. IN UINTN Length
  781. )
  782. {
  783. CHAR8 *Destination8;
  784. CHAR8 *Source8;
  785. if (Source < Destination) {
  786. Destination8 = (CHAR8 *) Destination + Length - 1;
  787. Source8 = (CHAR8 *) Source + Length - 1;
  788. while (Length--) {
  789. *(Destination8--) |= *(Source8--);
  790. }
  791. } else {
  792. Destination8 = (CHAR8 *) Destination;
  793. Source8 = (CHAR8 *) Source;
  794. while (Length--) {
  795. *(Destination8++) |= *(Source8++);
  796. }
  797. }
  798. }
  799. VOID
  800. PchInitBeforeBoot()
  801. {
  802. //
  803. // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
  804. //
  805. S3BootScriptSaveMemWrite (
  806. S3BootScriptWidthUint32,
  807. (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
  808. 1,
  809. (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
  810. S3BootScriptSaveMemWrite (
  811. S3BootScriptWidthUint32,
  812. (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
  813. 1,
  814. (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
  815. S3BootScriptSaveMemWrite (
  816. S3BootScriptWidthUint16,
  817. (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
  818. 1,
  819. (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
  820. S3BootScriptSaveMemWrite (
  821. S3BootScriptWidthUint16,
  822. (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
  823. 1,
  824. (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
  825. //
  826. // Saved MTPMC_1 for S3 resume.
  827. //
  828. S3BootScriptSaveMemWrite (
  829. S3BootScriptWidthUint32,
  830. (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
  831. 1,
  832. (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
  833. return;
  834. }
  835. VOID
  836. EFIAPI
  837. ReadyToBootFunction (
  838. EFI_EVENT Event,
  839. VOID *Context
  840. )
  841. {
  842. //
  843. // save LAN info to a variable
  844. //
  845. if (NULL != mPciLanInfo) {
  846. gRT->SetVariable (
  847. L"PciLanInfo",
  848. &gEfiPciLanInfoGuid,
  849. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
  850. mPciLanCount * sizeof(PCI_LAN_INFO),
  851. mPciLanInfo
  852. );
  853. }
  854. if (NULL != mPciLanInfo) {
  855. gBS->FreePool (mPciLanInfo);
  856. mPciLanInfo = NULL;
  857. }
  858. }
  859. /**
  860. Initializes manufacturing and config mode setting.
  861. **/
  862. VOID
  863. InitMfgAndConfigModeStateVar()
  864. {
  865. EFI_PLATFORM_SETUP_ID *BootModeBuffer;
  866. VOID *HobList;
  867. HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
  868. if (HobList != NULL) {
  869. BootModeBuffer = GET_GUID_HOB_DATA (HobList);
  870. //
  871. // Check if in Manufacturing mode
  872. //
  873. if ( !CompareMem (
  874. &BootModeBuffer->SetupName,
  875. MANUFACTURE_SETUP_NAME,
  876. StrSize (MANUFACTURE_SETUP_NAME)
  877. ) ) {
  878. mMfgMode = TRUE;
  879. }
  880. }
  881. }
  882. /**
  883. Initializes manufacturing and config mode setting.
  884. **/
  885. VOID
  886. InitPlatformBootMode()
  887. {
  888. EFI_PLATFORM_SETUP_ID *BootModeBuffer;
  889. VOID *HobList;
  890. HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
  891. if (HobList != NULL) {
  892. BootModeBuffer = GET_GUID_HOB_DATA (HobList);
  893. mPlatformBootMode = BootModeBuffer->PlatformBootMode;
  894. }
  895. }
  896. /**
  897. Initializes ITK.
  898. **/
  899. VOID
  900. InitItk(
  901. )
  902. {
  903. EFI_STATUS Status;
  904. UINT16 ItkModBiosState;
  905. UINT8 Value;
  906. UINTN DataSize;
  907. UINT32 Attributes;
  908. //
  909. // Setup local variable according to ITK variable
  910. //
  911. //
  912. // Read ItkBiosModVar to determine if BIOS has been modified by ITK
  913. // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
  914. // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
  915. //
  916. DataSize = sizeof (Value);
  917. Status = gRT->GetVariable (
  918. ITK_BIOS_MOD_VAR_NAME,
  919. &gItkDataVarGuid,
  920. &Attributes,
  921. &DataSize,
  922. &Value
  923. );
  924. if (Status == EFI_NOT_FOUND) {
  925. //
  926. // Variable not found, hasn't been initialized, intialize to 0
  927. //
  928. Value=0x00;
  929. //
  930. // Write variable to flash.
  931. //
  932. gRT->SetVariable (
  933. ITK_BIOS_MOD_VAR_NAME,
  934. &gItkDataVarGuid,
  935. EFI_VARIABLE_RUNTIME_ACCESS |
  936. EFI_VARIABLE_NON_VOLATILE |
  937. EFI_VARIABLE_BOOTSERVICE_ACCESS,
  938. sizeof (Value),
  939. &Value
  940. );
  941. }
  942. if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
  943. if (Value == 0x00) {
  944. ItkModBiosState = 0x00;
  945. } else {
  946. ItkModBiosState = 0x01;
  947. }
  948. gRT->SetVariable (
  949. VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
  950. &gEfiNormalSetupGuid,
  951. EFI_VARIABLE_BOOTSERVICE_ACCESS,
  952. 2,
  953. (void *)&ItkModBiosState
  954. );
  955. }
  956. }
  957. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  958. /**
  959. Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
  960. **/
  961. STATIC
  962. VOID
  963. InitFirmwareId(
  964. )
  965. {
  966. EFI_STATUS Status;
  967. CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
  968. //
  969. // First try writing the variable without a password in case we are
  970. // upgrading from a BIOS without password protection on the FirmwareId
  971. //
  972. Status = gRT->SetVariable(
  973. (CHAR16 *)&gFirmwareIdName,
  974. &gFirmwareIdGuid,
  975. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
  976. EFI_VARIABLE_RUNTIME_ACCESS,
  977. sizeof( FIRMWARE_ID ) - 1,
  978. FIRMWARE_ID
  979. );
  980. if (Status == EFI_INVALID_PARAMETER) {
  981. //
  982. // Since setting the firmware id without the password failed,
  983. // a password must be required.
  984. //
  985. Status = gRT->SetVariable(
  986. (CHAR16 *)&FirmwareIdNameWithPassword,
  987. &gFirmwareIdGuid,
  988. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
  989. EFI_VARIABLE_RUNTIME_ACCESS,
  990. sizeof( FIRMWARE_ID ) - 1,
  991. FIRMWARE_ID
  992. );
  993. }
  994. }
  995. #endif
  996. VOID
  997. UpdateDVMTSetup(
  998. )
  999. {
  1000. //
  1001. // Workaround to support IIA bug.
  1002. // IIA request to change option value to 4, 5 and 7 relatively
  1003. // instead of 1, 2, and 3 which follow Lakeport Specs.
  1004. // Check option value, temporary hardcode GraphicsDriverMemorySize
  1005. // Option value to fulfill IIA requirment. So that user no need to
  1006. // load default and update setupvariable after update BIOS.
  1007. // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
  1008. // *This is for broadwater and above product only.
  1009. //
  1010. SYSTEM_CONFIGURATION SystemConfiguration;
  1011. UINTN VarSize;
  1012. EFI_STATUS Status;
  1013. VarSize = sizeof(SYSTEM_CONFIGURATION);
  1014. Status = gRT->GetVariable(
  1015. NORMAL_SETUP_NAME,
  1016. &gEfiNormalSetupGuid,
  1017. NULL,
  1018. &VarSize,
  1019. &SystemConfiguration
  1020. );
  1021. if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
  1022. //The setup variable is corrupted
  1023. VarSize = sizeof(SYSTEM_CONFIGURATION);
  1024. Status = gRT->GetVariable(
  1025. L"SetupRecovery",
  1026. &gEfiNormalSetupGuid,
  1027. NULL,
  1028. &VarSize,
  1029. &SystemConfiguration
  1030. );
  1031. ASSERT_EFI_ERROR (Status);
  1032. }
  1033. if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
  1034. switch (SystemConfiguration.GraphicsDriverMemorySize){
  1035. case 1:
  1036. SystemConfiguration.GraphicsDriverMemorySize = 4;
  1037. break;
  1038. case 2:
  1039. SystemConfiguration.GraphicsDriverMemorySize = 5;
  1040. break;
  1041. case 3:
  1042. SystemConfiguration.GraphicsDriverMemorySize = 7;
  1043. break;
  1044. default:
  1045. break;
  1046. }
  1047. Status = gRT->SetVariable (
  1048. NORMAL_SETUP_NAME,
  1049. &gEfiNormalSetupGuid,
  1050. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  1051. sizeof(SYSTEM_CONFIGURATION),
  1052. &SystemConfiguration
  1053. );
  1054. }
  1055. }
  1056. UINT8
  1057. ReadCmosBank1Byte (
  1058. IN EFI_CPU_IO2_PROTOCOL *CpuIo,
  1059. IN UINT8 Index
  1060. )
  1061. {
  1062. UINT8 Data;
  1063. CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
  1064. CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
  1065. return Data;
  1066. }
  1067. VOID
  1068. WriteCmosBank1Byte (
  1069. IN EFI_CPU_IO2_PROTOCOL *CpuIo,
  1070. IN UINT8 Index,
  1071. IN UINT8 Data
  1072. )
  1073. {
  1074. CpuIo->Io.Write (
  1075. CpuIo,
  1076. EfiCpuIoWidthUint8,
  1077. 0x72,
  1078. 1,
  1079. &Index
  1080. );
  1081. CpuIo->Io.Write (
  1082. CpuIo,
  1083. EfiCpuIoWidthUint8,
  1084. 0x73,
  1085. 1,
  1086. &Data
  1087. );
  1088. }