Configuration.h 27 KB

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  1. /*++
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. Configuration.h
  6. Abstract:
  7. Driver configuration include file
  8. --*/
  9. #ifndef _CONFIGURATION_H
  10. #define _CONFIGURATION_H
  11. #define EFI_NON_DEVICE_CLASS 0x00
  12. #define EFI_DISK_DEVICE_CLASS 0x01
  13. #define EFI_VIDEO_DEVICE_CLASS 0x02
  14. #define EFI_NETWORK_DEVICE_CLASS 0x04
  15. #define EFI_INPUT_DEVICE_CLASS 0x08
  16. #define EFI_ON_BOARD_DEVICE_CLASS 0x10
  17. #define EFI_OTHER_DEVICE_CLASS 0x20
  18. //
  19. // Processor labels
  20. //
  21. #define PROCESSOR_HT_MODE 0x0100
  22. #define PROCESSOR_FSB_MULTIPLIER 0x0101
  23. #define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
  24. //
  25. // Memory labels
  26. //
  27. #define MEMORY_SLOT1_SPEED 0x0200
  28. #define MEMORY_SLOT2_SPEED 0x0201
  29. #define MEMORY_SLOT3_SPEED 0x0202
  30. #define MEMORY_SLOT4_SPEED 0x0203
  31. #define END_MEMORY_SLOT_SPEED 0x020F
  32. #define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
  33. #define UCLK_RATIO_CONTROL 0x0212
  34. //
  35. // Language label
  36. //
  37. #define FRONT_PAGE_ITEM_LANGUAGE 0x300
  38. //
  39. // Boot Labels
  40. //
  41. #define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
  42. #define BOOT_DEVICE_PRIORITY_END 0x0401
  43. #define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
  44. #define BOOT_OPTICAL_DEVICE_END 0x0411
  45. #define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
  46. #define BOOT_REMOVABLE_DEVICE_END 0x0421
  47. #define BOOT_PXE_DEVICE_BEGIN 0x0430
  48. #define BOOT_PXE_DEVICE_END 0x0431
  49. #define BOOT_MENU_TYPE_BEGIN 0x0440
  50. #define BOOT_MENU_TYPE_END 0x0441
  51. #define BOOT_USB_DEVICE_BEGIN 0x0450
  52. #define BOOT_USB_DEVICE_END 0x0451
  53. #define BOOT_USB_FIRST_BEGIN 0x0460
  54. #define BOOT_USB_FIRST_END 0x0461
  55. #define BOOT_UEFI_BEGIN 0x0470
  56. #define BOOT_UEFI_END 0x0471
  57. #define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
  58. #define BOOT_USB_UNAVAILABLE_END 0x0481
  59. #define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
  60. #define BOOT_CD_UNAVAILABLE_END 0x0491
  61. #define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
  62. #define BOOT_FDD_UNAVAILABLE_END 0x04A1
  63. #define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
  64. #define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
  65. #define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
  66. #define BOOT_USB_OPT_LABEL_END 0x04C1
  67. #define VAR_EQ_ADMIN_NAME 0x0041 // A
  68. #define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
  69. #define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
  70. #define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
  71. #define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
  72. #define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
  73. #define VAR_EQ_CPU_EE_NAME 0x0045 // E
  74. #define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
  75. #define VAR_EQ_HT_MODE_NAME 0x0048 // H
  76. #define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
  77. #define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
  78. #define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
  79. #define VAR_EQ_CPU_LOCK_NAME 0x004C // L
  80. #define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
  81. #define VAR_EQ_NX_MODE_NAME 0x004E // N
  82. #define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
  83. #define VAR_EQ_RAID_MODE_NAME 0x0052 // R
  84. #define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
  85. #define VAR_EQ_1394_MODE_NAME 0x0054 // T
  86. #define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
  87. #define VAR_EQ_USER_NAME 0x0055 // U
  88. #define VAR_EQ_USER_DECIMAL_NAME L"85"
  89. #define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
  90. #define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
  91. #define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
  92. #define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
  93. #define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
  94. #define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
  95. #define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
  96. #define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
  97. #define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
  98. #define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
  99. #define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
  100. #define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
  101. #define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
  102. #define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
  103. #define VAR_EQ_TPM_MODE_NAME 0x005E // ^
  104. #define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
  105. #define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
  106. #define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
  107. #define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
  108. #define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
  109. #define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
  110. #define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
  111. #define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
  112. #define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
  113. #define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
  114. #define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
  115. #define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
  116. #define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
  117. #define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
  118. #define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
  119. #define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
  120. #define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
  121. #define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
  122. #define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
  123. #define VAR_EQ_2_SATA_NAME 0x0068 // ??
  124. #define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
  125. #define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
  126. #define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
  127. #define VAR_EQ_AMT_MODE_NAME 0x006A // ??
  128. #define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
  129. #define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
  130. #define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
  131. #define VAR_EQ_VT_NAME 0x006C
  132. #define VAR_EQ_VT_DECIMAL_NAME L"108"
  133. #define VAR_EQ_LT_NAME 0x006D
  134. #define VAR_EQ_LT_DECIMAL_NAME L"109"
  135. #define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
  136. #define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
  137. #define VAR_EQ_HPET_NAME 0x006F
  138. #define VAR_EQ_HPET_DECIMAL_NAME L"111"
  139. #define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
  140. #define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
  141. #define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
  142. #define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
  143. #define VAR_EQ_CPU_CMP_NAME 0x0072
  144. #define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
  145. #define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
  146. #define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
  147. #define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
  148. #define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
  149. #define VAR_EQ_AFSC_SETUP_NAME 0x0075
  150. #define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
  151. #define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
  152. #define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
  153. #define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
  154. #define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
  155. #define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
  156. #define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
  157. #define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
  158. #define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
  159. #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A
  160. #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"
  161. #define VAR_EQ_CPU_FSB_NAME 0x007B //
  162. #define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
  163. #define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
  164. #define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
  165. #define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
  166. #define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
  167. #define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
  168. #define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
  169. #define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
  170. #define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
  171. #define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
  172. #define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
  173. #define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
  174. #define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
  175. #define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled
  176. #define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
  177. #define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
  178. #define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
  179. #define VAR_EQ_USB_2_NAME 0x0084 //
  180. #define VAR_EQ_USB_2_DECIMAL_NAME L"132"
  181. #define VAR_EQ_RVP_NAME 0x0085 //
  182. #define VAR_EQ_RVP_DECIMAL_NAME L"133"
  183. #define VAR_EQ_ECIR_NAME 0x0086
  184. #define VAR_EQ_ECIR_DECIMAL_NAME L"134"
  185. #define VAR_EQ_WAKONS5KB_NAME 0x0087
  186. #define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
  187. #define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
  188. #define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
  189. #define VAR_EQ_FINGERPRINT_NAME 0x0089
  190. #define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
  191. #define VAR_EQ_BLUETOOTH_NAME 0x008A
  192. #define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
  193. #define VAR_EQ_WLAN_NAME 0x008B
  194. #define VAR_EQ_WLAN_DECIMAL_NAME L"139"
  195. #define VAR_EQ_1_PATA_NAME 0x008C
  196. #define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
  197. #define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
  198. #define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
  199. #define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
  200. #define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
  201. #define VAR_EQ_XE_MODE_CAP_NAME 0x008F
  202. #define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
  203. #define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
  204. #define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
  205. #define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
  206. #define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
  207. #define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
  208. #define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
  209. #define VAR_EQ_LVDS_NAME 0x0093
  210. #define VAR_EQ_LVDS_DECIMAL_NAME L"147"
  211. #define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
  212. #define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
  213. #define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
  214. #define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
  215. #define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
  216. #define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
  217. #define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
  218. #define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
  219. #define VAR_EQ_VIDEO_SLOT_NAME 0x0098
  220. #define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
  221. #define VAR_EQ_HDMI_SLOT_NAME 0x0099
  222. #define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
  223. #define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
  224. #define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
  225. #define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
  226. #define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
  227. #define VAR_EQ_MSATA_HIDE_NAME 0x009f
  228. #define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
  229. #define VAR_EQ_PCI_SLOT1_NAME 0x00a0
  230. #define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
  231. #define VAR_EQ_PCI_SLOT2_NAME 0x00a1
  232. #define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
  233. //
  234. // Generic Form Ids
  235. //
  236. #define ROOT_FORM_ID 1
  237. //
  238. // Advance Page. Do not have to be sequential but have to be unique
  239. //
  240. #define CONFIGURATION_ROOT_FORM_ID 2
  241. #define BOOT_CONFIGURATION_ID 3
  242. #define ONBOARDDEVICE_CONFIGURATION_ID 4
  243. #define DRIVE_CONFIGURATION_ID 5
  244. #define FLOPPY_CONFIGURATION_ID 6
  245. #define EVENT_LOG_CONFIGURATION_ID 7
  246. #define VIDEO_CONFIGURATION_ID 8
  247. #define USB_CONFIGURATION_ID 9
  248. #define HARDWARE_MONITOR_CONFIGURATION_ID 10
  249. #define VIEW_EVENT_LOG_CONFIGURATION_ID 11
  250. #define MEMORY_OVERRIDE_ID 12
  251. #define CHIPSET_CONFIGURATION_ID 13
  252. #define BURN_IN_MODE_ID 14
  253. #define PCI_EXPRESS_ID 15
  254. #define MANAGEMENT_CONFIGURATION_ID 16
  255. #define CPU_CONFIGURATION_ID 17
  256. #define PCI_CONFIGURATION_ID 18
  257. #define SECURITY_CONFIGURATION_ID 19
  258. #define ZIP_CONFIGURATION_ID 20
  259. #define AFSC_FAN_CONTROL_ID 21
  260. #define VFR_FORMID_CSI 22
  261. #define VFR_FORMID_MEMORY 23
  262. #define VFR_FORMID_IOH 24
  263. #define VFR_FORMID_CPU_CSI 25
  264. #define VFR_FORMID_IOH_CONFIG 26
  265. #define VFR_FORMID_VTD 27
  266. #define VFR_FORMID_PCIE_P0 28
  267. #define VFR_FORMID_PCIE_P1 29
  268. #define VFR_FORMID_PCIE_P2 30
  269. #define VFR_FORMID_PCIE_P3 31
  270. #define VFR_FORMID_PCIE_P4 32
  271. #define VFR_FORMID_PCIE_P5 33
  272. #define VFR_FORMID_PCIE_P6 34
  273. #define VFR_FORMID_PCIE_P7 35
  274. #define VFR_FORMID_PCIE_P8 36
  275. #define VFR_FORMID_PCIE_P9 37
  276. #define VFR_FORMID_PCIE_P10 38
  277. #define VFR_FID_SKT0 39
  278. #define VFR_FID_IOH0 40
  279. #define VFR_FID_IOH_DEV_HIDE 41
  280. #define PROCESSOR_OVERRIDES_FORM_ID 42
  281. #define BUS_OVERRIDES_FORM_ID 43
  282. #define REF_OVERRIDES_FORM_ID 44
  283. #define MEMORY_INFORMATION_ID 45
  284. #define LVDS_WARNING_ID 46
  285. #define LVDS_CONFIGURATION_ID 47
  286. #define PCI_SLOT_CONFIGURATION_ID 48
  287. #define HECETA_CONFIGURATION_ID 49
  288. #define LVDS_EXPERT_CONFIGURATION_ID 50
  289. #define PCI_SLOT_7_ID 51
  290. #define PCI_SLOT_6_ID 52
  291. #define PCI_SLOT_5_ID 53
  292. #define PCI_SLOT_4_ID 54
  293. #define PCI_SLOT_3_ID 55
  294. #define PCI_SLOT_2_ID 56
  295. #define PCI_SLOT_1_ID 57
  296. #define BOOT_DISPLAY_ID 58
  297. #define CPU_PWR_CONFIGURATION_ID 59
  298. #define FSC_CONFIGURATION_ID 60
  299. #define FSC_CPU_TEMPERATURE_FORM_ID 61
  300. #define FSC_VTT_VOLTAGE_FORM_ID 62
  301. #define FSC_FEATURES_CONTROL_ID 63
  302. #define FSC_FAN_CONFIGURATION_ID 64
  303. #define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
  304. #define FSC_FRONT_FAN_CONFIGURATION_ID 66
  305. #define FSC_REAR_FAN_CONFIGURATION_ID 67
  306. #define FSC_AUX_FAN_CONFIGURATION_ID 68
  307. #define FSC_12_VOLTAGE_FORM_ID 69
  308. #define FSC_5_VOLTAGE_FORM_ID 70
  309. #define FSC_3P3_VOLTAGE_FORM_ID 71
  310. #define FSC_2P5_VOLTAGE_FORM_ID 72
  311. #define FSC_VCC_VOLTAGE_FORM_ID 73
  312. #define FSC_PCH_TEMPERATURE_FORM_ID 74
  313. #define FSC_MEM_TEMPERATURE_FORM_ID 75
  314. #define FSC_VR_TEMPERATURE_FORM_ID 76
  315. #define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
  316. #define FSC_5BACKUP_VOLTAGE_FORM_ID 78
  317. #define ROOT_MAIN_FORM_ID 79
  318. #define ROOT_BOOT_FORM_ID 80
  319. #define ROOT_MAINTENANCE_ID 81
  320. #define ROOT_POWER_FORM_ID 82
  321. #define ROOT_SECURITY_FORM_ID 83
  322. #define ROOT_PERFORMANCE_FORM_ID 84
  323. #define ROOT_SYSTEM_SETUP_FORM_ID 85
  324. #define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
  325. #define THERMAL_CONFIG_FORM_ID 87
  326. #define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
  327. #define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
  328. #define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
  329. #define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
  330. #define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
  331. #define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
  332. #define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
  333. #define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
  334. //
  335. // Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
  336. //
  337. #define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
  338. #define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
  339. #define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
  340. #define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003
  341. #define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
  342. #define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
  343. #define ADVANCE_LVDS_CALLBACK_KEY 0x2010
  344. //
  345. // Main Callback Keys. Do not have to be sequential but have to be unique
  346. //
  347. #define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
  348. //
  349. // Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
  350. //
  351. #define POWER_HARDWARE_CALLBACK_KEY 0x4000
  352. //
  353. // Performance Callback Keys. Do not have to be sequential but have to be unique
  354. //
  355. #define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
  356. #define PERFORMANCE_CALLBACK_KEY 0x5001
  357. #define BUS_OVERRIDES_CALLBACK_KEY 0x5002
  358. #define MEMORY_CFG_CALLBACK_KEY 0x5003
  359. #define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
  360. #define MEMORY_RATIO_CALLBACK_KEY 0x5005
  361. #define MEMORY_MODE_CALLBACK_KEY 0x5006
  362. //
  363. // Security Callback Keys. Do not have to be sequential but have to be unique
  364. //
  365. #define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
  366. #define SECURITY_USER_CALLBACK_KEY 0x1001
  367. #define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
  368. #define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
  369. #define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
  370. #define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
  371. #define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
  372. #define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
  373. //
  374. // Boot Callback Keys. Do not have to be sequential but have to be unique
  375. //
  376. #define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
  377. #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
  378. #define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
  379. #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
  380. //
  381. // IDCC/Setup FSB Frequency Override Range
  382. //
  383. #define EFI_IDCC_FSB_MIN 133
  384. #define EFI_IDCC_FSB_MAX 240
  385. #define EFI_IDCC_FSB_STEP 1
  386. //
  387. // Reference voltage
  388. //
  389. #define EFI_REF_DAC_MIN 0
  390. #define EFI_REF_DAC_MAX 255
  391. #define EFI_GTLREF_DEF 170
  392. #define EFI_DDRREF_DEF 128
  393. #define EFI_DIMMREF_DEF 128
  394. //
  395. // Setup FSB Frequency Override Range
  396. //
  397. #define EFI_FSB_MIN 133
  398. #define EFI_FSB_MAX 240
  399. #define EFI_FSB_STEP 1
  400. #define EFI_FSB_AUTOMATIC 0
  401. #define EFI_FSB_MANUAL 1
  402. #define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1
  403. #define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
  404. //
  405. // Setup processor multiplier range
  406. //
  407. #define EFI_PROC_MULT_MIN 5
  408. #define EFI_PROC_MULT_MAX 40
  409. #define EFI_PROC_MULT_STEP 1
  410. #define EFI_PROC_AUTOMATIC 0
  411. #define EFI_PROC_MANUAL 1
  412. #define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
  413. #define PROC_MULT_ENTRY_TYPE UINT8_TYPE
  414. //
  415. // PCI Express Definitions
  416. //
  417. #define EFI_PCIE_FREQ_DEF 0x0
  418. #define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
  419. #define PCIE_FREQ_ENTRY_7 0x7
  420. #define PCIE_FREQ_ENTRY_6 0x6
  421. #define PCIE_FREQ_ENTRY_5 0x5
  422. #define PCIE_FREQ_ENTRY_4 0x4
  423. #define PCIE_FREQ_ENTRY_3 0x3
  424. #define PCIE_FREQ_ENTRY_2 0x2
  425. #define PCIE_FREQ_ENTRY_1 0x1
  426. #define PCIE_FREQ_ENTRY_0 0x0
  427. #define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
  428. #define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
  429. PCIE_FREQ_ENTRY_1, \
  430. PCIE_FREQ_ENTRY_2, \
  431. PCIE_FREQ_ENTRY_3, \
  432. PCIE_FREQ_ENTRY_4, \
  433. PCIE_FREQ_ENTRY_5, \
  434. PCIE_FREQ_ENTRY_6, \
  435. PCIE_FREQ_ENTRY_7 }
  436. #define PCIE_FREQ_PRECISION 2
  437. #define PCIE_FREQ_VALUE_7 10924
  438. #define PCIE_FREQ_VALUE_6 10792
  439. #define PCIE_FREQ_VALUE_5 10660
  440. #define PCIE_FREQ_VALUE_4 10528
  441. #define PCIE_FREQ_VALUE_3 10396
  442. #define PCIE_FREQ_VALUE_2 10264
  443. #define PCIE_FREQ_VALUE_1 10132
  444. #define PCIE_FREQ_VALUE_0 10000
  445. #define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
  446. PCIE_FREQ_VALUE_1, \
  447. PCIE_FREQ_VALUE_2, \
  448. PCIE_FREQ_VALUE_3, \
  449. PCIE_FREQ_VALUE_4, \
  450. PCIE_FREQ_VALUE_5, \
  451. PCIE_FREQ_VALUE_6, \
  452. PCIE_FREQ_VALUE_7 }
  453. //
  454. // Memory Frequency Definitions
  455. //
  456. #define MEMORY_REF_FREQ_ENTRY_DEF 0x08
  457. #define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
  458. #define MEMORY_REF_FREQ_ENTRY_3 0x04
  459. #define MEMORY_REF_FREQ_ENTRY_2 0x00
  460. #define MEMORY_REF_FREQ_ENTRY_1 0x02
  461. #define MEMORY_REF_FREQ_ENTRY_0 0x01
  462. #define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
  463. #define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \
  464. MEMORY_REF_FREQ_ENTRY_1, \
  465. MEMORY_REF_FREQ_ENTRY_2, \
  466. MEMORY_REF_FREQ_ENTRY_3 }
  467. #define MEMORY_REF_FREQ_PRECISION 0
  468. #define MEMORY_REF_FREQ_VALUE_3 333
  469. #define MEMORY_REF_FREQ_VALUE_2 267
  470. #define MEMORY_REF_FREQ_VALUE_1 200
  471. #define MEMORY_REF_FREQ_VALUE_0 133
  472. #define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \
  473. MEMORY_REF_FREQ_VALUE_1, \
  474. MEMORY_REF_FREQ_VALUE_2, \
  475. MEMORY_REF_FREQ_VALUE_3 }
  476. //
  477. // Memory Reference Frequency Definitions
  478. //
  479. #define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
  480. #define MEMORY_FREQ_ENTRY_3 0x4
  481. #define MEMORY_FREQ_ENTRY_2 0x3
  482. #define MEMORY_FREQ_ENTRY_1 0x2
  483. #define MEMORY_FREQ_ENTRY_0 0x1
  484. #define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
  485. #define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \
  486. MEMORY_FREQ_ENTRY_1, \
  487. MEMORY_FREQ_ENTRY_2, \
  488. MEMORY_FREQ_ENTRY_3 }
  489. #define MEMORY_FREQ_MULT_PRECISION 2
  490. #define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
  491. #define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
  492. #define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
  493. #define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
  494. #define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
  495. #define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
  496. #define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
  497. #define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
  498. #define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
  499. #define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
  500. #define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
  501. #define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
  502. #define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
  503. #define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
  504. #define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
  505. #define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
  506. #define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
  507. MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
  508. MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
  509. MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
  510. #define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
  511. MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
  512. MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
  513. MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
  514. #define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
  515. MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
  516. MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
  517. MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
  518. #define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
  519. MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
  520. MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
  521. MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
  522. //
  523. // CAS Memory Timing Definitions
  524. //
  525. #define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
  526. #define MEMORY_TCL_ENTRY_3 0x2
  527. #define MEMORY_TCL_ENTRY_2 0x1
  528. #define MEMORY_TCL_ENTRY_1 0x0
  529. #define MEMORY_TCL_ENTRY_0 0x3
  530. #define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
  531. #define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \
  532. MEMORY_TCL_ENTRY_1, \
  533. MEMORY_TCL_ENTRY_2, \
  534. MEMORY_TCL_ENTRY_3 }
  535. #define MEMORY_TCL_PRECISION 0
  536. #define MEMORY_TCL_VALUE_3 3
  537. #define MEMORY_TCL_VALUE_2 4
  538. #define MEMORY_TCL_VALUE_1 5
  539. #define MEMORY_TCL_VALUE_0 6
  540. #define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
  541. MEMORY_TCL_VALUE_1, \
  542. MEMORY_TCL_VALUE_2, \
  543. MEMORY_TCL_VALUE_3 }
  544. //
  545. // TRCD Memory Timing Definitions
  546. //
  547. #define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
  548. #define MEMORY_TRCD_ENTRY_3 0x0
  549. #define MEMORY_TRCD_ENTRY_2 0x1
  550. #define MEMORY_TRCD_ENTRY_1 0x2
  551. #define MEMORY_TRCD_ENTRY_0 0x3
  552. #define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
  553. #define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \
  554. MEMORY_TRCD_ENTRY_1, \
  555. MEMORY_TRCD_ENTRY_2, \
  556. MEMORY_TRCD_ENTRY_3 }
  557. #define MEMORY_TRCD_PRECISION 0
  558. #define MEMORY_TRCD_VALUE_3 2
  559. #define MEMORY_TRCD_VALUE_2 3
  560. #define MEMORY_TRCD_VALUE_1 4
  561. #define MEMORY_TRCD_VALUE_0 5
  562. #define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
  563. MEMORY_TRCD_VALUE_1, \
  564. MEMORY_TRCD_VALUE_2, \
  565. MEMORY_TRCD_VALUE_3 }
  566. //
  567. // TRP Memory Timing Definitions
  568. //
  569. #define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
  570. #define MEMORY_TRP_ENTRY_3 0x0
  571. #define MEMORY_TRP_ENTRY_2 0x1
  572. #define MEMORY_TRP_ENTRY_1 0x2
  573. #define MEMORY_TRP_ENTRY_0 0x3
  574. #define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
  575. #define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \
  576. MEMORY_TRP_ENTRY_1, \
  577. MEMORY_TRP_ENTRY_2, \
  578. MEMORY_TRP_ENTRY_3 }
  579. #define MEMORY_TRP_PRECISION 0
  580. #define MEMORY_TRP_VALUE_3 2
  581. #define MEMORY_TRP_VALUE_2 3
  582. #define MEMORY_TRP_VALUE_1 4
  583. #define MEMORY_TRP_VALUE_0 5
  584. #define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
  585. MEMORY_TRP_VALUE_1, \
  586. MEMORY_TRP_VALUE_2, \
  587. MEMORY_TRP_VALUE_3 }
  588. //
  589. // TRAS Memory Timing Definitions
  590. //
  591. #define MEMORY_TRAS_MIN 4
  592. #define MEMORY_TRAS_MAX 18
  593. #define MEMORY_TRAS_STEP 1
  594. #define MEMORY_TRAS_DEFAULT 13
  595. #define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
  596. #define MEMORY_TRAS_TYPE UINT8_TYPE
  597. //
  598. // Uncore Multiplier Definitions
  599. //
  600. #define UCLK_RATIO_MIN 12
  601. #define UCLK_RATIO_MAX 30
  602. #define UCLK_RATIO_DEFAULT 20
  603. #endif // #ifndef _CONFIGURATION_H