Platform.h 4.1 KB

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  1. /*++
  2. Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. Platform.h
  6. Abstract:
  7. Pinetrail platform specific information.
  8. **/
  9. #ifndef _PLATFORM_H
  10. #define _PLATFORM_H
  11. #include "ChipsetAccess.h"
  12. #include "PlatformBaseAddresses.h"
  13. //
  14. // Number of P & T states supported.
  15. //
  16. #define NPTM_P_STATES_SUPPORTED 16
  17. #define NPTM_T_STATES_SUPPORTED 8
  18. //
  19. // I/O APIC IDs, the code uses math to generate the numbers
  20. // instead of using these defines.
  21. //
  22. #define ICH_IOAPIC (1 << 0)
  23. #define ICH_IOAPIC_ID 0x08
  24. //
  25. // Possible SMBus addresses that will be present.
  26. //
  27. #define SMBUS_ADDR_CH_A_1 0xA0
  28. #define SMBUS_ADDR_CH_A_2 0xA2
  29. #define SMBUS_ADDR_CH_B_1 0xA4
  30. #define SMBUS_ADDR_CH_B_2 0xA6
  31. #define SMBUS_ADDR_CH_C_1 0xA8
  32. #define SMBUS_ADDR_CH_C_2 0xAA
  33. #define SMBUS_ADDR_CH_D_1 0xAC
  34. #define SMBUS_ADDR_CH_D_2 0xAE
  35. #define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC
  36. #define SMBUS_ADDR_ICH_SLAVE 0x44
  37. #define SMBUS_ADDR_HECETA 0x5C
  38. #define SMBUS_ADDR_SMBARP 0xC2
  39. #define SMBUS_ADDR_82573E 0xC6
  40. #define SMBUS_ADDR_CLKCHIP 0xD2
  41. #define SMBUS_ADDR_BRD_REV 0x4E
  42. #define SMBUS_ADDR_DB803 0x82
  43. //
  44. // SMBus addresses that used on this platform.
  45. //
  46. #define PLATFORM_SMBUS_RSVD_ADDRESSES { \
  47. SMBUS_ADDR_CH_A_1, \
  48. SMBUS_ADDR_CH_A_2, \
  49. SMBUS_ADDR_HOST_CLK_BUFFER, \
  50. SMBUS_ADDR_ICH_SLAVE, \
  51. SMBUS_ADDR_SMBARP, \
  52. SMBUS_ADDR_CLKCHIP, \
  53. SMBUS_ADDR_BRD_REV, \
  54. SMBUS_ADDR_DB803 \
  55. }
  56. //
  57. // Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
  58. //
  59. #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
  60. //
  61. // CMOS usage
  62. //
  63. #define CMOS_CPU_BSP_SELECT 0x10
  64. #define CMOS_CPU_UP_MODE 0x11
  65. #define CMOS_CPU_RATIO_OFFSET 0x12
  66. #define CMOS_CPU_CORE_HT_OFFSET 0x13
  67. #define CMOS_EFI_DEBUG 0x14
  68. #define CMOS_CPU_BIST_OFFSET 0x15
  69. #define CMOS_CPU_VMX_OFFSET 0x16
  70. #define CMOS_ICH_PORT80_OFFSET 0x17
  71. #define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID.
  72. #define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP.
  73. #define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
  74. #define CMOS_DCU_MODE_OFFSET 0x1B
  75. #define CMOS_VR11_SET_OFFSET 0x1C
  76. #define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!
  77. #define CMOS_RESET_TYPE_BY_OS 0x52
  78. #define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
  79. #define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
  80. #define ACPI_TPM_REQUEST 0x75
  81. #define ACPI_TPM_LAST_REQUEST 0x76
  82. #define CMOS_BOOT_FLAG_ADDRESS 0x7E
  83. //
  84. // GPIO Index Data Structure.
  85. //
  86. typedef struct {
  87. UINT8 Register;
  88. UINT32 Value;
  89. } ICH_GPIO_DEV;
  90. //
  91. // CPU Equates
  92. //
  93. #define MAX_THREAD 2
  94. #define MAX_CORE 1
  95. #define MAX_DIE 2
  96. #define MAX_CPU_SOCKET 1
  97. #define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)
  98. #define MEM64_LEN 0x00100000000
  99. #define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36
  100. #define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36
  101. #define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39
  102. #define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39
  103. #define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40
  104. #define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40
  105. #define PLATFORM_MAX_BUS_NUM 0x3f
  106. #define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d
  107. #define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b
  108. #define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086
  109. #endif