PlatformCpuInfo.h 7.4 KB

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  1. /*++
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformCpuInfo.h
  6. Abstract:
  7. GUID used for Platform CPU Info Data entries in the HOB list.
  8. --*/
  9. #ifndef _PLATFORM_CPU_INFO_GUID_H_
  10. #define _PLATFORM_CPU_INFO_GUID_H_
  11. #include "CpuType.h"
  12. #define EFI_PLATFORM_CPU_INFO_GUID \
  13. {\
  14. 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
  15. }
  16. extern EFI_GUID gEfiPlatformCpuInfoGuid;
  17. extern CHAR16 EfiPlatformCpuInfoVariable[];
  18. //
  19. // Tri-state for feature capabilities and enable/disable.
  20. // [0] clear=feature isn't capable
  21. // [0] set =feature is capable
  22. // [1] clear=feature is disabled
  23. // [1] set =feature is enabled
  24. //
  25. #define CPU_FEATURES_CAPABLE BIT0
  26. #define CPU_FEATURES_ENABLE BIT1
  27. #define MAX_CACHE_DESCRIPTORS 64
  28. #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
  29. #pragma pack(1)
  30. typedef struct {
  31. UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF
  32. UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0
  33. UINT8 ExtendedFamilyId; // [27:20]
  34. UINT8 ExtendedModelId; // [19:16]
  35. UINT8 ProcessorType; // [13:11]
  36. UINT8 FamilyId; // [11:8]
  37. UINT8 Model; // [7:4]
  38. UINT8 SteppingId; // [3:0]
  39. } EFI_CPU_VERSION_INFO; // CPUID.1.EAX
  40. typedef struct {
  41. UINT32 L1InstructionCacheSize;
  42. UINT32 L1DataCacheSize;
  43. UINT32 L2CacheSize;
  44. UINT32 L3CacheSize;
  45. UINT32 TraceCacheSize;
  46. UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];
  47. } EFI_CPU_CACHE_INFO; // CPUID.2.EAX
  48. typedef struct {
  49. UINT8 PhysicalPackages;
  50. UINT8 LogicalProcessorsPerPhysicalPackage;
  51. UINT8 CoresPerPhysicalPackage;
  52. UINT8 ThreadsPerCore;
  53. } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
  54. typedef struct {
  55. UINT32 RegEdx; // CPUID.5.EAX
  56. UINT8 MaxCState;
  57. UINT8 C0SubCStatesMwait; // EDX [3:0]
  58. UINT8 C1SubCStatesMwait; // EDX [7:4]
  59. UINT8 C2SubCStatesMwait; // EDX [11:8]
  60. UINT8 C3SubCStatesMwait; // EDX [15:12]
  61. UINT8 C4SubCStatesMwait; // EDX [19:16]
  62. UINT8 C5SubCStatesMwait; // EDX [23:20]
  63. UINT8 C6SubCStatesMwait; // EDX [27:24]
  64. UINT8 C7SubCStatesMwait; // EDX [31:28]
  65. UINT8 MonitorMwaitSupport; // ECX [0]
  66. UINT8 InterruptsBreakMwait; // ECX [1]
  67. } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
  68. typedef struct {
  69. UINT8 Turbo; // EAX [1]
  70. UINT8 PECI; // EAX [0]
  71. UINT8 NumIntThresholds; // EBX [3:0]
  72. UINT8 HwCoordinationFeedback; // ECX [0]
  73. } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
  74. typedef struct {
  75. UINT32 RegEax;
  76. UINT32 RegEbx;
  77. UINT32 RegEcx;
  78. UINT32 RegEdx;
  79. } EFI_CPUID_REGISTER;
  80. //
  81. // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
  82. // - Keep the respective feature entry variable as default value (0x00)
  83. // if the CPU is not capable for the feature.
  84. // - Use the specially defined programming convention to update the variable
  85. // to indicate capable, enable or disable.
  86. // ie. F_CAPABLE for feature available
  87. // F_ENABLE for feature enable
  88. // F_DISABLE for feature disable
  89. //
  90. typedef struct {
  91. EFI_CPUID_REGISTER Regs; // CPUID.1.EAX
  92. UINT8 Xapic; // ECX [21]
  93. UINT8 SSE4_2; // ECX [20]
  94. UINT8 SSE4_1; // ECX [19]
  95. UINT8 Dca; // ECX [18]
  96. UINT8 SupSSE3; // ECX [9]
  97. UINT8 Tm2; // ECX [8]
  98. UINT8 Eist; // ECX [7]
  99. UINT8 Lt; // ECX [6]
  100. UINT8 Vt; // ECX [5]
  101. UINT8 Mwait; // ECX [3]
  102. UINT8 SSE3; // ECX [0]
  103. UINT8 Tcc; // EDX [29]
  104. UINT8 Mt; // EDX [28]
  105. UINT8 SSE2; // EDX [26]
  106. UINT8 SSE; // EDX [25]
  107. UINT8 MMX; // EDX [23]
  108. EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX
  109. UINT8 ExtLahfSahf64; // ECX [0]
  110. UINT8 ExtIntel64; // EDX [29]
  111. UINT8 ExtXd; // EDX [20]
  112. UINT8 ExtSysCallRet64; // EDX [11]
  113. UINT16 Ht; // CPUID.0B.EAX EBX [15:0]
  114. } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
  115. typedef struct {
  116. UINT8 PhysicalBits;
  117. UINT8 VirtualBits;
  118. } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
  119. typedef struct {
  120. UINT8 PlatformID; // MSR 0x17 [52:50]
  121. UINT32 MicrocodeRevision; // MSR 0x8B [63:32]
  122. UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]
  123. UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]
  124. UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]
  125. UINT8 RatioLimitsTurbo; // MSR 0xCE [28]
  126. UINT8 PreProduction; // MSR 0xCE [27]
  127. UINT8 DcuModeSelect; // MSR 0xCE [26]
  128. UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]
  129. UINT8 Emrr; // MSR 0xFE [12]
  130. UINT8 Smrr; // MSR 0xFE [11]
  131. UINT8 VariableMtrrCount; // MSR 0xFE [7:0]
  132. UINT16 PState; // MSR 0x198 [15:0]
  133. UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]
  134. UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]
  135. UINT32 PCIeBar; // MSR 0x300 [39:20]
  136. UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]
  137. } EFI_MSR_FEATURES;
  138. typedef struct {
  139. BOOLEAN IsIntelProcessor;
  140. UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
  141. UINT32 CpuidMaxInputValue;
  142. UINT32 CpuidMaxExtInputValue;
  143. EFI_CPU_UARCH CpuUarch;
  144. EFI_CPU_FAMILY CpuFamily;
  145. EFI_CPU_PLATFORM CpuPlatform;
  146. EFI_CPU_TYPE CpuType;
  147. EFI_CPU_VERSION_INFO CpuVersion;
  148. EFI_CPU_CACHE_INFO CpuCache;
  149. EFI_CPU_FEATURES CpuFeatures;
  150. EFI_CPU_CSTATE_INFO CpuCState;
  151. EFI_CPU_PACKAGE_INFO CpuPackage;
  152. EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;
  153. EFI_CPU_ADDRESS_BITS CpuAddress;
  154. EFI_MSR_FEATURES Msr;
  155. } EFI_PLATFORM_CPU_INFO;
  156. #pragma pack()
  157. #endif