Initialize.c 10 KB

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  1. /** @file
  2. Graphics Output Protocol functions for the QEMU video controller.
  3. Copyright (c) 2007 - 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "Simics.h"
  7. ///
  8. /// Generic Attribute Controller Register Settings
  9. ///
  10. UINT8 AttributeController[21] = {
  11. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  12. 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
  13. 0x41, 0x00, 0x0F, 0x00, 0x00
  14. };
  15. ///
  16. /// Generic Graphics Controller Register Settings
  17. ///
  18. UINT8 GraphicsController[9] = {
  19. 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF
  20. };
  21. //
  22. // 640 x 480 x 256 color @ 60 Hertz
  23. //
  24. UINT8 Crtc_640_480_256_60[28] = {
  25. 0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,
  26. 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  27. 0xe1, 0x83, 0xdf, 0x50, 0x00, 0xe7, 0x04, 0xe3,
  28. 0xff, 0x00, 0x00, 0x22
  29. };
  30. UINT8 Crtc_640_480_32bpp_60[28] = {
  31. 0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,
  32. 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  33. 0xe1, 0x83, 0xdf, 0x40, 0x00, 0xe7, 0x04, 0xe3,
  34. 0xff, 0x00, 0x00, 0x32
  35. };
  36. UINT16 Seq_640_480_256_60[15] = {
  37. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
  38. 0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e
  39. };
  40. UINT16 Seq_640_480_32bpp_60[15] = {
  41. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
  42. 0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e
  43. };
  44. //
  45. // 800 x 600 x 256 color @ 60 Hertz
  46. //
  47. UINT8 Crtc_800_600_256_60[28] = {
  48. 0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,
  49. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  50. 0x58, 0x8C, 0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,
  51. 0xFF, 0x00, 0x00, 0x22
  52. };
  53. UINT8 Crtc_800_600_32bpp_60[28] = {
  54. 0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,
  55. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  56. 0x58, 0x8C, 0x57, 0x90, 0x00, 0x5F, 0x91, 0xE3,
  57. 0xFF, 0x00, 0x00, 0x32
  58. };
  59. UINT16 Seq_800_600_256_60[15] = {
  60. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
  61. 0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e
  62. };
  63. UINT16 Seq_800_600_32bpp_60[15] = {
  64. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
  65. 0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e
  66. };
  67. UINT8 Crtc_960_720_32bpp_60[28] = {
  68. 0xA3, 0x77, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
  69. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  70. 0x02, 0x88, 0xCF, 0xe0, 0x00, 0x00, 0x64, 0xE3,
  71. 0xFF, 0x4A, 0x00, 0x32
  72. };
  73. UINT16 Seq_960_720_32bpp_60[15] = {
  74. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
  75. 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
  76. };
  77. //
  78. // 1024 x 768 x 256 color @ 60 Hertz
  79. //
  80. UINT8 Crtc_1024_768_256_60[28] = {
  81. 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
  82. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  83. 0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
  84. 0xFF, 0x4A, 0x00, 0x22
  85. };
  86. UINT16 Seq_1024_768_256_60[15] = {
  87. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
  88. 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
  89. };
  90. //
  91. // 1024 x 768 x 24-bit color @ 60 Hertz
  92. //
  93. UINT8 Crtc_1024_768_24bpp_60[28] = {
  94. 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
  95. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  96. 0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
  97. 0xFF, 0x4A, 0x00, 0x32
  98. };
  99. UINT16 Seq_1024_768_24bpp_60[15] = {
  100. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1507, 0x0008, 0x4a0b,
  101. 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
  102. };
  103. UINT8 Crtc_1024_768_32bpp_60[28] = {
  104. 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
  105. 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  106. 0x02, 0x88, 0xFF, 0xe0, 0x00, 0x00, 0x64, 0xE3,
  107. 0xFF, 0x4A, 0x00, 0x32
  108. };
  109. UINT16 Seq_1024_768_32bpp_60[15] = {
  110. 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
  111. 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
  112. };
  113. ///
  114. /// Table of supported video modes
  115. ///
  116. QEMU_VIDEO_CIRRUS_MODES QemuVideoCirrusModes[] = {
  117. // { 640, 480, 8, Crtc_640_480_256_60, Seq_640_480_256_60, 0xe3 },
  118. // { 800, 600, 8, Crtc_800_600_256_60, Seq_800_600_256_60, 0xef },
  119. { 640, 480, 32, Crtc_640_480_32bpp_60, Seq_640_480_32bpp_60, 0xef },
  120. { 800, 600, 32, Crtc_800_600_32bpp_60, Seq_800_600_32bpp_60, 0xef },
  121. // { 1024, 768, 8, Crtc_1024_768_256_60, Seq_1024_768_256_60, 0xef }
  122. { 1024, 768, 24, Crtc_1024_768_24bpp_60, Seq_1024_768_24bpp_60, 0xef }
  123. // { 1024, 768, 32, Crtc_1024_768_32bpp_60, Seq_1024_768_32bpp_60, 0xef }
  124. // { 960, 720, 32, Crtc_960_720_32bpp_60, Seq_1024_768_32bpp_60, 0xef }
  125. };
  126. #define QEMU_VIDEO_CIRRUS_MODE_COUNT \
  127. (ARRAY_SIZE (QemuVideoCirrusModes))
  128. /**
  129. Construct the valid video modes for QemuVideo.
  130. **/
  131. EFI_STATUS
  132. QemuVideoCirrusModeSetup (
  133. QEMU_VIDEO_PRIVATE_DATA *Private
  134. )
  135. {
  136. UINT32 Index;
  137. QEMU_VIDEO_MODE_DATA *ModeData;
  138. QEMU_VIDEO_CIRRUS_MODES *VideoMode;
  139. //
  140. // Setup Video Modes
  141. //
  142. Private->ModeData = AllocatePool (
  143. sizeof (Private->ModeData[0]) * QEMU_VIDEO_CIRRUS_MODE_COUNT
  144. );
  145. if (Private->ModeData == NULL) {
  146. return EFI_OUT_OF_RESOURCES;
  147. }
  148. ModeData = Private->ModeData;
  149. VideoMode = &QemuVideoCirrusModes[0];
  150. for (Index = 0; Index < QEMU_VIDEO_CIRRUS_MODE_COUNT; Index ++) {
  151. ModeData->InternalModeIndex = Index;
  152. ModeData->HorizontalResolution = VideoMode->Width;
  153. ModeData->VerticalResolution = VideoMode->Height;
  154. ModeData->ColorDepth = VideoMode->ColorDepth;
  155. DEBUG ((EFI_D_INFO,
  156. "Adding Mode %d as Cirrus Internal Mode %d: %dx%d, %d-bit\n",
  157. (INT32) (ModeData - Private->ModeData),
  158. ModeData->InternalModeIndex,
  159. ModeData->HorizontalResolution,
  160. ModeData->VerticalResolution,
  161. ModeData->ColorDepth
  162. ));
  163. ModeData ++ ;
  164. VideoMode ++;
  165. }
  166. Private->MaxMode = ModeData - Private->ModeData;
  167. return EFI_SUCCESS;
  168. }
  169. ///
  170. /// Table of supported video modes
  171. ///
  172. QEMU_VIDEO_BOCHS_MODES QemuVideoBochsModes[] = {
  173. { 640, 480, 32 },
  174. { 800, 480, 32 },
  175. { 800, 600, 32 },
  176. { 832, 624, 32 },
  177. { 960, 640, 32 },
  178. { 1024, 600, 32 },
  179. { 1024, 768, 32 },
  180. { 1152, 864, 32 },
  181. { 1152, 870, 32 },
  182. { 1280, 720, 32 },
  183. { 1280, 760, 32 },
  184. { 1280, 768, 32 },
  185. { 1280, 800, 32 },
  186. { 1280, 960, 32 },
  187. { 1280, 1024, 32 },
  188. { 1360, 768, 32 },
  189. { 1366, 768, 32 },
  190. { 1400, 1050, 32 },
  191. { 1440, 900, 32 },
  192. { 1600, 900, 32 },
  193. { 1600, 1200, 32 },
  194. { 1680, 1050, 32 },
  195. { 1920, 1080, 32 },
  196. { 1920, 1200, 32 },
  197. { 1920, 1440, 32 },
  198. { 2000, 2000, 32 },
  199. { 2048, 1536, 32 },
  200. { 2048, 2048, 32 },
  201. { 2560, 1440, 32 },
  202. { 2560, 1600, 32 },
  203. { 2560, 2048, 32 },
  204. { 2800, 2100, 32 },
  205. { 3200, 2400, 32 },
  206. { 3840, 2160, 32 },
  207. { 4096, 2160, 32 },
  208. { 7680, 4320, 32 },
  209. { 8192, 4320, 32 }
  210. };
  211. #define QEMU_VIDEO_BOCHS_MODE_COUNT \
  212. (ARRAY_SIZE (QemuVideoBochsModes))
  213. EFI_STATUS
  214. QemuVideoBochsModeSetup (
  215. QEMU_VIDEO_PRIVATE_DATA *Private,
  216. BOOLEAN IsQxl
  217. )
  218. {
  219. UINT32 AvailableFbSize;
  220. UINT32 Index;
  221. QEMU_VIDEO_MODE_DATA *ModeData;
  222. QEMU_VIDEO_BOCHS_MODES *VideoMode;
  223. //
  224. // Fetch the available framebuffer size.
  225. //
  226. // VBE_DISPI_INDEX_VIDEO_MEMORY_64K is expected to return the size of the
  227. // drawable framebuffer. Up to and including qemu-2.1 however it used to
  228. // return the size of PCI BAR 0 (ie. the full video RAM size).
  229. //
  230. // On stdvga the two concepts coincide with each other; the full memory size
  231. // is usable for drawing.
  232. //
  233. // On QXL however, only a leading segment, "surface 0", can be used for
  234. // drawing; the rest of the video memory is used for the QXL guest-host
  235. // protocol. VBE_DISPI_INDEX_VIDEO_MEMORY_64K should report the size of
  236. // "surface 0", but since it doesn't (up to and including qemu-2.1), we
  237. // retrieve the size of the drawable portion from a field in the QXL ROM BAR,
  238. // where it is also available.
  239. //
  240. if (IsQxl) {
  241. UINT32 Signature;
  242. UINT32 DrawStart;
  243. Signature = 0;
  244. DrawStart = 0xFFFFFFFF;
  245. AvailableFbSize = 0;
  246. if (EFI_ERROR (
  247. Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
  248. PCI_BAR_IDX2, 0, 1, &Signature)) ||
  249. Signature != SIGNATURE_32 ('Q', 'X', 'R', 'O') ||
  250. EFI_ERROR (
  251. Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
  252. PCI_BAR_IDX2, 36, 1, &DrawStart)) ||
  253. DrawStart != 0 ||
  254. EFI_ERROR (
  255. Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
  256. PCI_BAR_IDX2, 40, 1, &AvailableFbSize))) {
  257. DEBUG ((EFI_D_ERROR, "%a: can't read size of drawable buffer from QXL "
  258. "ROM\n", __FUNCTION__));
  259. return EFI_NOT_FOUND;
  260. }
  261. } else {
  262. AvailableFbSize = BochsRead (Private, VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
  263. AvailableFbSize *= SIZE_64KB;
  264. }
  265. DEBUG ((EFI_D_INFO, "%a: AvailableFbSize=0x%x\n", __FUNCTION__,
  266. AvailableFbSize));
  267. //
  268. // Setup Video Modes
  269. //
  270. Private->ModeData = AllocatePool (
  271. sizeof (Private->ModeData[0]) * QEMU_VIDEO_BOCHS_MODE_COUNT
  272. );
  273. if (Private->ModeData == NULL) {
  274. return EFI_OUT_OF_RESOURCES;
  275. }
  276. ModeData = Private->ModeData;
  277. VideoMode = &QemuVideoBochsModes[0];
  278. for (Index = 0; Index < QEMU_VIDEO_BOCHS_MODE_COUNT; Index ++) {
  279. UINTN RequiredFbSize;
  280. ASSERT (VideoMode->ColorDepth % 8 == 0);
  281. RequiredFbSize = (UINTN) VideoMode->Width * VideoMode->Height *
  282. (VideoMode->ColorDepth / 8);
  283. if (RequiredFbSize <= AvailableFbSize) {
  284. ModeData->InternalModeIndex = Index;
  285. ModeData->HorizontalResolution = VideoMode->Width;
  286. ModeData->VerticalResolution = VideoMode->Height;
  287. ModeData->ColorDepth = VideoMode->ColorDepth;
  288. DEBUG ((EFI_D_INFO,
  289. "Adding Mode %d as Bochs Internal Mode %d: %dx%d, %d-bit\n",
  290. (INT32) (ModeData - Private->ModeData),
  291. ModeData->InternalModeIndex,
  292. ModeData->HorizontalResolution,
  293. ModeData->VerticalResolution,
  294. ModeData->ColorDepth
  295. ));
  296. ModeData ++ ;
  297. }
  298. VideoMode ++;
  299. }
  300. Private->MaxMode = ModeData - Private->ModeData;
  301. return EFI_SUCCESS;
  302. }