PlatformBoards.h 7.9 KB

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  1. /** @file
  2. Board config definitions for each of the boards supported by this platform
  3. package.
  4. Copyright (c) 2013 Intel Corporation.
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include "Platform.h"
  8. #ifndef __PLATFORM_BOARDS_H__
  9. #define __PLATFORM_BOARDS_H__
  10. //
  11. // Constant definition
  12. //
  13. //
  14. // Default resume well TPM reset.
  15. //
  16. #define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5
  17. //
  18. // Basic Configs for GPIO table definitions.
  19. //
  20. #define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
  21. #define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}
  22. #define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER
  23. #define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}
  24. #define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}
  25. #define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}
  26. #define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}
  27. #define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}
  28. #define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}
  29. #define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}
  30. #define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
  31. #define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
  32. #define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
  33. #define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}
  34. #define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}
  35. #define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}
  36. #define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}
  37. #define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}
  38. //
  39. // Legacy Gpio to be used to assert / deassert PCI express PERST# signal
  40. // on Galileo Gen 2 platform.
  41. //
  42. #define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0
  43. //
  44. // Io expander slave address.
  45. //
  46. //
  47. // On Galileo value of Jumper J2 determines slave address of io expander.
  48. //
  49. #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
  50. #define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20
  51. #define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21
  52. //
  53. // Three IO Expmanders at fixed addresses on Galileo Gen2.
  54. //
  55. #define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25
  56. #define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26
  57. #define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27
  58. //
  59. // Led GPIOs for flash update / recovery.
  60. //
  61. #define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1
  62. #define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5
  63. //
  64. // Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.
  65. //
  66. typedef struct {
  67. UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.
  68. UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.
  69. UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.
  70. UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.
  71. UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.
  72. UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.
  73. UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.
  74. UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.
  75. UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.
  76. UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.
  77. UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.
  78. UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.
  79. UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.
  80. UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.
  81. UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.
  82. UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.
  83. UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.
  84. UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.
  85. } BOARD_LEGACY_GPIO_CONFIG;
  86. //
  87. // GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.
  88. //
  89. typedef struct {
  90. UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.
  91. UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.
  92. UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN.
  93. UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK.
  94. UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.
  95. UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.
  96. UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.
  97. UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC.
  98. } BOARD_GPIO_CONTROLLER_CONFIG;
  99. ///
  100. /// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported
  101. /// by this platform package.
  102. /// Table indexed with EFI_PLATFORM_TYPE enum value.
  103. ///
  104. #define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \
  105. /* EFI_PLATFORM_TYPE - TypeUnknown*/\
  106. NULL_LEGACY_GPIO_INITIALIZER,\
  107. /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
  108. QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\
  109. /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
  110. CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\
  111. /* EFI_PLATFORM_TYPE - KipsBay*/\
  112. KIPS_BAY_LEGACY_GPIO_INITIALIZER,\
  113. /* EFI_PLATFORM_TYPE - CrossHill*/\
  114. CROSS_HILL_LEGACY_GPIO_INITIALIZER,\
  115. /* EFI_PLATFORM_TYPE - ClantonHill*/\
  116. CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\
  117. /* EFI_PLATFORM_TYPE - Galileo*/\
  118. GALILEO_LEGACY_GPIO_INITIALIZER,\
  119. /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\
  120. NULL_LEGACY_GPIO_INITIALIZER,\
  121. /* EFI_PLATFORM_TYPE - GalileoGen2*/\
  122. GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\
  123. ///
  124. /// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board
  125. /// supported by this platform package.
  126. /// Table indexed with EFI_PLATFORM_TYPE enum value.
  127. ///
  128. #define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \
  129. /* EFI_PLATFORM_TYPE - TypeUnknown*/\
  130. NULL_GPIO_CONTROLLER_INITIALIZER,\
  131. /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
  132. QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\
  133. /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
  134. CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\
  135. /* EFI_PLATFORM_TYPE - KipsBay*/\
  136. KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\
  137. /* EFI_PLATFORM_TYPE - CrossHill*/\
  138. CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\
  139. /* EFI_PLATFORM_TYPE - ClantonHill*/\
  140. CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\
  141. /* EFI_PLATFORM_TYPE - Galileo*/\
  142. GALILEO_GPIO_CONTROLLER_INITIALIZER,\
  143. /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\
  144. NULL_GPIO_CONTROLLER_INITIALIZER,\
  145. /* EFI_PLATFORM_TYPE - GalileoGen2*/\
  146. GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\
  147. #endif