Platform.h 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119
  1. /** @file
  2. Quark platform specific information.
  3. Copyright (c) 2013 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "Uefi.h"
  7. #ifndef __PLATFORM_H__
  8. #define __PLATFORM_H__
  9. //
  10. // Constant definition
  11. //
  12. #define MAX_SMRAM_RANGES 4
  13. #define MAX_NODE 1
  14. #define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0
  15. #define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F.
  16. #define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F.
  17. #define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map.
  18. #define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB.
  19. #define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address.
  20. #define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM.
  21. //
  22. // Gpio to be used to assert / deassert PCI express PERST# signal.
  23. //
  24. #define PCIEXP_PERST_RESUMEWELL_GPIO 3
  25. //
  26. // Minimum time in microseconds for assertion of PERST# signal.
  27. //
  28. #define PCIEXP_PERST_MIN_ASSERT_US 100
  29. //
  30. // Microsecond delay post issueing common lane reset.
  31. //
  32. #define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1
  33. //
  34. // Microsecond delay to wait for PLL to lock.
  35. //
  36. #define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80
  37. //
  38. // Microsecond delay post issueing sideband interface reset.
  39. //
  40. #define PCIEXP_DELAY_US_POST_SBI_RESET 20
  41. //
  42. // Microsecond delay post deasserting PERST#.
  43. //
  44. #define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10
  45. //
  46. // Catastrophic Trip point in degrees Celsius for this platform.
  47. //
  48. #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
  49. //
  50. // Platform flash update LED common definitions.
  51. //
  52. #define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7
  53. #define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.
  54. //
  55. // This structure stores the base and size of the ACPI reserved memory used when
  56. // resuming from S3. This region must be allocated by the platform code.
  57. //
  58. typedef struct {
  59. UINT32 AcpiReservedMemoryBase;
  60. UINT32 AcpiReservedMemorySize;
  61. UINT32 SystemMemoryLength;
  62. } RESERVED_ACPI_S3_RANGE;
  63. #define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))
  64. //
  65. // Define valid platform types.
  66. // First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition
  67. // and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.
  68. // Value shown for supported platforms to help sanity checking with build tools
  69. // and ACPI method usage.
  70. //
  71. typedef enum {
  72. TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!
  73. QuarkEmulation = 1,
  74. ClantonPeakSVP = 2,
  75. KipsBay = 3,
  76. CrossHill = 4,
  77. ClantonHill = 5,
  78. Galileo = 6,
  79. TypePlatformRsv7 = 7,
  80. GalileoGen2 = 8,
  81. TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!
  82. } EFI_PLATFORM_TYPE;
  83. #define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \
  84. L"TypeUnknown",\
  85. L"QuarkEmulation",\
  86. L"ClantonPeakSVP",\
  87. L"KipsBay",\
  88. L"CrossHill",\
  89. L"ClantonHill",\
  90. L"Galileo",\
  91. L"TypePlatformRsv7",\
  92. L"GalileoGen2",\
  93. typedef struct {
  94. UINT32 EntryOffset;
  95. UINT8 ImageIndex;
  96. } QUARK_EDKII_STAGE1_HEADER;
  97. #endif