Platform.h 2.7 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include "Uefi.h"
  6. #include "Guid/SetupVariable.h"
  7. #include "UncoreCommonIncludes.h"
  8. #include <Library/PcdLib.h>
  9. #ifndef __PLATFORM_H__
  10. #define __PLATFORM_H__
  11. //
  12. // Assigning default ID and base addresses here, these definitions are used by ACPI tables
  13. //
  14. #define PCH_INTERRUPT_BASE 0
  15. #if MAX_SOCKET > 4
  16. #define PCH_IOAPIC 0
  17. #else
  18. #define PCH_IOAPIC (1 << 0)
  19. #endif
  20. //
  21. // This structure stores the base and size of the ACPI reserved memory used when
  22. // resuming from S3. This region must be allocated by the platform code.
  23. //
  24. typedef struct {
  25. UINT32 AcpiReservedMemoryBase;
  26. UINT32 AcpiReservedMemorySize;
  27. UINT32 SystemMemoryLength;
  28. } RESERVED_ACPI_S3_RANGE;
  29. #define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))
  30. //
  31. // SMBUS Data
  32. //
  33. #define PCH_SMBUS_BASE_ADDRESS 0x0780
  34. //
  35. // CMOS usage
  36. //
  37. #define CMOS_WARM_RESET_COUNTER_OFFSET 0xBD // 1 byte CMOS Space for passing warm reset counter to Dxe
  38. // due to reset in MRC Dxe always thinks that warm reset occurs
  39. // counter > 1 -> means WarmReset
  40. //
  41. // ACPI and legacy I/O register offsets from PMBASE
  42. //
  43. #define R_ACPI_PM1_STS 0x00
  44. #define R_ACPI_PM1_EN 0x02
  45. #define R_ACPI_PM1_CNT 0x04
  46. #define R_ACPI_PM1_TMR 0x08
  47. #define R_ACPI_PROC_CNT 0x10
  48. #define R_ACPI_PM2_CNT 0x50
  49. #define R_ACPI_GPE0_STS 0x20
  50. #define R_ACPI_GPE0_EN 0x28
  51. #define R_ACPI_SMI_EN 0x30
  52. #define R_ACPI_SMI_STS 0x34
  53. #define R_ACPI_ALT_GP_SMI_EN 0x38
  54. #define R_ACPI_ALT_GP_SMI_STS 0x3A
  55. #define R_ACPI_LV2 0x14
  56. #define R_IOPORT_CMOS_STANDARD_INDEX 0x70
  57. #define R_IOPORT_CMOS_STANDARD_DATA 0x71
  58. #define R_IOPORT_CMOS_UPPER_INDEX 0x72
  59. #define R_IOPORT_CMOS_UPPER_DATA 0x73
  60. #define R_IOPORT_CMOS_IDX_DIAGNOSTIC_STATUS 0x0E
  61. //
  62. // Misc PCI register offsets and sizes
  63. //
  64. #define R_EFI_PCI_SVID 0x2C
  65. #define V_EFI_PCI_SVID_SIZE 0x2
  66. #define R_EFI_PCI_SID 0x2E
  67. #define V_EFI_PCI_SID_SIZE 0x2
  68. //
  69. // Need min. of 24 MB PEI phase
  70. //
  71. #define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000))
  72. #endif