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- /** @file
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
- **/
- //
- // BIOS parameter BIOS_ACPI_PARAM
- //
- OperationRegion (PSYS, SystemMemory, 0x30584946, 0x400) // (FIX0 - Patched by ACPI Platform Driver during POST)
- Field (PSYS, ByteAcc, NoLock, Preserve) {
- // IOAPIC Start
- PLAT , 32, // Platform ID
- Offset (0x04), //
- #if MAX_SOCKET > 4
- AP00 , 1, // PC00 IOAPIC Enable
- AP01 , 1, // PC01 IOAPIC Enable
- AP02 , 1, // PC02 IOAPIC Enable
- AP03 , 1, // PC03 IOAPIC Enable
- AP04 , 1, // PC04 IOAPIC Enable
- AP05 , 1, // PC05 IOAPIC Enable
- AP06 , 1, // PC06 IOAPIC Enable
- AP07 , 1, // PC07 IOAPIC Enable
- AP08 , 1, // PC08 IOAPIC Enable
- AP09 , 1, // PC09 IOAPIC Enable
- AP10 , 1, // PC10 IOAPIC Enable
- AP11 , 1, // PC11 IOAPIC Enable
- AP12 , 1, // PC12 IOAPIC Enable
- AP13 , 1, // PC13 IOAPIC Enable
- AP14 , 1, // PC14 IOAPIC Enable
- AP15 , 1, // PC15 IOAPIC Enable
- AP16 , 1, // PC16 IOAPIC Enable
- AP17 , 1, // PC17 IOAPIC Enable
- AP18 , 1, // PC18 IOAPIC Enable
- AP19 , 1, // PC19 IOAPIC Enable
- AP20 , 1, // PC20 IOAPIC Enable
- AP21 , 1, // PC21 IOAPIC Enable
- AP22 , 1, // PC22 IOAPIC Enable
- AP23 , 1, // PC23 IOAPIC Enable
- AP24 , 1, // PC24 IOAPIC Enable
- AP25 , 1, // 8S PC25 IOAPIC Enable
- AP26 , 1, // 8S PC26 IOAPIC Enable
- AP27 , 1, // 8S PC27 IOAPIC Enable
- AP28 , 1, // 8S PC28 IOAPIC Enable
- AP29 , 1, // 8S PC29 IOAPIC Enable
- AP30 , 1, // 8S PC30 IOAPIC Enable
- AP31 , 1, // 8S PC31 IOAPIC Enable
- #else
- APC0 , 1, // PCH IOAPIC Enable
- AP00 , 1, // PC00 IOAPIC Enable
- AP01 , 1, // PC01 IOAPIC Enable
- AP02 , 1, // PC02 IOAPIC Enable
- AP03 , 1, // PC03 IOAPIC Enable
- AP04 , 1, // PC04 IOAPIC Enable
- AP05 , 1, // PC05 IOAPIC Enable
- AP06 , 1, // PC06 IOAPIC Enable
- AP07 , 1, // PC07 IOAPIC Enable
- AP08 , 1, // PC08 IOAPIC Enable
- AP09 , 1, // PC09 IOAPIC Enable
- AP10 , 1, // PC10 IOAPIC Enable
- AP11 , 1, // PC11 IOAPIC Enable
- AP12 , 1, // PC12 IOAPIC Enable
- AP13 , 1, // PC13 IOAPIC Enable
- AP14 , 1, // PC14 IOAPIC Enable
- AP15 , 1, // PC15 IOAPIC Enable
- AP16 , 1, // PC16 IOAPIC Enable
- AP17 , 1, // PC17 IOAPIC Enable
- AP18 , 1, // PC18 IOAPIC Enable
- AP19 , 1, // PC19 IOAPIC Enable
- AP20 , 1, // PC20 IOAPIC Enable
- AP21 , 1, // PC21 IOAPIC Enable
- AP22 , 1, // PC22 IOAPIC Enable
- AP23 , 1, // PC23 IOAPIC Enable
- RESA , 7, // Unused
- #endif
- Offset (0x08),
- SKOV , 1, // Override ApicId socket field
- , 7, // Unused
- // IOAPIC End
- // Power Managment Start
- Offset (0x09),
- , 1, //
- CSEN , 1, // C State Enable
- C3EN , 1, // OS C3 Report Enbale
- C6EN , 1, // C6 Enable
- C7EN , 1, // C7 Enable
- MWOS , 1, // MWAIT support Enable
- PSEN , 1, // P State Enable
- EMCA , 1, // EMCA Enable
- Offset (0x0A),
- HWAL , 2, // PSD HW_ALL Enable
- KPRS , 1, // KB present Flag
- MPRS , 1, // Mouse present Flag
- TSEN , 1, // T State Enable Flag
- FGTS , 1, // Fine grained T state Flag
- OSCX , 1, // OS C States
- RESX , 1, // Unused
- // Power Management End
- // RAS Start
- Offset (0x0B),
- CPHP , 8, // Bit field for determining CPU hotplug event is happening, Update every time CPU Hotpug event is registered as valid
- // Bit0 CPU0 O*L Request
- // Bit1 CPU1 O*L Request
- // Bit2 CPU2 O*L Request
- // Bit3 CPU3 O*L Request
- // Bit4-7 Reserved
- IIOP , 8, // Bit field for determining IIO hotplug event is happening, Update every time IIO Hotpug event is registered as valid
- // Bit0 IIO1 O*L Request
- // Bit1 IIO2 O*L Request
- // Bit2 IIO3 O*L Request
- // Bit3-7 Reserved
- IIOH , 64, // IIO bit Mask, what IIOs are present for STA method, Update every time IIO hotplug event happens and at boot time (Patched by ACPI Platform Driver during POST)
- PRBM , 32, // Processor Bit mask, what sockets are present for STA method, Update every time hotplug event happen and at boot time (Patched by ACPI Platform Driver during POST)
- P0ID , 32, // Processor 0 APIC ID base
- P1ID , 32, // Processor 1 APIC ID base
- P2ID , 32, // Processor 2 APIC ID base
- P3ID , 32, // Processor 3 APIC ID base
- P4ID , 32, // Processor 4 APIC ID base
- P5ID , 32, // Processor 5 APIC ID base
- P6ID , 32, // Processor 6 APIC ID base
- P7ID , 32, // Processor 7 APIC ID base
- P0BM , 64, // Processor 0 Bit mask, what cores are present for STA method
- P1BM , 64, // Processor 1 Bit mask, what cores are present for STA method
- P2BM , 64, // Processor 2 Bit mask, what cores are present for STA method
- P3BM , 64, // Processor 3 Bit mask, what cores are present for STA method
- P4BM , 64, // Processor 4 Bit mask, what cores are present for STA method
- P5BM , 64, // Processor 5 Bit mask, what cores are present for STA method
- P6BM , 64, // Processor 6 Bit mask, what cores are present for STA method
- P7BM , 64, // Processor 7 Bit mask, what cores are present for STA method
- MEBM , 16, // Memory controller bit mask what memory controllers are present, for STA Method
- MEBC , 16, // Memory controller change event mask what memory controllers have been changed, for notify
- CFMM , 32, // MMCFG Base
- TSSZ , 32, // TSEG Size.
- M0BS , 64, // Memory Controller Base 0
- M1BS , 64, // Memory Controller Base 1
- M2BS , 64, // Memory Controller Base 2
- M3BS , 64, // Memory Controller Base 3
- M4BS , 64, // Memory Controller Base 4
- M5BS , 64, // Memory Controller Base 5
- M6BS , 64, // Memory Controller Base 6
- M7BS , 64, // Memory Controller Base 7
- M0RN , 64, // Memory Controller Range 0
- M1RN , 64, // Memory Controller Range 1
- M2RN , 64, // Memory Controller Range 2
- M3RN , 64, // Memory Controller Range 3
- M4RN , 64, // Memory Controller Range 4
- M5RN , 64, // Memory Controller Range 5
- M6RN , 64, // Memory Controller Range 6
- M7RN , 64, // Memory Controller Range 7
- SMI0 , 32, // Parameter0 used for faked SMI request
- SMI1 , 32, // Parameter1 used for faked SMI request
- SMI2 , 32, // Parameter2 used for faked SMI request
- SMI3 , 32, // Parameter3 used for faked SMI request
- SCI0 , 32, // Parameter0 used for faked SCI request
- SCI1 , 32, // Parameter1 used for faked SCI request
- SCI2 , 32, // Parameter2 used for faked SCI request
- SCI3 , 32, // Parameter3 used for faked SCI request
- MADD , 64, // Migration ActionRegion GAS address. (Migration support written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 are invalid.)
- CUU0 , 128, // CPU0 UUID
- CUU1 , 128, // CPU1 UUID
- CUU2 , 128, // CPU2 UUID
- CUU3 , 128, // CPU3 UUID
- CUU4 , 128, // CPU4 UUID
- CUU5 , 128, // CPU5 UUID
- CUU6 , 128, // CPU6 UUID
- CUU7 , 128, // CPU7 UUID
- CPSP , 8, // CPU spare bitmap. 1 == IsSpare.
- ME00 , 128, // MEM0 UUID
- ME01 , 128, // MEM1 UUID
- ME10 , 128, // MEM2 UUID
- ME11 , 128, // MEM3 UUID
- ME20 , 128, // MEM4 UUID
- ME21 , 128, // MEM5 UUID
- ME30 , 128, // MEM6 UUID
- ME31 , 128, // MEM7 UUID
- ME40 , 128, // MEM8 UUID
- ME41 , 128, // MEM9 UUID
- ME50 , 128, // MEM10 UUID
- ME51 , 128, // MEM11 UUID
- ME60 , 128, // MEM12 UUID
- ME61 , 128, // MEM13 UUID
- ME70 , 128, // MEM14 UUID
- ME71 , 128, // MEM15 UUID
- MESP , 16, // Memory module spare bitmap. 1 == IsSpare.
- LDIR , 64, // L1 Directory Address
- PRID , 32, // Processor ID
- AHPE , 8, // ACPI PCIe hot plug enable.
- // RAS End
- // VTD Start
- DHRD , 192, // DHRD
- ATSR , 192, // ATSR
- RHSA , 192, // RHSA
- // VTD End
- // BIOS Guard Start
- CNBS , 8, // CPU SKU number bit shift
- // BIOS Guard End
- // USB3 Start
- XHMD , 8, // copy of setup item PchUsb30Mode
- SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1)
- SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2)
- // USB3 End
- // HWPM Start
- , 2, // HWPM State Enable option from setup
- , 1, // Aunomous C-state Enable option from setup
- HWPI , 1, // HWP Interrupt
- , 4, // Reserved bits
- // HWPM End
- // PCIe Multi-Seg Start
- BB00 , 8, // Bus Base for PC00
- BB01 , 8, // Bus Base for PC01
- BB02 , 8, // Bus Base for PC02
- BB03 , 8, // Bus Base for PC03
- BB04 , 8, // Bus Base for PC04
- BB05 , 8, // Bus Base for PC05
- BB06 , 8, // Bus Base for PC06
- BB07 , 8, // Bus Base for PC07
- BB08 , 8, // Bus Base for PC08
- BB09 , 8, // Bus Base for PC09
- BB10 , 8, // Bus Base for PC10
- BB11 , 8, // Bus Base for PC11
- BB12 , 8, // Bus Base for PC12
- BB13 , 8, // Bus Base for PC13
- BB14 , 8, // Bus Base for PC14
- BB15 , 8, // Bus Base for PC15
- BB16 , 8, // Bus Base for PC16
- BB17 , 8, // Bus Base for PC17
- BB18 , 8, // Bus Base for PC18
- BB19 , 8, // Bus Base for PC19
- BB20 , 8, // Bus Base for PC20
- BB21 , 8, // Bus Base for PC21
- BB22 , 8, // Bus Base for PC22
- BB23 , 8, // Bus Base for PC23
- BB24 , 8, // Bus Base for PC24
- BB25 , 8, // Bus Base for PC25
- BB26 , 8, // Bus Base for PC26
- BB27 , 8, // Bus Base for PC27
- BB28 , 8, // Bus Base for PC28
- BB29 , 8, // Bus Base for PC29
- BB30 , 8, // Bus Base for PC30
- BB31 , 8, // Bus Base for PC31
- BB32 , 8, // Bus Base for PC32
- BB33 , 8, // Bus Base for PC33
- BB34 , 8, // Bus Base for PC34
- BB35 , 8, // Bus Base for PC35
- BB36 , 8, // Bus Base for PC36
- BB37 , 8, // Bus Base for PC37
- BB38 , 8, // Bus Base for PC38
- BB39 , 8, // Bus Base for PC39
- BB40 , 8, // Bus Base for PC40
- BB41 , 8, // Bus Base for PC41
- BB42 , 8, // Bus Base for PC42
- BB43 , 8, // Bus Base for PC43
- BB44 , 8, // Bus Base for PC44
- BB45 , 8, // Bus Base for PC45
- BB46 , 8, // Bus Base for PC46
- BB47 , 8, // Bus Base for PC47
- SGEN , 8, // PCIe_MultiSeg_Support enable/disable
- SG00 , 8, // Segment ID for Segment Group 0
- SG01 , 8, // Segment ID for Segment Group 1
- SG02 , 8, // Segment ID for Segment Group 2
- SG03 , 8, // Segment ID for Segment Group 3
- SG04 , 8, // Segment ID for Segment Group 4
- SG05 , 8, // Segment ID for Segment Group 5
- SG06 , 8, // Segment ID for Segment Group 6
- SG07 , 8, // Segment ID for Segment Group 7
- // PCIe Multi-Seg End
- // Performance start
- CLOD , 8, // SncAnd2Cluster, i.e. 1=SNC enable and 2 Clusters, 0 otherwise
- // Performance End
-
- }
-
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