GlobalNvs.asi 12 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. //
  6. // BIOS parameter BIOS_ACPI_PARAM
  7. //
  8. OperationRegion (PSYS, SystemMemory, 0x30584946, 0x400) // (FIX0 - Patched by ACPI Platform Driver during POST)
  9. Field (PSYS, ByteAcc, NoLock, Preserve) {
  10. // IOAPIC Start
  11. PLAT , 32, // Platform ID
  12. Offset (0x04), //
  13. #if MAX_SOCKET > 4
  14. AP00 , 1, // PC00 IOAPIC Enable
  15. AP01 , 1, // PC01 IOAPIC Enable
  16. AP02 , 1, // PC02 IOAPIC Enable
  17. AP03 , 1, // PC03 IOAPIC Enable
  18. AP04 , 1, // PC04 IOAPIC Enable
  19. AP05 , 1, // PC05 IOAPIC Enable
  20. AP06 , 1, // PC06 IOAPIC Enable
  21. AP07 , 1, // PC07 IOAPIC Enable
  22. AP08 , 1, // PC08 IOAPIC Enable
  23. AP09 , 1, // PC09 IOAPIC Enable
  24. AP10 , 1, // PC10 IOAPIC Enable
  25. AP11 , 1, // PC11 IOAPIC Enable
  26. AP12 , 1, // PC12 IOAPIC Enable
  27. AP13 , 1, // PC13 IOAPIC Enable
  28. AP14 , 1, // PC14 IOAPIC Enable
  29. AP15 , 1, // PC15 IOAPIC Enable
  30. AP16 , 1, // PC16 IOAPIC Enable
  31. AP17 , 1, // PC17 IOAPIC Enable
  32. AP18 , 1, // PC18 IOAPIC Enable
  33. AP19 , 1, // PC19 IOAPIC Enable
  34. AP20 , 1, // PC20 IOAPIC Enable
  35. AP21 , 1, // PC21 IOAPIC Enable
  36. AP22 , 1, // PC22 IOAPIC Enable
  37. AP23 , 1, // PC23 IOAPIC Enable
  38. AP24 , 1, // PC24 IOAPIC Enable
  39. AP25 , 1, // 8S PC25 IOAPIC Enable
  40. AP26 , 1, // 8S PC26 IOAPIC Enable
  41. AP27 , 1, // 8S PC27 IOAPIC Enable
  42. AP28 , 1, // 8S PC28 IOAPIC Enable
  43. AP29 , 1, // 8S PC29 IOAPIC Enable
  44. AP30 , 1, // 8S PC30 IOAPIC Enable
  45. AP31 , 1, // 8S PC31 IOAPIC Enable
  46. #else
  47. APC0 , 1, // PCH IOAPIC Enable
  48. AP00 , 1, // PC00 IOAPIC Enable
  49. AP01 , 1, // PC01 IOAPIC Enable
  50. AP02 , 1, // PC02 IOAPIC Enable
  51. AP03 , 1, // PC03 IOAPIC Enable
  52. AP04 , 1, // PC04 IOAPIC Enable
  53. AP05 , 1, // PC05 IOAPIC Enable
  54. AP06 , 1, // PC06 IOAPIC Enable
  55. AP07 , 1, // PC07 IOAPIC Enable
  56. AP08 , 1, // PC08 IOAPIC Enable
  57. AP09 , 1, // PC09 IOAPIC Enable
  58. AP10 , 1, // PC10 IOAPIC Enable
  59. AP11 , 1, // PC11 IOAPIC Enable
  60. AP12 , 1, // PC12 IOAPIC Enable
  61. AP13 , 1, // PC13 IOAPIC Enable
  62. AP14 , 1, // PC14 IOAPIC Enable
  63. AP15 , 1, // PC15 IOAPIC Enable
  64. AP16 , 1, // PC16 IOAPIC Enable
  65. AP17 , 1, // PC17 IOAPIC Enable
  66. AP18 , 1, // PC18 IOAPIC Enable
  67. AP19 , 1, // PC19 IOAPIC Enable
  68. AP20 , 1, // PC20 IOAPIC Enable
  69. AP21 , 1, // PC21 IOAPIC Enable
  70. AP22 , 1, // PC22 IOAPIC Enable
  71. AP23 , 1, // PC23 IOAPIC Enable
  72. RESA , 7, // Unused
  73. #endif
  74. Offset (0x08),
  75. SKOV , 1, // Override ApicId socket field
  76. , 7, // Unused
  77. // IOAPIC End
  78. // Power Managment Start
  79. Offset (0x09),
  80. , 1, //
  81. CSEN , 1, // C State Enable
  82. C3EN , 1, // OS C3 Report Enbale
  83. C6EN , 1, // C6 Enable
  84. C7EN , 1, // C7 Enable
  85. MWOS , 1, // MWAIT support Enable
  86. PSEN , 1, // P State Enable
  87. EMCA , 1, // EMCA Enable
  88. Offset (0x0A),
  89. HWAL , 2, // PSD HW_ALL Enable
  90. KPRS , 1, // KB present Flag
  91. MPRS , 1, // Mouse present Flag
  92. TSEN , 1, // T State Enable Flag
  93. FGTS , 1, // Fine grained T state Flag
  94. OSCX , 1, // OS C States
  95. RESX , 1, // Unused
  96. // Power Management End
  97. // RAS Start
  98. Offset (0x0B),
  99. CPHP , 8, // Bit field for determining CPU hotplug event is happening, Update every time CPU Hotpug event is registered as valid
  100. // Bit0 CPU0 O*L Request
  101. // Bit1 CPU1 O*L Request
  102. // Bit2 CPU2 O*L Request
  103. // Bit3 CPU3 O*L Request
  104. // Bit4-7 Reserved
  105. IIOP , 8, // Bit field for determining IIO hotplug event is happening, Update every time IIO Hotpug event is registered as valid
  106. // Bit0 IIO1 O*L Request
  107. // Bit1 IIO2 O*L Request
  108. // Bit2 IIO3 O*L Request
  109. // Bit3-7 Reserved
  110. IIOH , 64, // IIO bit Mask, what IIOs are present for STA method, Update every time IIO hotplug event happens and at boot time (Patched by ACPI Platform Driver during POST)
  111. PRBM , 32, // Processor Bit mask, what sockets are present for STA method, Update every time hotplug event happen and at boot time (Patched by ACPI Platform Driver during POST)
  112. P0ID , 32, // Processor 0 APIC ID base
  113. P1ID , 32, // Processor 1 APIC ID base
  114. P2ID , 32, // Processor 2 APIC ID base
  115. P3ID , 32, // Processor 3 APIC ID base
  116. P4ID , 32, // Processor 4 APIC ID base
  117. P5ID , 32, // Processor 5 APIC ID base
  118. P6ID , 32, // Processor 6 APIC ID base
  119. P7ID , 32, // Processor 7 APIC ID base
  120. P0BM , 64, // Processor 0 Bit mask, what cores are present for STA method
  121. P1BM , 64, // Processor 1 Bit mask, what cores are present for STA method
  122. P2BM , 64, // Processor 2 Bit mask, what cores are present for STA method
  123. P3BM , 64, // Processor 3 Bit mask, what cores are present for STA method
  124. P4BM , 64, // Processor 4 Bit mask, what cores are present for STA method
  125. P5BM , 64, // Processor 5 Bit mask, what cores are present for STA method
  126. P6BM , 64, // Processor 6 Bit mask, what cores are present for STA method
  127. P7BM , 64, // Processor 7 Bit mask, what cores are present for STA method
  128. MEBM , 16, // Memory controller bit mask what memory controllers are present, for STA Method
  129. MEBC , 16, // Memory controller change event mask what memory controllers have been changed, for notify
  130. CFMM , 32, // MMCFG Base
  131. TSSZ , 32, // TSEG Size.
  132. M0BS , 64, // Memory Controller Base 0
  133. M1BS , 64, // Memory Controller Base 1
  134. M2BS , 64, // Memory Controller Base 2
  135. M3BS , 64, // Memory Controller Base 3
  136. M4BS , 64, // Memory Controller Base 4
  137. M5BS , 64, // Memory Controller Base 5
  138. M6BS , 64, // Memory Controller Base 6
  139. M7BS , 64, // Memory Controller Base 7
  140. M0RN , 64, // Memory Controller Range 0
  141. M1RN , 64, // Memory Controller Range 1
  142. M2RN , 64, // Memory Controller Range 2
  143. M3RN , 64, // Memory Controller Range 3
  144. M4RN , 64, // Memory Controller Range 4
  145. M5RN , 64, // Memory Controller Range 5
  146. M6RN , 64, // Memory Controller Range 6
  147. M7RN , 64, // Memory Controller Range 7
  148. SMI0 , 32, // Parameter0 used for faked SMI request
  149. SMI1 , 32, // Parameter1 used for faked SMI request
  150. SMI2 , 32, // Parameter2 used for faked SMI request
  151. SMI3 , 32, // Parameter3 used for faked SMI request
  152. SCI0 , 32, // Parameter0 used for faked SCI request
  153. SCI1 , 32, // Parameter1 used for faked SCI request
  154. SCI2 , 32, // Parameter2 used for faked SCI request
  155. SCI3 , 32, // Parameter3 used for faked SCI request
  156. MADD , 64, // Migration ActionRegion GAS address. (Migration support written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 are invalid.)
  157. CUU0 , 128, // CPU0 UUID
  158. CUU1 , 128, // CPU1 UUID
  159. CUU2 , 128, // CPU2 UUID
  160. CUU3 , 128, // CPU3 UUID
  161. CUU4 , 128, // CPU4 UUID
  162. CUU5 , 128, // CPU5 UUID
  163. CUU6 , 128, // CPU6 UUID
  164. CUU7 , 128, // CPU7 UUID
  165. CPSP , 8, // CPU spare bitmap. 1 == IsSpare.
  166. ME00 , 128, // MEM0 UUID
  167. ME01 , 128, // MEM1 UUID
  168. ME10 , 128, // MEM2 UUID
  169. ME11 , 128, // MEM3 UUID
  170. ME20 , 128, // MEM4 UUID
  171. ME21 , 128, // MEM5 UUID
  172. ME30 , 128, // MEM6 UUID
  173. ME31 , 128, // MEM7 UUID
  174. ME40 , 128, // MEM8 UUID
  175. ME41 , 128, // MEM9 UUID
  176. ME50 , 128, // MEM10 UUID
  177. ME51 , 128, // MEM11 UUID
  178. ME60 , 128, // MEM12 UUID
  179. ME61 , 128, // MEM13 UUID
  180. ME70 , 128, // MEM14 UUID
  181. ME71 , 128, // MEM15 UUID
  182. MESP , 16, // Memory module spare bitmap. 1 == IsSpare.
  183. LDIR , 64, // L1 Directory Address
  184. PRID , 32, // Processor ID
  185. AHPE , 8, // ACPI PCIe hot plug enable.
  186. // RAS End
  187. // VTD Start
  188. DHRD , 192, // DHRD
  189. ATSR , 192, // ATSR
  190. RHSA , 192, // RHSA
  191. // VTD End
  192. // BIOS Guard Start
  193. CNBS , 8, // CPU SKU number bit shift
  194. // BIOS Guard End
  195. // USB3 Start
  196. XHMD , 8, // copy of setup item PchUsb30Mode
  197. SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1)
  198. SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2)
  199. // USB3 End
  200. // HWPM Start
  201. , 2, // HWPM State Enable option from setup
  202. , 1, // Aunomous C-state Enable option from setup
  203. HWPI , 1, // HWP Interrupt
  204. , 4, // Reserved bits
  205. // HWPM End
  206. // PCIe Multi-Seg Start
  207. BB00 , 8, // Bus Base for PC00
  208. BB01 , 8, // Bus Base for PC01
  209. BB02 , 8, // Bus Base for PC02
  210. BB03 , 8, // Bus Base for PC03
  211. BB04 , 8, // Bus Base for PC04
  212. BB05 , 8, // Bus Base for PC05
  213. BB06 , 8, // Bus Base for PC06
  214. BB07 , 8, // Bus Base for PC07
  215. BB08 , 8, // Bus Base for PC08
  216. BB09 , 8, // Bus Base for PC09
  217. BB10 , 8, // Bus Base for PC10
  218. BB11 , 8, // Bus Base for PC11
  219. BB12 , 8, // Bus Base for PC12
  220. BB13 , 8, // Bus Base for PC13
  221. BB14 , 8, // Bus Base for PC14
  222. BB15 , 8, // Bus Base for PC15
  223. BB16 , 8, // Bus Base for PC16
  224. BB17 , 8, // Bus Base for PC17
  225. BB18 , 8, // Bus Base for PC18
  226. BB19 , 8, // Bus Base for PC19
  227. BB20 , 8, // Bus Base for PC20
  228. BB21 , 8, // Bus Base for PC21
  229. BB22 , 8, // Bus Base for PC22
  230. BB23 , 8, // Bus Base for PC23
  231. BB24 , 8, // Bus Base for PC24
  232. BB25 , 8, // Bus Base for PC25
  233. BB26 , 8, // Bus Base for PC26
  234. BB27 , 8, // Bus Base for PC27
  235. BB28 , 8, // Bus Base for PC28
  236. BB29 , 8, // Bus Base for PC29
  237. BB30 , 8, // Bus Base for PC30
  238. BB31 , 8, // Bus Base for PC31
  239. BB32 , 8, // Bus Base for PC32
  240. BB33 , 8, // Bus Base for PC33
  241. BB34 , 8, // Bus Base for PC34
  242. BB35 , 8, // Bus Base for PC35
  243. BB36 , 8, // Bus Base for PC36
  244. BB37 , 8, // Bus Base for PC37
  245. BB38 , 8, // Bus Base for PC38
  246. BB39 , 8, // Bus Base for PC39
  247. BB40 , 8, // Bus Base for PC40
  248. BB41 , 8, // Bus Base for PC41
  249. BB42 , 8, // Bus Base for PC42
  250. BB43 , 8, // Bus Base for PC43
  251. BB44 , 8, // Bus Base for PC44
  252. BB45 , 8, // Bus Base for PC45
  253. BB46 , 8, // Bus Base for PC46
  254. BB47 , 8, // Bus Base for PC47
  255. SGEN , 8, // PCIe_MultiSeg_Support enable/disable
  256. SG00 , 8, // Segment ID for Segment Group 0
  257. SG01 , 8, // Segment ID for Segment Group 1
  258. SG02 , 8, // Segment ID for Segment Group 2
  259. SG03 , 8, // Segment ID for Segment Group 3
  260. SG04 , 8, // Segment ID for Segment Group 4
  261. SG05 , 8, // Segment ID for Segment Group 5
  262. SG06 , 8, // Segment ID for Segment Group 6
  263. SG07 , 8, // Segment ID for Segment Group 7
  264. // PCIe Multi-Seg End
  265. // Performance start
  266. CLOD , 8, // SncAnd2Cluster, i.e. 1=SNC enable and 2 Clusters, 0 otherwise
  267. // Performance End
  268. }