OpenBoardPkg.fdf 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589
  1. ## @file
  2. # FDF file for the MtOlympus board.
  3. #
  4. # Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. # Note: FlashNv PCD naming conventions are as follows:
  11. # Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
  12. # Others should be examined with an effort to work toward this guideline.
  13. # PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
  14. # PcdFlash*Size is a hex count of the length of the FD or FV
  15. # All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
  16. #
  17. # Also all values will have a PCD assigned so that they can be used in the system, and
  18. # the FlashMap edit tool can be used to change the values here, without effecting the code.
  19. # This requires all code to only use the PCD tokens to recover the values.
  20. [FD.Platform]
  21. BaseAddress = 0xFF000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress
  22. Size = 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSize
  23. ErasePolarity = 1
  24. BlockSize = 0x10000
  25. NumBlocks = 0x100
  26. 0x00000000|0x00500000
  27. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  28. FV = FvAdvanced
  29. 0x00500000|0x00100000
  30. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  31. FV = FvSecurity
  32. 0x00600000|0x00100000
  33. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  34. FV = FvOsBoot
  35. 0x00700000|0x00200000
  36. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
  37. FV = FvLateSiliconCompressed
  38. 0x00900000|0x00400000
  39. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  40. FV = FvUefiBoot
  41. 0x00D00000|0x0007C000
  42. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  43. #NV_VARIABLE_STORE
  44. DATA = {
  45. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  46. # ZeroVector []
  47. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  48. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  49. # FileSystemGuid: gEfiSystemNvDataFvGuid =
  50. # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
  51. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  52. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  53. # FvLength: 0x100000
  54. 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
  55. #Signature "_FVH" #Attributes
  56. 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
  57. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  58. 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02,
  59. #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block
  60. 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  61. #Blockmap[1]: End
  62. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  63. ## This is the VARIABLE_STORE_HEADER
  64. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  65. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }
  66. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  67. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  68. !else
  69. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  70. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  71. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  72. !endif
  73. #Size: 0x7c000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x7BFFB8
  74. # This can speed up the Variable Dispatch a bit.
  75. 0xB8, 0xBF, 0x07, 0x00,
  76. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  77. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  78. }
  79. 0x00D7C000|0x00002000
  80. #NV_EVENT_LOG
  81. 0x00D7E000|0x00002000
  82. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  83. #NV_FTW_WORKING
  84. DATA = {
  85. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  86. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  87. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  88. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  89. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  90. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  91. # WriteQueueSize: UINT64
  92. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  93. }
  94. 0x00D80000|0x00080000
  95. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  96. #NV_FTW_SPARE
  97. 0x00E00000|0x00010000
  98. gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  99. FV = MICROCODE_FV
  100. 0x00E10000|0x00010000
  101. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  102. FV = FvPostMemory
  103. 0x00E20000|0x00030000
  104. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  105. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv
  106. 0x00E50000|0x00060000
  107. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  108. FV = FvPreMemory
  109. 0x00EB0000|0x00130000
  110. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  111. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv
  112. 0x00FE0000|0x00020000
  113. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  114. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.Fv
  115. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
  116. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  117. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
  118. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
  119. SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
  120. SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
  121. ################################################################################
  122. #
  123. # FV Section
  124. #
  125. # [FV] section is used to define what components or modules are placed within a flash
  126. # device file. This section also defines order the components and modules are positioned
  127. # within the image. The [FV] section consists of define statements, set statements and
  128. # module statements.
  129. #
  130. ################################################################################
  131. [FV.FvLateSiliconCompressed]
  132. FvAlignment = 16
  133. ERASE_POLARITY = 1
  134. MEMORY_MAPPED = TRUE
  135. STICKY_WRITE = TRUE
  136. LOCK_CAP = TRUE
  137. LOCK_STATUS = TRUE
  138. WRITE_DISABLED_CAP = TRUE
  139. WRITE_ENABLED_CAP = TRUE
  140. WRITE_STATUS = TRUE
  141. WRITE_LOCK_CAP = TRUE
  142. WRITE_LOCK_STATUS = TRUE
  143. READ_DISABLED_CAP = TRUE
  144. READ_ENABLED_CAP = TRUE
  145. READ_STATUS = TRUE
  146. READ_LOCK_CAP = TRUE
  147. READ_LOCK_STATUS = TRUE
  148. FvNameGuid = BA793112-EA2E-47C4-9AFE-A8FCFE603D6D
  149. FILE FV_IMAGE = A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F {
  150. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  151. SECTION FV_IMAGE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.Fv
  152. }
  153. }
  154. [FV.MICROCODE_FV]
  155. FvAlignment = 16
  156. ERASE_POLARITY = 1
  157. MEMORY_MAPPED = TRUE
  158. STICKY_WRITE = TRUE
  159. LOCK_CAP = TRUE
  160. LOCK_STATUS = FALSE
  161. WRITE_DISABLED_CAP = TRUE
  162. WRITE_ENABLED_CAP = TRUE
  163. WRITE_STATUS = TRUE
  164. WRITE_LOCK_CAP = TRUE
  165. WRITE_LOCK_STATUS = TRUE
  166. READ_DISABLED_CAP = TRUE
  167. READ_ENABLED_CAP = TRUE
  168. READ_STATUS = TRUE
  169. READ_LOCK_CAP = TRUE
  170. READ_LOCK_STATUS = TRUE
  171. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf
  172. [FV.FvPreMemory]
  173. FvAlignment = 16
  174. FvForceRebase = TRUE
  175. ERASE_POLARITY = 1
  176. MEMORY_MAPPED = TRUE
  177. STICKY_WRITE = TRUE
  178. LOCK_CAP = TRUE
  179. LOCK_STATUS = TRUE
  180. WRITE_DISABLED_CAP = TRUE
  181. WRITE_ENABLED_CAP = TRUE
  182. WRITE_STATUS = TRUE
  183. WRITE_LOCK_CAP = TRUE
  184. WRITE_LOCK_STATUS = TRUE
  185. READ_DISABLED_CAP = TRUE
  186. READ_ENABLED_CAP = TRUE
  187. READ_STATUS = TRUE
  188. READ_LOCK_CAP = TRUE
  189. READ_LOCK_STATUS = TRUE
  190. FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
  191. ##
  192. # PEI Apriori file example, more PEIM module added later.
  193. ##
  194. INF MdeModulePkg/Core/Pei/PeiMain.inf
  195. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  196. INF $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf
  197. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  198. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  199. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  200. [FV.FvPostMemory]
  201. FvAlignment = 16
  202. ERASE_POLARITY = 1
  203. MEMORY_MAPPED = TRUE
  204. STICKY_WRITE = TRUE
  205. LOCK_CAP = TRUE
  206. LOCK_STATUS = TRUE
  207. WRITE_DISABLED_CAP = TRUE
  208. WRITE_ENABLED_CAP = TRUE
  209. WRITE_STATUS = TRUE
  210. WRITE_LOCK_CAP = TRUE
  211. WRITE_LOCK_STATUS = TRUE
  212. READ_DISABLED_CAP = TRUE
  213. READ_ENABLED_CAP = TRUE
  214. READ_STATUS = TRUE
  215. READ_LOCK_CAP = TRUE
  216. READ_LOCK_STATUS = TRUE
  217. FvNameGuid = C54E3E8D-9FF5-4D52-AF03-58018EB55F63
  218. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  219. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  220. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  221. [FV.FvUefiBootUncompact]
  222. BlockSize = 0x10000
  223. FvAlignment = 16
  224. ERASE_POLARITY = 1
  225. MEMORY_MAPPED = TRUE
  226. STICKY_WRITE = TRUE
  227. LOCK_CAP = TRUE
  228. LOCK_STATUS = TRUE
  229. WRITE_DISABLED_CAP = TRUE
  230. WRITE_ENABLED_CAP = TRUE
  231. WRITE_STATUS = TRUE
  232. WRITE_LOCK_CAP = TRUE
  233. WRITE_LOCK_STATUS = TRUE
  234. READ_DISABLED_CAP = TRUE
  235. READ_ENABLED_CAP = TRUE
  236. READ_STATUS = TRUE
  237. READ_LOCK_CAP = TRUE
  238. READ_LOCK_STATUS = TRUE
  239. FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
  240. ##
  241. # DXE Phase modules
  242. ##
  243. ##
  244. # DXE Apriori file example, more DXE module added later.
  245. ##
  246. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  247. INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf
  248. INF $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf
  249. INF $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf
  250. INF $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf
  251. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  252. INF ShellPkg/Application/Shell/Shell.inf
  253. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  254. [FV.FvUefiBoot]
  255. FvAlignment = 16
  256. ERASE_POLARITY = 1
  257. MEMORY_MAPPED = TRUE
  258. STICKY_WRITE = TRUE
  259. LOCK_CAP = TRUE
  260. LOCK_STATUS = TRUE
  261. WRITE_DISABLED_CAP = TRUE
  262. WRITE_ENABLED_CAP = TRUE
  263. WRITE_STATUS = TRUE
  264. WRITE_LOCK_CAP = TRUE
  265. WRITE_LOCK_STATUS = TRUE
  266. READ_DISABLED_CAP = TRUE
  267. READ_ENABLED_CAP = TRUE
  268. READ_STATUS = TRUE
  269. READ_LOCK_CAP = TRUE
  270. READ_LOCK_STATUS = TRUE
  271. FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
  272. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  273. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  274. SECTION FV_IMAGE = FvUefiBootUncompact
  275. }
  276. }
  277. [FV.FvOsBootUncompact]
  278. FvAlignment = 16
  279. ERASE_POLARITY = 1
  280. MEMORY_MAPPED = TRUE
  281. STICKY_WRITE = TRUE
  282. LOCK_CAP = TRUE
  283. LOCK_STATUS = TRUE
  284. WRITE_DISABLED_CAP = TRUE
  285. WRITE_ENABLED_CAP = TRUE
  286. WRITE_STATUS = TRUE
  287. WRITE_LOCK_CAP = TRUE
  288. WRITE_LOCK_STATUS = TRUE
  289. READ_DISABLED_CAP = TRUE
  290. READ_ENABLED_CAP = TRUE
  291. READ_STATUS = TRUE
  292. READ_LOCK_CAP = TRUE
  293. READ_LOCK_STATUS = TRUE
  294. FvNameGuid = 5AB52883-85DF-445B-99F7-E0C1D517A905
  295. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  296. INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  297. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  298. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  299. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  300. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  301. [FV.FvOsBoot]
  302. FvAlignment = 16
  303. ERASE_POLARITY = 1
  304. MEMORY_MAPPED = TRUE
  305. STICKY_WRITE = TRUE
  306. LOCK_CAP = TRUE
  307. LOCK_STATUS = TRUE
  308. WRITE_DISABLED_CAP = TRUE
  309. WRITE_ENABLED_CAP = TRUE
  310. WRITE_STATUS = TRUE
  311. WRITE_LOCK_CAP = TRUE
  312. WRITE_LOCK_STATUS = TRUE
  313. READ_DISABLED_CAP = TRUE
  314. READ_ENABLED_CAP = TRUE
  315. READ_STATUS = TRUE
  316. READ_LOCK_CAP = TRUE
  317. READ_LOCK_STATUS = TRUE
  318. FvNameGuid = 5e2363c4-3e9e-4203-b873-bb40df46c8e6
  319. FILE FV_IMAGE = AC09A11F-BD9F-4C87-B656-F4868EEA89B8 {
  320. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  321. SECTION FV_IMAGE = FvOsBootUncompact
  322. }
  323. }
  324. [FV.FvSecurityPreMem]
  325. FvAlignment = 16
  326. ERASE_POLARITY = 1
  327. MEMORY_MAPPED = TRUE
  328. STICKY_WRITE = TRUE
  329. LOCK_CAP = TRUE
  330. LOCK_STATUS = TRUE
  331. WRITE_DISABLED_CAP = TRUE
  332. WRITE_ENABLED_CAP = TRUE
  333. WRITE_STATUS = TRUE
  334. WRITE_LOCK_CAP = TRUE
  335. WRITE_LOCK_STATUS = TRUE
  336. READ_DISABLED_CAP = TRUE
  337. READ_ENABLED_CAP = TRUE
  338. READ_STATUS = TRUE
  339. READ_LOCK_CAP = TRUE
  340. READ_LOCK_STATUS = TRUE
  341. FvNameGuid = A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA
  342. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  343. [FV.FvSecurityPostMem]
  344. FvAlignment = 16
  345. ERASE_POLARITY = 1
  346. MEMORY_MAPPED = TRUE
  347. STICKY_WRITE = TRUE
  348. LOCK_CAP = TRUE
  349. LOCK_STATUS = TRUE
  350. WRITE_DISABLED_CAP = TRUE
  351. WRITE_ENABLED_CAP = TRUE
  352. WRITE_STATUS = TRUE
  353. WRITE_LOCK_CAP = TRUE
  354. WRITE_LOCK_STATUS = TRUE
  355. READ_DISABLED_CAP = TRUE
  356. READ_ENABLED_CAP = TRUE
  357. READ_STATUS = TRUE
  358. READ_LOCK_CAP = TRUE
  359. READ_LOCK_STATUS = TRUE
  360. FvNameGuid = 04B00029-2391-44C1-97BA-3FA8A42E9D3A
  361. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  362. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  363. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  364. !endif
  365. [FV.FvSecurityLate]
  366. FvAlignment = 16
  367. ERASE_POLARITY = 1
  368. MEMORY_MAPPED = TRUE
  369. STICKY_WRITE = TRUE
  370. LOCK_CAP = TRUE
  371. LOCK_STATUS = TRUE
  372. WRITE_DISABLED_CAP = TRUE
  373. WRITE_ENABLED_CAP = TRUE
  374. WRITE_STATUS = TRUE
  375. WRITE_LOCK_CAP = TRUE
  376. WRITE_LOCK_STATUS = TRUE
  377. READ_DISABLED_CAP = TRUE
  378. READ_ENABLED_CAP = TRUE
  379. READ_STATUS = TRUE
  380. READ_LOCK_CAP = TRUE
  381. READ_LOCK_STATUS = TRUE
  382. FvNameGuid = CCBC50ED-0902-413E-BC2C-409C906F4A80
  383. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  384. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  385. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  386. !endif
  387. [FV.FvSecurity]
  388. FvAlignment = 16
  389. ERASE_POLARITY = 1
  390. MEMORY_MAPPED = TRUE
  391. STICKY_WRITE = TRUE
  392. LOCK_CAP = TRUE
  393. LOCK_STATUS = TRUE
  394. WRITE_DISABLED_CAP = TRUE
  395. WRITE_ENABLED_CAP = TRUE
  396. WRITE_STATUS = TRUE
  397. WRITE_LOCK_CAP = TRUE
  398. WRITE_LOCK_STATUS = TRUE
  399. READ_DISABLED_CAP = TRUE
  400. READ_ENABLED_CAP = TRUE
  401. READ_STATUS = TRUE
  402. READ_LOCK_CAP = TRUE
  403. READ_LOCK_STATUS = TRUE
  404. FvNameGuid = 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7
  405. FILE FV_IMAGE = A63B2BBF-7A02-4862-BF22-A1BA5258DD68 {
  406. SECTION FV_IMAGE = FvSecurityPreMem
  407. }
  408. FILE FV_IMAGE = 47B40638-0087-4938-97CF-B56983A1A07B {
  409. SECTION FV_IMAGE = FvSecurityPostMem
  410. }
  411. FILE FV_IMAGE = 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 {
  412. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  413. SECTION FV_IMAGE = FvSecurityLate
  414. }
  415. }
  416. [FV.FvAdvancedPreMem]
  417. FvAlignment = 16
  418. ERASE_POLARITY = 1
  419. MEMORY_MAPPED = TRUE
  420. STICKY_WRITE = TRUE
  421. LOCK_CAP = TRUE
  422. LOCK_STATUS = TRUE
  423. WRITE_DISABLED_CAP = TRUE
  424. WRITE_ENABLED_CAP = TRUE
  425. WRITE_STATUS = TRUE
  426. WRITE_LOCK_CAP = TRUE
  427. WRITE_LOCK_STATUS = TRUE
  428. READ_DISABLED_CAP = TRUE
  429. READ_ENABLED_CAP = TRUE
  430. READ_STATUS = TRUE
  431. READ_LOCK_CAP = TRUE
  432. READ_LOCK_STATUS = TRUE
  433. FvNameGuid = EBC45843-B180-44D3-A485-0031A75DB16D
  434. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  435. [FV.FvAdvancedUncompact]
  436. FvAlignment = 16
  437. ERASE_POLARITY = 1
  438. MEMORY_MAPPED = TRUE
  439. STICKY_WRITE = TRUE
  440. LOCK_CAP = TRUE
  441. LOCK_STATUS = TRUE
  442. WRITE_DISABLED_CAP = TRUE
  443. WRITE_ENABLED_CAP = TRUE
  444. WRITE_STATUS = TRUE
  445. WRITE_LOCK_CAP = TRUE
  446. WRITE_LOCK_STATUS = TRUE
  447. READ_DISABLED_CAP = TRUE
  448. READ_ENABLED_CAP = TRUE
  449. READ_STATUS = TRUE
  450. READ_LOCK_CAP = TRUE
  451. READ_LOCK_STATUS = TRUE
  452. FvNameGuid = 05411CAD-6C35-4675-B6CA-8748032144B4
  453. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  454. [FV.FvAdvanced]
  455. FvAlignment = 16
  456. ERASE_POLARITY = 1
  457. MEMORY_MAPPED = TRUE
  458. STICKY_WRITE = TRUE
  459. LOCK_CAP = TRUE
  460. LOCK_STATUS = TRUE
  461. WRITE_DISABLED_CAP = TRUE
  462. WRITE_ENABLED_CAP = TRUE
  463. WRITE_STATUS = TRUE
  464. WRITE_LOCK_CAP = TRUE
  465. WRITE_LOCK_STATUS = TRUE
  466. READ_DISABLED_CAP = TRUE
  467. READ_ENABLED_CAP = TRUE
  468. READ_STATUS = TRUE
  469. READ_LOCK_CAP = TRUE
  470. READ_LOCK_STATUS = TRUE
  471. FvNameGuid = 59584CB6-0740-4EE6-A335-A46B370A101A
  472. FILE FV_IMAGE = 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 {
  473. SECTION FV_IMAGE = FvAdvancedPreMem
  474. }
  475. FILE FV_IMAGE = 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 {
  476. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  477. SECTION FV_IMAGE = FvAdvancedUncompact
  478. }
  479. }
  480. [FV.FvDummy]
  481. FvAlignment = 16
  482. FvForceRebase = FALSE
  483. ERASE_POLARITY = 1
  484. MEMORY_MAPPED = TRUE
  485. STICKY_WRITE = TRUE
  486. LOCK_CAP = TRUE
  487. LOCK_STATUS = TRUE
  488. WRITE_DISABLED_CAP = TRUE
  489. WRITE_ENABLED_CAP = TRUE
  490. WRITE_STATUS = TRUE
  491. WRITE_LOCK_CAP = TRUE
  492. WRITE_LOCK_STATUS = TRUE
  493. READ_DISABLED_CAP = TRUE
  494. READ_ENABLED_CAP = TRUE
  495. READ_STATUS = TRUE
  496. READ_LOCK_CAP = TRUE
  497. READ_LOCK_STATUS = TRUE
  498. # Add dummy FV here to build the PCD in FV into PCD database.
  499. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf
  500. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf
  501. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf
  502. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.inf
  503. ################################################################################
  504. #
  505. # Rules are use with the [FV] section's module INF type to define
  506. # how an FFS file is created for a given INF file. The following Rule are the default
  507. # rules for the different module type. User can add the customized rules to define the
  508. # content of the FFS file.
  509. #
  510. ################################################################################
  511. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf