PchXhci.asi 7.7 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. Name (OPAC, Zero)
  6. Name (XRST, Zero)
  7. Name (XUSB, Zero)
  8. OperationRegion (XPRT, PCI_Config, 0x74, 0x6C)
  9. Field (XPRT, DWordAcc, NoLock, Preserve)
  10. {
  11. , 8,
  12. PMEE, 1, // PWR_CNTL_STS.PME_En
  13. , 6,
  14. PMES, 1, // PWR_CNTL_STS.PME_Sts
  15. Offset (0x5C),
  16. PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
  17. PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
  18. PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
  19. PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
  20. }
  21. Method (_PSW,1)
  22. {
  23. If (Arg0)
  24. {
  25. Store (Ones,PMEE)
  26. }
  27. Else
  28. {
  29. Store (0,PMEE)
  30. }
  31. }
  32. //
  33. // Indicate access to OperationRegions is enabled/disabled
  34. //
  35. Method (_REG, 2) {
  36. //
  37. // If OperationRegion ID = PCI_Config
  38. //
  39. If (LEqual (Arg0, 2)) {
  40. //
  41. // If access is enabled
  42. //
  43. If (LEqual(Arg1, 1)) {
  44. //
  45. // Set local flag
  46. //
  47. Store (One, OPAC)
  48. } Else {
  49. //
  50. // Clear local flag
  51. //
  52. Store (One, OPAC)
  53. }
  54. }
  55. }
  56. //
  57. // Initialization for this controller
  58. //
  59. Method (_INI, 0) {
  60. //
  61. // If access to OperationRegion is enabled
  62. //
  63. If (LEqual (OPAC, One)) {
  64. Store (1, PMES) // clear PME status
  65. Store (0, PMEE) // clear PME enable
  66. }
  67. }
  68. //
  69. // _OSC for xHCI
  70. // This method enables XHCI controller if available.
  71. //
  72. // Arguments:
  73. // Arg0 (Integer): Revision ID - should be set to 1
  74. //
  75. // Arg1 (Integer): Count of DWords in Arg3
  76. //
  77. // Arg2 (Buffer) : Capabilities Buffer
  78. // DWORD #0 (Status/Error):
  79. // Bit 0 - Query Support Flag
  80. // Bit 1 - Always clear(0)
  81. // Bit 2 - Always clear(0)
  82. // Bit 3 - Always clear(0)
  83. //
  84. // All others - reserved
  85. //
  86. // DWORD #1 (Supported):
  87. // Bit 0 - 1: Switch to xHCI
  88. //
  89. // All others - reserved
  90. //
  91. // DWORD #2 (Controlled):
  92. // Bit 0 - 1: Clear Smart Auto state (disable xHCI)
  93. //
  94. // All others - reserved
  95. //
  96. // Returns:
  97. // Capabilities Buffer:
  98. // DWORD #0 (Status):
  99. // Bit 0 - Reserved (not used)
  100. //
  101. // Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query.
  102. // Capabilities bits may have been masked.
  103. //
  104. // Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware
  105. // does not recognize the UUID passed in _OSC Arg0.
  106. // Capabilities bits are preserved.
  107. //
  108. // Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware
  109. // does not recognize the Revision ID passed in via Arg1.
  110. // Capabilities bits beyond those comprehended by the firmware will be masked.
  111. //
  112. // Bit 4 - Capabilities Masked. This bit is set to indicate
  113. // that capabilities bits set by driver software
  114. // have been cleared by platform firmware.
  115. //
  116. // Bit 5 - 0: EHCI controller exposed to OS
  117. // 1: xHCI controller exposed to OS
  118. //
  119. // All others - reserved (return 0)
  120. //
  121. // DWORD #1 (Supported):
  122. // Bit 0 - 0: EHCI supported
  123. // 1: xHCI supported
  124. //
  125. // All others - reserved
  126. //
  127. // DWORD #2 (Controlled):
  128. //
  129. // All bits - reserved
  130. //
  131. Method (POSC, 3) {
  132. Store (0x81, IO80)
  133. //
  134. // Create DWord fields from the Capabilities Buffer
  135. //
  136. CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0 of Arg2
  137. CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4 of Arg2
  138. CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8 of Arg2
  139. //
  140. // Are we running a version of Windows that runs the Intel xHCI driver?
  141. // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7
  142. //
  143. If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) {
  144. //
  145. // Running Windows
  146. // Check revision is >= 2
  147. //
  148. If (LLess (Arg0, 2)) {
  149. //
  150. // Set unknown revision bit
  151. //
  152. Or (CDW1, 8, CDW1)
  153. Store (0x82, IO80)
  154. }
  155. } Else {
  156. //
  157. // If the Intel xHCI driver not calling,
  158. // then it must be SVOS
  159. If (LNotEqual (Arg0, 1)) {
  160. //
  161. // Set unknown revision bit
  162. //
  163. Or (CDW1, 8, CDW1)
  164. Store (0x82, IO80)
  165. }
  166. }
  167. //
  168. // Set failure if xHCI is disabled by BIOS
  169. //
  170. If (LEqual (XHMD, 0)) {
  171. Or (CDW1, 2, CDW1)
  172. Store (0x83, IO80)
  173. }
  174. //
  175. // If no error bits set
  176. //
  177. If (LEqual (And (CDW1, 0xE), 0)) {
  178. //
  179. // If not just querying support
  180. //
  181. If (LNot (And (CDW1, 1))) {
  182. //
  183. // If uninstaller calling
  184. // to switch back to EHCI
  185. //
  186. If (And (CDW3, 1)) {
  187. //
  188. // Switch to EHCI
  189. //
  190. ESEL()
  191. Store (0x85, IO80)
  192. //
  193. // And clear ACPINVS variable
  194. // that is a copy of USB3.0 setup option
  195. // so that we will not re-enable xHCI until
  196. // the next reboot
  197. //
  198. Store (0, XHMD)
  199. }
  200. //
  201. // Uninstaller not calling,
  202. // OS wants to enable xHCI?
  203. //
  204. If (And (CDW2, 1)) {
  205. //
  206. // Switch to xHCI
  207. //
  208. XSEL(0)
  209. Store (0x84, IO80)
  210. } Else {
  211. //
  212. // Switch to EHCI
  213. //
  214. ESEL()
  215. Store (0x85, IO80)
  216. }
  217. }
  218. }
  219. Return(Arg2)
  220. }
  221. //
  222. // Put all ports in XHCI mode
  223. //
  224. Method (XSEL, 1, Serialized) {
  225. //
  226. // If xHCI in auto or smart auto mode
  227. // or Arg0 == 1
  228. //
  229. If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) {
  230. //
  231. // If xHCI in smart auto mode
  232. //
  233. If (LEqual (XHMD, 3)) {
  234. //
  235. // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI controller
  236. //
  237. Store (1, \_SB.PC00.LPC0.XSMB)
  238. }
  239. //
  240. // Set flags so on Sx resume, we'll know OS has previously
  241. // routed ports to xHCI
  242. //
  243. Store (1, XUSB)
  244. Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx
  245. //
  246. // Enable selected SS ports, route corresponding HS ports to xHCI
  247. //
  248. Store (0, Local0)
  249. And (PR3, 0xFFFFFFC0, Local0)
  250. Or (Local0, PR3M, PR3)
  251. Store (0, Local0)
  252. And (PR2, 0xFFFF8000, Local0)
  253. Or (Local0, PR2M, PR2)
  254. }
  255. }
  256. //
  257. // Put all ports in EHCI mode
  258. //
  259. Method (ESEL, 0, Serialized) {
  260. //
  261. // xHCI in auto or smart auto mode
  262. //
  263. If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) {
  264. //
  265. // Disable all SS ports, route all HS ports to EHCI
  266. //
  267. And (PR3, 0xFFFFFFC0, PR3)
  268. And (PR2, 0xFFFF8000, PR2)
  269. //
  270. // Mark as not routed.
  271. //
  272. Store (0, XUSB)
  273. Store (0, XRST)
  274. }
  275. }
  276. Method (XWAK, 0, Serialized) {
  277. //
  278. // If ports were routed to xHCI before sleep
  279. //
  280. If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) {
  281. //
  282. // Restore back to xHCI, ignore XHMD
  283. //
  284. XSEL(1)
  285. //
  286. // And tell OS to re-enumerate xHCI
  287. //
  288. Notify (\_SB.PC00.XHCI, 0x00)
  289. }
  290. }
  291. //
  292. // Report what D state the controller is in
  293. // when the system changes to S3 and S4
  294. //
  295. Method(_S3D, 0, NotSerialized) {
  296. Return(2)
  297. }
  298. Method(_S4D, 0, NotSerialized) {
  299. Return(2)
  300. }