CommonPlatform.asi 4.1 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include "MaxSocket.h"
  6. //
  7. // External declarations
  8. // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl
  9. //
  10. External(\_SB.PC00.HEC2.HPTS, MethodObj)
  11. External(\_SB.PC00.HEC2.HWAK, MethodObj)
  12. //
  13. // System Sleep States
  14. //
  15. Name (\_S0,Package (){0,0,0,0})
  16. Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in Setup
  17. Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in Setup
  18. Name (\_S5,Package (){7,0,0,0})
  19. //
  20. // Native OS hot plug support, 0->ACPI, 1->OS
  21. //
  22. Name (\OSHF, 0)
  23. //
  24. // OS flag
  25. //
  26. #include "Os.asi"
  27. //
  28. // for determing PIC mode
  29. //
  30. Name (\PICM,Zero)
  31. Method (\_PIC, 1, NotSerialized) {
  32. Store(Arg0,\PICM)
  33. }
  34. OperationRegion (DBG0, SystemIO, 0x80, 2)
  35. Field (DBG0, ByteAcc,NoLock,Preserve) {
  36. IO80, 8,
  37. IO81, 8
  38. }
  39. //
  40. // Access CMOS range
  41. //
  42. OperationRegion (ACMS, SystemIO, 0x72, 2)
  43. Field ( ACMS, ByteAcc, NoLock, Preserve) {
  44. INDX, 8,
  45. DATA, 8
  46. }
  47. //
  48. // SWGPE_CTRL
  49. //
  50. OperationRegion (GPCT, SystemIO, 0x442, 1)
  51. Field ( GPCT, ByteAcc, NoLock, Preserve) {
  52. , 1,
  53. SGPC , 1,
  54. }
  55. //
  56. // GPI_INV
  57. //
  58. OperationRegion (GPIV, SystemIO, 0x52c, 2)
  59. Field ( GPIV, ByteAcc, NoLock, Preserve) {
  60. GP0I , 1,
  61. }
  62. #include "Acpi/GlobalNvs.asi"
  63. //
  64. // Operation region for GPI status bits
  65. //
  66. OperationRegion (GSTS, SystemIO, 0x422, 2)
  67. Field ( GSTS, ByteAcc, NoLock, Preserve) {
  68. GP00 , 1,
  69. , 12,
  70. GP13 , 1,
  71. }
  72. //
  73. // GPE0 HOT_PLUG_EN
  74. //
  75. OperationRegion (GPE0, SystemIO, 0x428, 8)
  76. Field (GPE0, ByteAcc,NoLock,Preserve) {
  77. ,1,
  78. GPEH,1,
  79. ,1,
  80. USB1,1,
  81. USB2,1,
  82. USB5,1,
  83. ,3,
  84. PCIE,1,
  85. ,1,
  86. PMEE,1,
  87. USB3,1,
  88. PMB0,1,
  89. USB4,1,
  90. ,9,
  91. ,1,
  92. ,7,
  93. USB6,1,
  94. ,15,
  95. }
  96. //
  97. // GPES Status
  98. //
  99. OperationRegion (GPES, SystemIO, 0x420, 8)
  100. Field (GPES, ByteAcc,NoLock,Preserve) {
  101. ,1,
  102. GPSH,1,
  103. SGPS,1,
  104. US1S,1,
  105. US2S,1,
  106. US5S,1,
  107. ,1,
  108. SMWS,1,
  109. ,1,
  110. PEES,1,
  111. ,1,
  112. PMES,1,
  113. US3S ,1,
  114. PMBS,1,
  115. US4S ,1,
  116. ,9,
  117. ,1,
  118. ,7,
  119. US6S,1,
  120. ,15,
  121. }
  122. //
  123. // System sleep down
  124. //
  125. Method (_PTS, 1, NotSerialized)
  126. {
  127. Store (0x72, IO80) // Sync with EfiPostCode.h
  128. //
  129. // Clear wake event status.
  130. //
  131. Store(1,US1S)
  132. Store(1,US2S)
  133. Store(1,US5S)
  134. Store(1,SMWS)
  135. Store(1,PMES)
  136. Store(1,US3S)
  137. Store(1,PMBS)
  138. Store(1,US4S)
  139. Store(1,US6S)
  140. //
  141. // Enable SCI and wake event sources.
  142. //
  143. Store(1,GPEH)
  144. Store(1,USB1)
  145. Store(1,USB2)
  146. Store(1,USB5)
  147. Store(1,PCIE)
  148. Store(1,PMEE)
  149. Store(1,USB3)
  150. Store(1,PMB0)
  151. Store(1,USB4)
  152. Store(1,USB6)
  153. //
  154. // If HECI-2 exist call its prepare-to-sleep handler.
  155. // The handler checks whether HECI-2 is enabled.
  156. //
  157. If (CondRefOf(\_SB.PC00.HEC2.HPTS))
  158. {
  159. \_SB.PC00.HEC2.HPTS()
  160. }
  161. /// WA for S3 on XHCI
  162. \_SB.PC00.XHCI.XHCS()
  163. }
  164. //#include "Uncore.asi"
  165. //
  166. // System Wake up
  167. //
  168. Method (_WAK, 1, Serialized)
  169. {
  170. Store (0x73, IO80) // Sync with EfiPostCode.h
  171. //
  172. // If HECI-2 exist call its wake-up handler.
  173. // The handler checks whether HECI-2 is enabled.
  174. //
  175. If (CondRefOf(\_SB.PC00.HEC2.HWAK))
  176. {
  177. \_SB.PC00.HEC2.HWAK()
  178. }
  179. //
  180. // If waking from S3
  181. //
  182. If (LEqual(Arg0, 3)) {
  183. }
  184. Return(Package(){0, 0})
  185. }
  186. Scope(\_SB) {
  187. // Information on CPU and Memory for hotplug SKUs
  188. // #include "CpuMemHp.asi"
  189. OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
  190. Field (IOB2, ByteAcc, NoLock, Preserve) {
  191. SMIC, 8, // SW-SMI ctrl port
  192. SMIS, 8, // SW-SMI status port
  193. }
  194. } // end _SB scope