SioRegs.h 4.9 KB

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  1. /** @file
  2. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _SIO_REG_H_
  6. #define _SIO_REG_H_
  7. #define REG_LOGICAL_DEVICE 0x07
  8. #define ACTIVATE 0x30
  9. #define BASE_ADDRESS_HIGH0 0x60
  10. #define BASE_ADDRESS_LOW0 0x61
  11. #define BASE_ADDRESS_HIGH1 0x62
  12. #define BASE_ADDRESS_LOW1 0x63
  13. #define BASE_ADDRESS_HIGH2 0x64
  14. #define BASE_ADDRESS_LOW2 0x65
  15. #define BASE_ADDRESS_HIGH3 0x66
  16. #define BASE_ADDRESS_LOW3 0x67
  17. #define PRIMARY_INTERRUPT_SELECT 0x70
  18. #define WAKEUP_ON_IRQ_EN 0x70
  19. #define INTERRUPT_TYPE 0x71
  20. #define DMA_CHANNEL_SELECT0 0x74
  21. #define DMA_CHANNEL_SELECT1 0x75
  22. //
  23. //Port address for PILOT - III
  24. //
  25. #define PILOTIII_CHIP_ID 0x03
  26. #define PILOTIII_SIO_INDEX_PORT 0x04E
  27. #define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
  28. #define PILOTIII_UNLOCK 0x5A
  29. #define PILOTIII_LOCK 0xA5
  30. //
  31. // logical device in PILOT-III
  32. //
  33. #define PILOTIII_SIO_PSR 0x00
  34. #define PILOTIII_SIO_COM2 0x01
  35. #define PILOTIII_SIO_COM1 0x02
  36. #define PILOTIII_SIO_SWCP 0x03
  37. #define PILOTIII_SIO_GPIO 0x04
  38. #define PILOTIII_SIO_WDT 0x05
  39. #define PILOTIII_SIO_KCS3 0x08
  40. #define PILOTIII_SIO_KCS4 0x09
  41. #define PILOTIII_SIO_KCS5 0x0A
  42. #define PILOTIII_SIO_BT 0x0B
  43. #define PILOTIII_SIO_SMIC 0x0C
  44. #define PILOTIII_SIO_MAILBOX 0x0D
  45. #define PILOTIII_SIO_RTC 0x0E
  46. #define PILOTIII_SIO_SPI 0x0F
  47. #define PILOTIII_SIO_TAP 0x10
  48. //
  49. // Regisgers for Pilot-III
  50. //
  51. #define PILOTIII_CHIP_ID_REG 0x20
  52. #define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  53. #define PILOTIII_ACTIVATE ACTIVATE
  54. #define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
  55. #define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
  56. #define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
  57. #define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
  58. #define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
  59. //
  60. // Port address for PC8374
  61. //
  62. #define PC8374_SIO_INDEX_PORT 0x02E
  63. #define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
  64. //
  65. // Logical device in PC8374
  66. //
  67. #define PC8374_SIO_FLOPPY 0x00
  68. #define PC8374_SIO_PARA 0x01
  69. #define PC8374_SIO_COM2 0x02
  70. #define PC8374_SIO_COM1 0x03
  71. #define PC8374_SIO_MOUSE 0x05
  72. #define PC8374_SIO_KYBD 0x06
  73. #define PC8374_SIO_GPIO 0x07
  74. //
  75. // Registers specific for PC8374
  76. //
  77. #define PC8374_CLOCK_SELECT 0x2D
  78. #define PC8374_CLOCK_CONFIG 0x29
  79. //
  80. // Registers for PC8374
  81. //
  82. #define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
  83. #define PC8374_ACTIVATE ACTIVATE
  84. #define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
  85. #define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
  86. #define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
  87. #define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
  88. #define PC87427_SERVERIO_CNF2 0x22
  89. //
  90. // Pilot III Mailbox Data Register definitions
  91. //
  92. #define MBDAT00_OFFSET 0x00
  93. #define MBDAT01_OFFSET 0x01
  94. #define MBDAT02_OFFSET 0x02
  95. #define MBDAT03_OFFSET 0x03
  96. #define MBDAT04_OFFSET 0x04
  97. #define MBDAT05_OFFSET 0x05
  98. #define MBDAT06_OFFSET 0x06
  99. #define MBDAT07_OFFSET 0x07
  100. #define MBDAT08_OFFSET 0x08
  101. #define MBDAT09_OFFSET 0x09
  102. #define MBDAT10_OFFSET 0x0A
  103. #define MBDAT11_OFFSET 0x0B
  104. #define MBDAT12_OFFSET 0x0C
  105. #define MBDAT13_OFFSET 0x0D
  106. #define MBDAT14_OFFSET 0x0E
  107. #define MBDAT15_OFFSET 0x0F
  108. #define MBST0_OFFSET 0x10
  109. #define MBST1_OFFSET 0x11
  110. #define MBBINT_OFFSET 0x12
  111. //
  112. // Mailbox Bit definitions...
  113. //
  114. #define MBBINT_MBBIST_BIT 0x80
  115. // If both are there, use the default one
  116. //
  117. #define W83527_EXIST BIT2
  118. #define PC8374_EXIST BIT1
  119. #define PILOTIII_EXIST BIT0
  120. #define DEFAULT_SIO PILOTIII_EXIST
  121. #define DEFAULT_KDB PC8374_EXIST
  122. #define IPMI_DEFAULT_SMM_IO_BASE 0xca2
  123. //
  124. // For Pilot III
  125. //
  126. #define PILOTIII_SWC_BASE_ADDRESS 0xA00
  127. #define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
  128. #define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
  129. #define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
  130. #define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
  131. #define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
  132. #define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
  133. #define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
  134. #define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
  135. #define PILOTIII_MAILBOX_MASK 0xFFE0
  136. #define BMC_KCS_BASE_ADDRESS 0x0CA0
  137. #endif