OpenBoardPkg.fdf 28 KB

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  1. ## @file
  2. # FDF file of Platform.
  3. #
  4. # Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  11. ################################################################################
  12. #
  13. # FD Section
  14. # The [FD] Section is made up of the definition statements and a
  15. # description of what goes into the Flash Device Image. Each FD section
  16. # defines one flash "device" image. A flash device image may be one of
  17. # the following: Removable media bootable image (like a boot floppy
  18. # image,) an Option ROM image (that would be "flashed" into an add-in
  19. # card,) a System "Flash" image (that would be burned into a system's
  20. # flash) or an Update ("Capsule") image that will be used to update and
  21. # existing system flash.
  22. #
  23. ################################################################################
  24. [FD.AspireVn7Dash572G]
  25. #
  26. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  27. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  28. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  29. #
  30. BaseAddress = $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the FLASH Device.
  31. Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize #The size in bytes of the FLASH Device
  32. ErasePolarity = 1
  33. BlockSize = $(FLASH_BLOCK_SIZE)
  34. NumBlocks = $(FLASH_NUM_BLOCKS)
  35. DEFINE SIPKG_DXE_SMM_BIN = INF
  36. DEFINE SIPKG_PEI_BIN = INF
  37. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  38. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  39. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  40. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  41. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  42. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  43. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  44. SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
  45. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  46. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  47. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  48. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  49. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  50. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  51. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  53. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  54. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  55. ################################################################################
  56. #
  57. # Following are lists of FD Region layout which correspond to the locations of different
  58. # images within the flash device.
  59. #
  60. # Regions must be defined in ascending order and may not overlap.
  61. #
  62. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  63. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  64. # "0x" characters. Like:
  65. # Offset|Size
  66. # PcdOffsetCName|PcdSizeCName
  67. # RegionType <FV, DATA, or FILE>
  68. # Fv Size can be adjusted
  69. #
  70. ################################################################################
  71. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  72. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  73. #NV_VARIABLE_STORE
  74. DATA = {
  75. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  76. # ZeroVector []
  77. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  78. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  79. # FileSystemGuid
  80. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  81. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  82. # FvLength: 0x40000
  83. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  84. #Signature "_FVH" #Attributes
  85. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  86. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  87. #
  88. # Be careful on CheckSum field.
  89. #
  90. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  91. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  92. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  93. #Blockmap[1]: End
  94. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  95. ## This is the VARIABLE_STORE_HEADER
  96. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  97. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  98. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  99. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  100. !else
  101. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  102. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  103. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  104. !endif
  105. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  106. # This can speed up the Variable Dispatch a bit.
  107. 0xB8, 0xDF, 0x01, 0x00,
  108. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  109. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  110. }
  111. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  112. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  113. #NV_FTW_WORKING
  114. DATA = {
  115. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  116. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  117. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  118. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  119. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  120. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  121. # WriteQueueSize: UINT64
  122. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  123. }
  124. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  125. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  126. #NV_FTW_SPARE
  127. gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
  128. gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
  129. #DEBUG_MESSAGE_AREA
  130. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  131. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  132. FV = FvAdvanced
  133. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  134. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  135. FV = FvSecurity
  136. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  137. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  138. FV = FvOsBoot
  139. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  140. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  141. FV = FvUefiBoot
  142. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  143. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  144. FV = FvPostMemory
  145. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  146. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  147. #Microcode
  148. FV = FvMicrocode
  149. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  150. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  151. # FSP_S Section
  152. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  153. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  154. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  155. # FSP_M Section
  156. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  157. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  158. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  159. # FSP_T Section
  160. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  161. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  162. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  163. FV = FvAdvancedPreMemory
  164. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  165. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  166. FV = FvPreMemory
  167. ################################################################################
  168. #
  169. # FV Section
  170. #
  171. # [FV] section is used to define what components or modules are placed within a flash
  172. # device file. This section also defines order the components and modules are positioned
  173. # within the image. The [FV] section consists of define statements, set statements and
  174. # module statements.
  175. #
  176. ################################################################################
  177. [FV.FvMicrocode]
  178. BlockSize = $(FLASH_BLOCK_SIZE)
  179. FvAlignment = 16
  180. ERASE_POLARITY = 1
  181. MEMORY_MAPPED = TRUE
  182. STICKY_WRITE = TRUE
  183. LOCK_CAP = TRUE
  184. LOCK_STATUS = FALSE
  185. WRITE_DISABLED_CAP = TRUE
  186. WRITE_ENABLED_CAP = TRUE
  187. WRITE_STATUS = TRUE
  188. WRITE_LOCK_CAP = TRUE
  189. WRITE_LOCK_STATUS = TRUE
  190. READ_DISABLED_CAP = TRUE
  191. READ_ENABLED_CAP = TRUE
  192. READ_STATUS = FALSE
  193. READ_LOCK_CAP = TRUE
  194. READ_LOCK_STATUS = TRUE
  195. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
  196. [FV.FvPreMemory]
  197. BlockSize = $(FLASH_BLOCK_SIZE)
  198. FvAlignment = 16
  199. ERASE_POLARITY = 1
  200. MEMORY_MAPPED = TRUE
  201. STICKY_WRITE = TRUE
  202. LOCK_CAP = TRUE
  203. LOCK_STATUS = TRUE
  204. WRITE_DISABLED_CAP = TRUE
  205. WRITE_ENABLED_CAP = TRUE
  206. WRITE_STATUS = TRUE
  207. WRITE_LOCK_CAP = TRUE
  208. WRITE_LOCK_STATUS = TRUE
  209. READ_DISABLED_CAP = TRUE
  210. READ_ENABLED_CAP = TRUE
  211. READ_STATUS = TRUE
  212. READ_LOCK_CAP = TRUE
  213. READ_LOCK_STATUS = TRUE
  214. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  215. INF UefiCpuPkg/SecCore/SecCore.inf
  216. !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
  217. #
  218. # PeiMain is needed only for FSP API mode or EDK2 build,
  219. # in FSP dispatch mode the one inside FSP Binary is launched
  220. # unless requested otherwise (PcdFspDispatchModeUseFspPeiMain == FALSE).
  221. #
  222. INF MdeModulePkg/Core/Pei/PeiMain.inf
  223. !endif
  224. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  225. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  226. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  227. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  228. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  229. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  230. [FV.FvPostMemoryUncompact]
  231. BlockSize = $(FLASH_BLOCK_SIZE)
  232. FvAlignment = 16
  233. ERASE_POLARITY = 1
  234. MEMORY_MAPPED = TRUE
  235. STICKY_WRITE = TRUE
  236. LOCK_CAP = TRUE
  237. LOCK_STATUS = TRUE
  238. WRITE_DISABLED_CAP = TRUE
  239. WRITE_ENABLED_CAP = TRUE
  240. WRITE_STATUS = TRUE
  241. WRITE_LOCK_CAP = TRUE
  242. WRITE_LOCK_STATUS = TRUE
  243. READ_DISABLED_CAP = TRUE
  244. READ_ENABLED_CAP = TRUE
  245. READ_STATUS = TRUE
  246. READ_LOCK_CAP = TRUE
  247. READ_LOCK_STATUS = TRUE
  248. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  249. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  250. # Init Board Config PCD
  251. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  252. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  253. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  254. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  255. FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
  256. SECTION RAW = $(BOARD)/Vbt.bin
  257. SECTION UI = "Vbt"
  258. }
  259. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  260. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  261. }
  262. !endif # PcdPeiDisplayEnable
  263. [FV.FvPostMemory]
  264. BlockSize = $(FLASH_BLOCK_SIZE)
  265. FvAlignment = 16
  266. ERASE_POLARITY = 1
  267. MEMORY_MAPPED = TRUE
  268. STICKY_WRITE = TRUE
  269. LOCK_CAP = TRUE
  270. LOCK_STATUS = TRUE
  271. WRITE_DISABLED_CAP = TRUE
  272. WRITE_ENABLED_CAP = TRUE
  273. WRITE_STATUS = TRUE
  274. WRITE_LOCK_CAP = TRUE
  275. WRITE_LOCK_STATUS = TRUE
  276. READ_DISABLED_CAP = TRUE
  277. READ_ENABLED_CAP = TRUE
  278. READ_STATUS = TRUE
  279. READ_LOCK_CAP = TRUE
  280. READ_LOCK_STATUS = TRUE
  281. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  282. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  283. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  284. SECTION FV_IMAGE = FvPostMemoryUncompact
  285. }
  286. }
  287. [FV.FvUefiBootUncompact]
  288. BlockSize = $(FLASH_BLOCK_SIZE)
  289. FvAlignment = 16
  290. ERASE_POLARITY = 1
  291. MEMORY_MAPPED = TRUE
  292. STICKY_WRITE = TRUE
  293. LOCK_CAP = TRUE
  294. LOCK_STATUS = TRUE
  295. WRITE_DISABLED_CAP = TRUE
  296. WRITE_ENABLED_CAP = TRUE
  297. WRITE_STATUS = TRUE
  298. WRITE_LOCK_CAP = TRUE
  299. WRITE_LOCK_STATUS = TRUE
  300. READ_DISABLED_CAP = TRUE
  301. READ_ENABLED_CAP = TRUE
  302. READ_STATUS = TRUE
  303. READ_LOCK_CAP = TRUE
  304. READ_LOCK_STATUS = TRUE
  305. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  306. # NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
  307. APRIORI DXE {
  308. INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
  309. INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
  310. INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
  311. }
  312. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  313. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  314. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  315. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  316. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  317. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  318. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  319. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  320. INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
  321. INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
  322. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  323. INF ShellPkg/Application/Shell/Shell.inf
  324. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  325. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  326. #
  327. # Below module is used by FSP API mode
  328. #
  329. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  330. !endif
  331. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  332. [FV.FvUefiBoot]
  333. BlockSize = $(FLASH_BLOCK_SIZE)
  334. FvAlignment = 16
  335. ERASE_POLARITY = 1
  336. MEMORY_MAPPED = TRUE
  337. STICKY_WRITE = TRUE
  338. LOCK_CAP = TRUE
  339. LOCK_STATUS = TRUE
  340. WRITE_DISABLED_CAP = TRUE
  341. WRITE_ENABLED_CAP = TRUE
  342. WRITE_STATUS = TRUE
  343. WRITE_LOCK_CAP = TRUE
  344. WRITE_LOCK_STATUS = TRUE
  345. READ_DISABLED_CAP = TRUE
  346. READ_ENABLED_CAP = TRUE
  347. READ_STATUS = TRUE
  348. READ_LOCK_CAP = TRUE
  349. READ_LOCK_STATUS = TRUE
  350. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  351. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  352. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  353. SECTION FV_IMAGE = FvUefiBootUncompact
  354. }
  355. }
  356. [FV.FvOsBootUncompact]
  357. BlockSize = $(FLASH_BLOCK_SIZE)
  358. FvAlignment = 16
  359. ERASE_POLARITY = 1
  360. MEMORY_MAPPED = TRUE
  361. STICKY_WRITE = TRUE
  362. LOCK_CAP = TRUE
  363. LOCK_STATUS = TRUE
  364. WRITE_DISABLED_CAP = TRUE
  365. WRITE_ENABLED_CAP = TRUE
  366. WRITE_STATUS = TRUE
  367. WRITE_LOCK_CAP = TRUE
  368. WRITE_LOCK_STATUS = TRUE
  369. READ_DISABLED_CAP = TRUE
  370. READ_ENABLED_CAP = TRUE
  371. READ_STATUS = TRUE
  372. READ_LOCK_CAP = TRUE
  373. READ_LOCK_STATUS = TRUE
  374. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  375. # NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
  376. APRIORI DXE {
  377. INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
  378. INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
  379. }
  380. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  381. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  382. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  383. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  384. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  385. INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  386. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  387. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  388. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  389. INF RuleOverride = ACPITABLE $(PROJECT)/Acpi/BoardAcpiTables.inf
  390. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  391. !endif
  392. [FV.FvLateSilicon]
  393. BlockSize = $(FLASH_BLOCK_SIZE)
  394. FvAlignment = 16
  395. ERASE_POLARITY = 1
  396. MEMORY_MAPPED = TRUE
  397. STICKY_WRITE = TRUE
  398. LOCK_CAP = TRUE
  399. LOCK_STATUS = TRUE
  400. WRITE_DISABLED_CAP = TRUE
  401. WRITE_ENABLED_CAP = TRUE
  402. WRITE_STATUS = TRUE
  403. WRITE_LOCK_CAP = TRUE
  404. WRITE_LOCK_STATUS = TRUE
  405. READ_DISABLED_CAP = TRUE
  406. READ_ENABLED_CAP = TRUE
  407. READ_STATUS = TRUE
  408. READ_LOCK_CAP = TRUE
  409. READ_LOCK_STATUS = TRUE
  410. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  411. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  412. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
  413. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  414. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  415. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  416. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  417. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  418. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  419. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  420. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  421. !endif
  422. [FV.FvOsBoot]
  423. BlockSize = $(FLASH_BLOCK_SIZE)
  424. FvAlignment = 16
  425. ERASE_POLARITY = 1
  426. MEMORY_MAPPED = TRUE
  427. STICKY_WRITE = TRUE
  428. LOCK_CAP = TRUE
  429. LOCK_STATUS = TRUE
  430. WRITE_DISABLED_CAP = TRUE
  431. WRITE_ENABLED_CAP = TRUE
  432. WRITE_STATUS = TRUE
  433. WRITE_LOCK_CAP = TRUE
  434. WRITE_LOCK_STATUS = TRUE
  435. READ_DISABLED_CAP = TRUE
  436. READ_ENABLED_CAP = TRUE
  437. READ_STATUS = TRUE
  438. READ_LOCK_CAP = TRUE
  439. READ_LOCK_STATUS = TRUE
  440. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  441. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  442. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  443. SECTION FV_IMAGE = FvOsBootUncompact
  444. }
  445. }
  446. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  447. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  448. SECTION FV_IMAGE = FvLateSilicon
  449. }
  450. }
  451. [FV.FvSecurityPreMemory]
  452. BlockSize = $(FLASH_BLOCK_SIZE)
  453. FvAlignment = 16 #FV alignment and FV attributes setting.
  454. ERASE_POLARITY = 1
  455. MEMORY_MAPPED = TRUE
  456. STICKY_WRITE = TRUE
  457. LOCK_CAP = TRUE
  458. LOCK_STATUS = TRUE
  459. WRITE_DISABLED_CAP = TRUE
  460. WRITE_ENABLED_CAP = TRUE
  461. WRITE_STATUS = TRUE
  462. WRITE_LOCK_CAP = TRUE
  463. WRITE_LOCK_STATUS = TRUE
  464. READ_DISABLED_CAP = TRUE
  465. READ_ENABLED_CAP = TRUE
  466. READ_STATUS = TRUE
  467. READ_LOCK_CAP = TRUE
  468. READ_LOCK_STATUS = TRUE
  469. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  470. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  471. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  472. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  473. [FV.FvSecurityPostMemory]
  474. BlockSize = $(FLASH_BLOCK_SIZE)
  475. FvAlignment = 16 #FV alignment and FV attributes setting.
  476. ERASE_POLARITY = 1
  477. MEMORY_MAPPED = TRUE
  478. STICKY_WRITE = TRUE
  479. LOCK_CAP = TRUE
  480. LOCK_STATUS = TRUE
  481. WRITE_DISABLED_CAP = TRUE
  482. WRITE_ENABLED_CAP = TRUE
  483. WRITE_STATUS = TRUE
  484. WRITE_LOCK_CAP = TRUE
  485. WRITE_LOCK_STATUS = TRUE
  486. READ_DISABLED_CAP = TRUE
  487. READ_ENABLED_CAP = TRUE
  488. READ_STATUS = TRUE
  489. READ_LOCK_CAP = TRUE
  490. READ_LOCK_STATUS = TRUE
  491. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  492. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  493. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  494. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  495. !endif
  496. [FV.FvSecurityLate]
  497. BlockSize = $(FLASH_BLOCK_SIZE)
  498. FvAlignment = 16
  499. ERASE_POLARITY = 1
  500. MEMORY_MAPPED = TRUE
  501. STICKY_WRITE = TRUE
  502. LOCK_CAP = TRUE
  503. LOCK_STATUS = TRUE
  504. WRITE_DISABLED_CAP = TRUE
  505. WRITE_ENABLED_CAP = TRUE
  506. WRITE_STATUS = TRUE
  507. WRITE_LOCK_CAP = TRUE
  508. WRITE_LOCK_STATUS = TRUE
  509. READ_DISABLED_CAP = TRUE
  510. READ_ENABLED_CAP = TRUE
  511. READ_STATUS = TRUE
  512. READ_LOCK_CAP = TRUE
  513. READ_LOCK_STATUS = TRUE
  514. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  515. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  516. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  517. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  518. INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
  519. !endif
  520. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  521. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  522. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  523. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  524. !endif
  525. !endif
  526. [FV.FvSecurity]
  527. BlockSize = $(FLASH_BLOCK_SIZE)
  528. FvAlignment = 16
  529. ERASE_POLARITY = 1
  530. MEMORY_MAPPED = TRUE
  531. STICKY_WRITE = TRUE
  532. LOCK_CAP = TRUE
  533. LOCK_STATUS = TRUE
  534. WRITE_DISABLED_CAP = TRUE
  535. WRITE_ENABLED_CAP = TRUE
  536. WRITE_STATUS = TRUE
  537. WRITE_LOCK_CAP = TRUE
  538. WRITE_LOCK_STATUS = TRUE
  539. READ_DISABLED_CAP = TRUE
  540. READ_ENABLED_CAP = TRUE
  541. READ_STATUS = TRUE
  542. READ_LOCK_CAP = TRUE
  543. READ_LOCK_STATUS = TRUE
  544. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  545. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  546. SECTION FV_IMAGE = FvSecurityPreMemory
  547. }
  548. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  549. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  550. SECTION FV_IMAGE = FvSecurityPostMemory
  551. }
  552. }
  553. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  554. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  555. SECTION FV_IMAGE = FvSecurityLate
  556. }
  557. }
  558. #
  559. # Pre-memory Advanced Features
  560. #
  561. [FV.FvAdvancedPreMemory]
  562. FvAlignment = 16
  563. ERASE_POLARITY = 1
  564. MEMORY_MAPPED = TRUE
  565. STICKY_WRITE = TRUE
  566. LOCK_CAP = TRUE
  567. LOCK_STATUS = TRUE
  568. WRITE_DISABLED_CAP = TRUE
  569. WRITE_ENABLED_CAP = TRUE
  570. WRITE_STATUS = TRUE
  571. WRITE_LOCK_CAP = TRUE
  572. WRITE_LOCK_STATUS = TRUE
  573. READ_DISABLED_CAP = TRUE
  574. READ_ENABLED_CAP = TRUE
  575. READ_STATUS = TRUE
  576. READ_LOCK_CAP = TRUE
  577. READ_LOCK_STATUS = TRUE
  578. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  579. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  580. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  581. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  582. !endif
  583. #
  584. # Post-Memory Advanced Features
  585. #
  586. [FV.FvAdvancedUncompact]
  587. FvAlignment = 16
  588. ERASE_POLARITY = 1
  589. MEMORY_MAPPED = TRUE
  590. STICKY_WRITE = TRUE
  591. LOCK_CAP = TRUE
  592. LOCK_STATUS = TRUE
  593. WRITE_DISABLED_CAP = TRUE
  594. WRITE_ENABLED_CAP = TRUE
  595. WRITE_STATUS = TRUE
  596. WRITE_LOCK_CAP = TRUE
  597. WRITE_LOCK_STATUS = TRUE
  598. READ_DISABLED_CAP = TRUE
  599. READ_ENABLED_CAP = TRUE
  600. READ_STATUS = TRUE
  601. READ_LOCK_CAP = TRUE
  602. READ_LOCK_STATUS = TRUE
  603. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  604. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  605. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  606. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  607. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  608. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  609. !endif
  610. #
  611. # Compressed FV with Post-Memory Advanced Features
  612. #
  613. [FV.FvAdvanced]
  614. BlockSize = $(FLASH_BLOCK_SIZE)
  615. FvAlignment = 16
  616. ERASE_POLARITY = 1
  617. MEMORY_MAPPED = TRUE
  618. STICKY_WRITE = TRUE
  619. LOCK_CAP = TRUE
  620. LOCK_STATUS = TRUE
  621. WRITE_DISABLED_CAP = TRUE
  622. WRITE_ENABLED_CAP = TRUE
  623. WRITE_STATUS = TRUE
  624. WRITE_LOCK_CAP = TRUE
  625. WRITE_LOCK_STATUS = TRUE
  626. READ_DISABLED_CAP = TRUE
  627. READ_ENABLED_CAP = TRUE
  628. READ_STATUS = TRUE
  629. READ_LOCK_CAP = TRUE
  630. READ_LOCK_STATUS = TRUE
  631. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  632. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  633. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  634. SECTION FV_IMAGE = FvAdvancedUncompact
  635. }
  636. }
  637. ################################################################################
  638. #
  639. # Rules are use with the [FV] section's module INF type to define
  640. # how an FFS file is created for a given INF file. The following Rule are the default
  641. # rules for the different module type. User can add the customized rules to define the
  642. # content of the FFS file.
  643. #
  644. ################################################################################
  645. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf