PeiAspireVn7Dash572GInitPostMemLib.c 4.0 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <Library/BoardEcLib.h>
  7. #include <Library/DebugLib.h>
  8. #include <Library/EcLib.h>
  9. #include <Library/GpioLib.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/PcdLib.h>
  12. #include <Library/PchCycleDecodingLib.h>
  13. #include <Library/PciLib.h>
  14. #include <Library/PeiServicesLib.h>
  15. #include <Library/SiliconInitLib.h>
  16. #include <PchAccess.h>
  17. #include <GpioPinsSklLp.h>
  18. #include "PeiAspireVn7Dash572GInitLib.h"
  19. /**
  20. Init from vendor's PeiOemModule. KbcPeim does not appear to be used
  21. (It implements commands also found in RtKbcDriver and SmmKbcDriver).
  22. Mostly, this puts the system back to sleep if the lid is closed during
  23. an S3 resume.
  24. **/
  25. VOID
  26. EcInit (
  27. VOID
  28. )
  29. {
  30. EFI_BOOT_MODE BootMode;
  31. UINT8 PowerRegister;
  32. UINT8 OutData;
  33. UINT16 ABase;
  34. UINT16 Pm1Sts;
  35. UINT32 GpeSts;
  36. /* This is called via a "$FNC" in a PeiOemModule pointer table, with "$DPX" on SiInit */
  37. IoWrite8 (0x6C, 0x5A); // 6Ch is the EC sideband port
  38. PeiServicesGetBootMode (&BootMode);
  39. if (BootMode == BOOT_ON_S3_RESUME) {
  40. /* "MLID" in LGMR-based memory map is equivalent to "ELID" in EC-based
  41. * memory map. Vendor firmware accesses through LGMR; remapped
  42. * - EcCmd* function calls will not remapped */
  43. EcRead (0x70, &PowerRegister);
  44. if (!(PowerRegister & BIT1)) { // Lid is closed
  45. EcCmd90Read (0x0A, &OutData);
  46. if (!(OutData & BIT1)) {
  47. EcCmd91Write (0x0A, OutData | BIT1);
  48. }
  49. /* Clear events and go back to sleep */
  50. PchAcpiBaseGet (&ABase);
  51. /* Clear ABase PM1_STS - RW/1C set bits */
  52. Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
  53. IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
  54. /* Clear ABase GPE0_STS[127:96] - RW/1C set bits */
  55. GpeSts = IoRead32 (ABase + R_PCH_ACPI_GPE0_STS_127_96);
  56. IoWrite32 (ABase + R_PCH_ACPI_GPE0_STS_127_96, GpeSts);
  57. /* Clear xHCI PM_CS[PME_Status] - RW/1C - and disable xHCI PM_CS[PME_En] */
  58. PciAndThenOr16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_PCH_XHCI, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI, R_PCH_XHCI_PWR_CNTL_STS),
  59. (UINT16) ~B_PCH_XHCI_PWR_CNTL_STS_PME_EN,
  60. B_PCH_XHCI_PWR_CNTL_STS_PME_STS
  61. );
  62. /* Enter S3 sleep */
  63. IoAndThenOr32 (ABase + R_PCH_ACPI_PM1_CNT,
  64. (UINT32) ~(B_PCH_ACPI_PM1_CNT_SLP_TYP | B_PCH_ACPI_PM1_CNT_SLP_EN),
  65. V_PCH_ACPI_PM1_CNT_S3
  66. );
  67. IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, B_PCH_ACPI_PM1_CNT_SLP_EN);
  68. CpuDeadLoop ();
  69. }
  70. }
  71. }
  72. /**
  73. Aspire VN7-572G board configuration init function for PEI post memory phase.
  74. **/
  75. VOID
  76. AspireVn7Dash572GInit (
  77. VOID
  78. )
  79. {
  80. PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc255AspireVn7Dash572G);
  81. PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINTN) &HdaVerbTableDisplayAudio);
  82. }
  83. /**
  84. Configures GPIO
  85. **/
  86. EFI_STATUS
  87. EFIAPI
  88. GpioInitPostMem (
  89. VOID
  90. )
  91. {
  92. EFI_STATUS Status;
  93. DEBUG ((DEBUG_INFO, "GpioInitPostMem() Start\n"));
  94. Status = GpioConfigurePads (mGpioTableAspireVn7Dash572GSize, mGpioTableAspireVn7Dash572G);
  95. if (EFI_ERROR (Status)) {
  96. DEBUG ((DEBUG_ERROR, "Failed to configure early GPIOs!\n"));
  97. return EFI_DEVICE_ERROR;
  98. }
  99. DEBUG ((DEBUG_INFO, "GpioInitPostMem() End\n"));
  100. return EFI_SUCCESS;
  101. }
  102. /**
  103. Configure GPIO and SIO
  104. @retval EFI_SUCCESS Operation success.
  105. **/
  106. EFI_STATUS
  107. EFIAPI
  108. AspireVn7Dash572GBoardInitBeforeSiliconInit (
  109. VOID
  110. )
  111. {
  112. GpioInitPostMem ();
  113. AspireVn7Dash572GInit ();
  114. ///
  115. /// Do Late PCH init
  116. ///
  117. LateSiliconInit ();
  118. return EFI_SUCCESS;
  119. }
  120. /**
  121. Notify EC
  122. @retval EFI_SUCCESS Operation success.
  123. **/
  124. EFI_STATUS
  125. EFIAPI
  126. AspireVn7Dash572GBoardInitAfterSiliconInit (
  127. VOID
  128. )
  129. {
  130. EcInit ();
  131. return EFI_SUCCESS;
  132. }