OpenBoardPkgPcd.dsc 16 KB

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  1. ## @file
  2. # PCD configuration build description file for the CometlakeURvp board.
  3. #
  4. # Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. ################################################################################
  10. #
  11. # Pcd Section - list of all PCD Entries used by this board.
  12. #
  13. ################################################################################
  14. [PcdsFixedAtBuild.common]
  15. ######################################
  16. # Key Boot Stage and FSP configuration
  17. ######################################
  18. #
  19. # Please select the Boot Stage here.
  20. # Stage 1 - enable debug (system deadloop after debug init)
  21. # Stage 2 - mem init (system deadloop after mem init)
  22. # Stage 3 - boot to shell only
  23. # Stage 4 - boot to OS
  24. # Stage 5 - boot to OS with security boot enabled
  25. # Stage 6 - boot with advanced features enabled
  26. #
  27. gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
  28. #
  29. # 0: FSP Wrapper is running in Dispatch mode.
  30. # 1: FSP Wrapper is running in API mode.
  31. # Note: Dispatch mode is currently NOT supported for this board.
  32. #
  33. gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
  34. #
  35. # FALSE: The board is not a FSP wrapper (FSP binary not used)
  36. # TRUE: The board is a FSP wrapper (FSP binary is used)
  37. #
  38. gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
  39. #
  40. # FSP Base address PCD will be updated in FDF basing on flash map.
  41. #
  42. gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
  43. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
  44. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
  45. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  46. gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
  47. gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  48. gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
  49. #
  50. # When sharing stack with boot loader, FSP only needs a small temp ram for heap
  51. #
  52. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
  53. #
  54. # Boot loader stack size has to be large enough for FSP execution
  55. #
  56. gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
  57. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
  58. gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
  59. gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
  60. #
  61. # PCIe Reserved Memory Space Range
  62. #
  63. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0xA0000000
  64. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF
  65. [PcdsFeatureFlag.common]
  66. ######################################
  67. # Edk2 Configuration
  68. ######################################
  69. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
  70. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
  71. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
  72. gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
  73. ######################################
  74. # Silicon Configuration
  75. ######################################
  76. # Build switches
  77. gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
  78. # CPU
  79. gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
  80. gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
  81. # SA
  82. gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
  83. gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
  84. gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
  85. gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
  86. gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
  87. gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
  88. gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
  89. gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
  90. gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
  91. # ME
  92. gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
  93. gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
  94. gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
  95. # Others
  96. gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
  97. gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
  98. gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
  99. gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
  100. gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
  101. gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
  102. gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
  103. gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
  104. gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
  105. gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
  106. gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
  107. gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
  108. gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
  109. gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
  110. gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.
  111. ######################################
  112. # Platform Configuration
  113. ######################################
  114. #
  115. # MinPlatform common include for required feature PCD
  116. # These PCD must be set before the core include files, CoreCommonLib,
  117. # CorePeiLib, and CoreDxeLib.
  118. # Optional MinPlatformPkg features should be enabled after this
  119. #
  120. !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc
  121. #
  122. # Commonly used MinPlatform feature configuration logic that maps functionity to stage
  123. #
  124. !include BoardModulePkg/Include/Dsc/CommonStageConfig.dsc.inc
  125. ######################################
  126. # Board Configuration
  127. ######################################
  128. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
  129. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
  130. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
  131. [PcdsFixedAtBuild.common]
  132. ######################################
  133. # Edk2 Configuration
  134. ######################################
  135. !if $(TARGET) == RELEASE
  136. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
  137. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
  138. !else
  139. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
  140. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
  141. !endif
  142. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  143. gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
  144. !endif
  145. gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
  146. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
  147. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
  148. gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
  149. gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
  150. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
  151. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  152. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
  153. !endif
  154. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
  155. gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
  156. gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
  157. !if $(TARGET) == DEBUG
  158. gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
  159. !endif
  160. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
  161. !if $(TARGET) == RELEASE
  162. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
  163. !else
  164. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
  165. !endif
  166. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
  167. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
  168. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
  169. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
  170. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
  171. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
  172. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
  173. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
  174. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
  175. # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
  176. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
  177. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
  178. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
  179. #
  180. # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
  181. # (They will be DynamicEx in FSP Dispatch mode)
  182. #
  183. ## Specifies the size of the microcode Region.
  184. # @Prompt Microcode Region size.
  185. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
  186. ## Specifies the AP wait loop state during POST phase.
  187. # The value is defined as below.
  188. # 1: Place AP in the Hlt-Loop state.
  189. # 2: Place AP in the Mwait-Loop state.
  190. # 3: Place AP in the Run-Loop state.
  191. # @Prompt The AP wait loop state.
  192. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
  193. ######################################
  194. # Silicon Configuration
  195. ######################################
  196. gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  197. ######################################
  198. # Platform Configuration
  199. ######################################
  200. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
  201. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
  202. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
  203. #
  204. # Set the location of the DUTY_CYCLE field in the P_CNT register
  205. # and indicate the width of the clock duty cycle to OS power management
  206. #
  207. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
  208. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
  209. #
  210. # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
  211. #
  212. # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
  213. # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
  214. # that lie entirely within the expected fixed memory regions.
  215. # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
  216. # BIT3-31: Reserved
  217. #
  218. gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
  219. !if $(TARGET) == RELEASE
  220. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
  221. !else
  222. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
  223. !endif
  224. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
  225. !if $(TARGET) == RELEASE
  226. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
  227. !else
  228. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
  229. !endif
  230. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
  231. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  232. !endif
  233. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
  234. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  235. !endif
  236. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
  237. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  238. !endif
  239. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
  240. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  241. !endif
  242. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
  243. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  244. !endif
  245. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
  246. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  247. !endif
  248. ######################################
  249. # Board Configuration
  250. ######################################
  251. gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1
  252. gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00}
  253. [PcdsFixedAtBuild.IA32]
  254. ######################################
  255. # Edk2 Configuration
  256. ######################################
  257. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
  258. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
  259. gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
  260. ######################################
  261. # Platform Configuration
  262. ######################################
  263. gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
  264. [PcdsFixedAtBuild.X64]
  265. ######################################
  266. # Edk2 Configuration
  267. ######################################
  268. # Default platform supported RFC 4646 languages: (American) English
  269. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
  270. [PcdsPatchableInModule.common]
  271. ######################################
  272. # Edk2 Configuration
  273. ######################################
  274. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
  275. gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
  276. ######################################
  277. # Silicon Configuration
  278. ######################################
  279. !if $(TARGET) == DEBUG
  280. gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
  281. !endif
  282. [PcdsDynamicDefault]
  283. ######################################
  284. # Edk2 Configuration
  285. ######################################
  286. gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
  287. gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
  288. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
  289. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
  290. gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  291. #
  292. # Set video to native resolution as Windows 8 WHCK requirement.
  293. #
  294. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
  295. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
  296. gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
  297. #
  298. # FSP Base address PCD will be updated in FDF basing on flash map.
  299. #
  300. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
  301. # Platform will pre-allocate UPD buffer and pass it to FspWrapper
  302. # Those dummy address will be patched before FspWrapper executing
  303. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
  304. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
  305. gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
  306. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
  307. ######################################
  308. # Board Configuration
  309. ######################################
  310. # Thunderbolt Configuration
  311. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
  312. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
  313. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
  314. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
  315. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
  316. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
  317. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
  318. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
  319. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
  320. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
  321. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
  322. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
  323. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
  324. gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
  325. [PcdsDynamicHii.X64.DEFAULT]
  326. ######################################
  327. # Edk2 Configuration
  328. ######################################
  329. gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
  330. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  331. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
  332. !else
  333. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
  334. !endif