PCI-S1.asi 56 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051
  1. /** @file
  2. Copyright (c) 2023, Ampere Computing LLC. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. //
  6. // S1 Start here
  7. //
  8. // PCIE6 S1 RCA2
  9. Device (PCIA) {
  10. //
  11. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  12. // Section 6.1.5
  13. //
  14. Name (_HID,"PNP0A08")
  15. Name (_CCA, ONE)
  16. Method (_STA, 0, NotSerialized) {
  17. Return (0xF)
  18. }
  19. //
  20. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  21. // root complex for use with pre-PCIe operating systems.
  22. // Section 6.1.2
  23. //
  24. Name (_CID,"PNP0A03")
  25. //
  26. // Declare the segment number of this root complex. Most systems only
  27. // have one segment, which is numbered 0.
  28. // Section 6.5.6
  29. //
  30. Name (_SEG, 6)
  31. //
  32. // Declare the base bus number, which is the bus number of the root
  33. // bus in this root complex. This is usually 0, but need not be.
  34. // For root complexes supporting multiple root busses, this should
  35. // be the lowest numbered root bus.
  36. // Section 6.5.5
  37. //
  38. Name (_BBN, 0)
  39. //
  40. // The _UID value provides a way of uniquely identifying a device
  41. // in the case where more than one instance of a specific device
  42. // is implemented with the same _HID/_CID. For systems with a
  43. // single root complex, this is usually just 0. For systems with
  44. // multiple root complexes, this should be different for each
  45. // root complex.
  46. // Section 6.1.12
  47. //
  48. Name (_UID, "PCIA")
  49. Name (_STR, Unicode("PCIe 10 Device"))
  50. //
  51. // Declare the PCI Routing Table.
  52. // This defines SPI mappings of the four line-based interrupts
  53. // associated with the root complex and hierarchy below it.
  54. // Section 6.2.12
  55. //
  56. Name (_PRT, Package() {
  57. //
  58. // Routing for device 0, all functions.
  59. // Note: ARM doesn't support LNK nodes, so the third param
  60. // is 0 and the fourth param is the SPI number of the interrupt
  61. // line. In this example, the A/B/C/D interrupts are wired to
  62. // SPI lines 136/137/138/139 + 320 respectively. PCIA RCA2
  63. //
  64. Package() {0x0001FFFF, 0, 0, 456},
  65. Package() {0x0001FFFF, 1, 0, 457},
  66. Package() {0x0001FFFF, 2, 0, 458},
  67. Package() {0x0001FFFF, 3, 0, 459},
  68. Package() {0x0002FFFF, 0, 0, 456},
  69. Package() {0x0002FFFF, 1, 0, 457},
  70. Package() {0x0002FFFF, 2, 0, 458},
  71. Package() {0x0002FFFF, 3, 0, 459},
  72. Package() {0x0003FFFF, 0, 0, 456},
  73. Package() {0x0003FFFF, 1, 0, 457},
  74. Package() {0x0003FFFF, 2, 0, 458},
  75. Package() {0x0003FFFF, 3, 0, 459},
  76. Package() {0x0004FFFF, 0, 0, 456},
  77. Package() {0x0004FFFF, 1, 0, 457},
  78. Package() {0x0004FFFF, 2, 0, 458},
  79. Package() {0x0004FFFF, 3, 0, 459},
  80. })
  81. //
  82. // Declare the resources assigned to this root complex.
  83. // Section 6.2.2
  84. //
  85. Method (_CBA, 0, Serialized) {
  86. Return (0x7BFFF0000000)
  87. }
  88. Name (RBUF, ResourceTemplate () {
  89. //
  90. // Declare the range of bus numbers assigned to this root
  91. // complex. In this example, the minimum bus number will be
  92. // 0, the maximum bus number will be 0xFF, supporting
  93. // 256 busses total.
  94. // Section 19.5.141
  95. //
  96. WordBusNumber (
  97. ResourceProducer,
  98. MinFixed, // IsMinFixed
  99. MaxFixed, // IsMaxFixed
  100. PosDecode, // Decode
  101. 0, // AddressGranularity
  102. 0, // AddressMinimum - Minimum Bus Number
  103. 255, // AddressMaximum - Maximum Bus Number
  104. 0, // AddressTranslation - Set to 0
  105. 256) // RangeLength - Number of Busses
  106. //
  107. // Declare the memory range to be used for BAR memory
  108. // windows. This declares a 4GB region starting at
  109. // 0x4000000000.
  110. // Section 19.5.80
  111. //
  112. // Memory32Fixed (ReadWrite, 0x1FF80000, 0x10000, )
  113. QWordMemory (
  114. ResourceProducer, // ResourceUsage
  115. PosDecode, // Decode
  116. MinFixed, // IsMinFixed
  117. MaxFixed, // IsMaxFixed
  118. NonCacheable, // NonCacheable
  119. ReadWrite, // ReadAndWrite
  120. 0x0000000000000000, // AddressGranularity - GRA
  121. 0x0000000070000000, // AddressMinimum - MIN
  122. 0x0000000077FFFFFF, // AddressMinimum - MAX
  123. 0x0000000000000000, // AddressTranslation - TRA
  124. 0x0000000008000000 // RangeLength - LEN
  125. )
  126. QWordMemory (
  127. ResourceProducer, // ResourceUsage
  128. PosDecode, // Decode
  129. MinFixed, // IsMinFixed
  130. MaxFixed, // IsMaxFixed
  131. NonCacheable, // NonCacheable
  132. ReadWrite, // ReadAndWrite
  133. 0x0000000000000000, // AddressGranularity - GRA
  134. 0x0000780000000000, // AddressMinimum - MIN
  135. 0x00007BFFDFFFFFFF, // AddressMaximum - MAX
  136. 0x0000000000000000, // AddressTranslation - TRA
  137. 0x000003FFE0000000 // RangeLength - LEN
  138. )
  139. })
  140. Method (_CRS, 0, Serialized) {
  141. Return (RBUF)
  142. }
  143. //
  144. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  145. //
  146. // Argments:
  147. // Arg0 A Buffer containing a UUID
  148. // Arg1 An Integer containing a Revision ID of the buffer format
  149. // Arg2 An Integer containing a count of entries in Arg3
  150. // Arg3 A Buffer containing a list of DWORD capabilities
  151. // Return Value:
  152. // A Buffer containing a list of capabilities
  153. // See the APCI spec, Section 6.2.10,
  154. // and the PCI FW spec, Section 4.5.
  155. //
  156. // The following is an example, and may need modification for
  157. // specific implementations.
  158. //
  159. Name (SUPP,0) // PCI _OSC Support Field value
  160. Name (CTRL,0) // PCI _OSC Control Field value
  161. Method (_OSC, 4) {
  162. //
  163. // Look for the PCI Host Bridge Interface UUID.
  164. // Section 6.2.10.3
  165. //
  166. //
  167. // Create DWord-adressable fields from the Capabilities Buffer
  168. // Create CDW1 outside the test as it's used in the else clause.
  169. //
  170. CreateDWordField (Arg3,0,CDW1)
  171. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  172. CreateDWordField (Arg3,4,CDW2)
  173. CreateDWordField (Arg3,8,CDW3)
  174. //
  175. // Save Capabilities DWord 2 & 3
  176. //
  177. Store (CDW2,SUPP)
  178. Store (CDW3,CTRL)
  179. //
  180. // Only allow native hot plug control if OS supports:
  181. // ASPM
  182. // Clock PM
  183. // MSI/MSI-X
  184. //
  185. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  186. //
  187. // Mask bit 0 (and undefined bits)
  188. //
  189. And (CTRL,0x1E,CTRL)
  190. }
  191. //
  192. // Never allow native Hot plug, PME.
  193. // Never allow SHPC (no SHPC controller in this system).
  194. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  195. // Allows PCI Express Capability Structure control
  196. //
  197. if (AERF) {
  198. And (CTRL, 0x10, CTRL)
  199. } Else {
  200. And (CTRL, 0x18, CTRL)
  201. }
  202. //
  203. // Check for unknown revision.
  204. //
  205. If (LNotEqual (Arg1,One)) {
  206. Or (CDW1,0x08,CDW1)
  207. }
  208. //
  209. // Check if capabilities bits were masked.
  210. //
  211. If (LNotEqual (CDW3,CTRL)) {
  212. Or (CDW1,0x10,CDW1)
  213. }
  214. //
  215. // Update DWORD3 in the buffer.
  216. //
  217. Store (CTRL,CDW3)
  218. Return (Arg3)
  219. } Else {
  220. //
  221. // Unrecognized UUID
  222. //
  223. Or (CDW1,4,CDW1)
  224. Return (Arg3)
  225. }
  226. } // End _OSC
  227. //
  228. // Declare a _DSM method for various functions called by the OS.
  229. // See the APCI spec, Section 9.14.1,
  230. // and the PCI FW spec, Section 4.6.
  231. // See also:
  232. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  233. //
  234. Method (_DSM, 0x4, Serialized) {
  235. //
  236. // Match against the _DSM PCI GUID.
  237. //
  238. If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  239. Switch (ToInteger(Arg2)) {
  240. //
  241. // Function 0: Return supported functions as a bitfield
  242. // with one bit for each supported function.
  243. // Bit 0 must always be set, as that represents
  244. // function 0 (which is what is being called here).
  245. // Support for different functions may depend on
  246. // the revision ID of the interface, passed as Arg1.
  247. //
  248. Case (0) {
  249. //
  250. // Functions 0-7 are supported.
  251. //
  252. Return (Buffer() {0x01})
  253. }
  254. }
  255. }
  256. //
  257. // If not one of the function identifiers we recognize, then return a buffer
  258. // with bit 0 set to 0 indicating no functions supported.
  259. //
  260. Return (Buffer() {0})
  261. }
  262. //
  263. // Root Port 0 Device within the Root Complex.
  264. //
  265. Device (RP0) {
  266. //
  267. // Device 0, Function 0.
  268. //
  269. Name (_ADR, 0x00000000)
  270. }
  271. Method (_PXM, 0, NotSerialized) {
  272. // Patch by code
  273. Return(0xFF)
  274. }
  275. } // PCIA RCA2
  276. // PCIEB RCA3
  277. Device (PCIB) {
  278. //
  279. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  280. // Section 6.1.5
  281. //
  282. Name (_HID,"PNP0A08")
  283. Name (_CCA, ONE)
  284. Method (_STA, 0, NotSerialized) {
  285. Return (0xF)
  286. }
  287. //
  288. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  289. // root complex for use with pre-PCIe operating systems.
  290. // Section 6.1.2
  291. //
  292. Name (_CID,"PNP0A03")
  293. //
  294. // Declare the segment number of this root complex. Most systems only
  295. // have one segment, which is numbered 0.
  296. // Section 6.5.6
  297. //
  298. Name (_SEG, 7)
  299. //
  300. // Declare the base bus number, which is the bus number of the root
  301. // bus in this root complex. This is usually 0, but need not be.
  302. // For root complexes supporting multiple root busses, this should
  303. // be the lowest numbered root bus.
  304. // Section 6.5.5
  305. //
  306. Name (_BBN, 0)
  307. //
  308. // The _UID value provides a way of uniquely identifying a device
  309. // in the case where more than one instance of a specific device
  310. // is implemented with the same _HID/_CID. For systems with a
  311. // single root complex, this is usually just 0. For systems with
  312. // multiple root complexes, this should be different for each
  313. // root complex.
  314. // Section 6.1.12
  315. //
  316. Name (_UID, "PCIB")
  317. Name (_STR, Unicode("PCIe 11 Device"))
  318. //
  319. // Declare the PCI Routing Table.
  320. // This defines SPI mappings of the four line-based interrupts
  321. // associated with the root complex and hierarchy below it.
  322. // Section 6.2.12
  323. //
  324. Name (_PRT, Package() {
  325. //
  326. // Routing for device 0, all functions.
  327. // Note: ARM doesn't support LNK nodes, so the third param
  328. // is 0 and the fourth param is the SPI number of the interrupt
  329. // line. In this example, the A/B/C/D interrupts are wired to
  330. // SPI lines 140/141/142/143 + 320 respectively. PCIB RCA3
  331. //
  332. Package() {0x0001FFFF, 0, 0, 460},
  333. Package() {0x0001FFFF, 1, 0, 461},
  334. Package() {0x0001FFFF, 2, 0, 462},
  335. Package() {0x0001FFFF, 3, 0, 463},
  336. Package() {0x0002FFFF, 0, 0, 460},
  337. Package() {0x0002FFFF, 1, 0, 461},
  338. Package() {0x0002FFFF, 2, 0, 462},
  339. Package() {0x0002FFFF, 3, 0, 463},
  340. Package() {0x0003FFFF, 0, 0, 460},
  341. Package() {0x0003FFFF, 1, 0, 461},
  342. Package() {0x0003FFFF, 2, 0, 462},
  343. Package() {0x0003FFFF, 3, 0, 463},
  344. Package() {0x0004FFFF, 0, 0, 460},
  345. Package() {0x0004FFFF, 1, 0, 461},
  346. Package() {0x0004FFFF, 2, 0, 462},
  347. Package() {0x0004FFFF, 3, 0, 463},
  348. })
  349. //
  350. // Declare the resources assigned to this root complex.
  351. // Section 6.2.2
  352. //
  353. Method (_CBA, 0, Serialized) {
  354. Return (0x7FFFF0000000)
  355. }
  356. Name (RBUF, ResourceTemplate () {
  357. //
  358. // Declare the range of bus numbers assigned to this root
  359. // complex. In this example, the minimum bus number will be
  360. // 0, the maximum bus number will be 0xFF, supporting
  361. // 256 busses total.
  362. // Section 19.5.141
  363. //
  364. WordBusNumber (
  365. ResourceProducer,
  366. MinFixed, // IsMinFixed
  367. MaxFixed, // IsMaxFixed
  368. PosDecode, // Decode
  369. 0, // AddressGranularity
  370. 0, // AddressMinimum - Minimum Bus Number
  371. 255, // AddressMaximum - Maximum Bus Number
  372. 0, // AddressTranslation - Set to 0
  373. 256) // RangeLength - Number of Busses
  374. //
  375. // Declare the memory range to be used for BAR memory
  376. // windows. This declares a 4GB region starting at
  377. // 0x4000000000.
  378. // Section 19.5.80
  379. //
  380. // Memory32Fixed (ReadWrite, 0x1FFC0000, 0x10000, )
  381. QWordMemory (
  382. ResourceProducer, // ResourceUsage
  383. PosDecode, // Decode
  384. MinFixed, // IsMinFixed
  385. MaxFixed, // IsMaxFixed
  386. NonCacheable, // NonCacheable
  387. ReadWrite, // ReadAndWrite
  388. 0x0000000000000000, // AddressGranularity - GRA
  389. 0x0000000078000000, // AddressMinimum - MIN
  390. 0x000000007FFFFFFF, // AddressMinimum - MAX
  391. 0x0000000000000000, // AddressTranslation - TRA
  392. 0x0000000008000000 // RangeLength - LEN
  393. )
  394. QWordMemory (
  395. ResourceProducer, // ResourceUsage
  396. PosDecode, // Decode
  397. MinFixed, // IsMinFixed
  398. MaxFixed, // IsMaxFixed
  399. NonCacheable, // NonCacheable
  400. ReadWrite, // ReadAndWrite
  401. 0x0000000000000000, // AddressGranularity - GRA
  402. 0x00007C0000000000, // AddressMinimum - MIN
  403. 0x00007FFFDFFFFFFF, // AddressMaximum - MAX
  404. 0x0000000000000000, // AddressTranslation - TRA
  405. 0x000003FFE0000000 // RangeLength - LEN
  406. )
  407. })
  408. Method (_CRS, 0, Serialized) {
  409. Return (RBUF)
  410. }
  411. //
  412. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  413. //
  414. // Argments:
  415. // Arg0 A Buffer containing a UUID
  416. // Arg1 An Integer containing a Revision ID of the buffer format
  417. // Arg2 An Integer containing a count of entries in Arg3
  418. // Arg3 A Buffer containing a list of DWORD capabilities
  419. // Return Value:
  420. // A Buffer containing a list of capabilities
  421. // See the APCI spec, Section 6.2.10,
  422. // and the PCI FW spec, Section 4.5.
  423. //
  424. // The following is an example, and may need modification for
  425. // specific implementations.
  426. //
  427. Name (SUPP,0) // PCI _OSC Support Field value
  428. Name (CTRL,0) // PCI _OSC Control Field value
  429. Method (_OSC, 4) {
  430. //
  431. // Look for the PCI Host Bridge Interface UUID.
  432. // Section 6.2.10.3
  433. //
  434. //
  435. // Create DWord-adressable fields from the Capabilities Buffer
  436. // Create CDW1 outside the test as it's used in the else clause.
  437. //
  438. CreateDWordField (Arg3,0,CDW1)
  439. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  440. CreateDWordField (Arg3,4,CDW2)
  441. CreateDWordField (Arg3,8,CDW3)
  442. //
  443. // Save Capabilities DWord 2 & 3
  444. //
  445. Store (CDW2,SUPP)
  446. Store (CDW3,CTRL)
  447. //
  448. // Only allow native hot plug control if OS supports:
  449. // ASPM
  450. // Clock PM
  451. // MSI/MSI-X
  452. //
  453. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  454. //
  455. // Mask bit 0 (and undefined bits)
  456. //
  457. And (CTRL,0x1E,CTRL)
  458. }
  459. //
  460. // Never allow native Hot plug, PME.
  461. // Never allow SHPC (no SHPC controller in this system).
  462. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  463. // Allows PCI Express Capability Structure control
  464. //
  465. if (AERF) {
  466. And (CTRL, 0x10, CTRL)
  467. } Else {
  468. And (CTRL, 0x18, CTRL)
  469. }
  470. //
  471. // Check for unknown revision.
  472. //
  473. If (LNotEqual (Arg1,One)) {
  474. Or (CDW1,0x08,CDW1)
  475. }
  476. //
  477. // Check if capabilities bits were masked.
  478. //
  479. If (LNotEqual (CDW3,CTRL)) {
  480. Or (CDW1,0x10,CDW1)
  481. }
  482. //
  483. // Update DWORD3 in the buffer.
  484. //
  485. Store (CTRL,CDW3)
  486. Return (Arg3)
  487. } Else {
  488. //
  489. // Unrecognized UUID
  490. //
  491. Or (CDW1,4,CDW1)
  492. Return (Arg3)
  493. }
  494. } // End _OSC
  495. //
  496. // Declare a _DSM method for various functions called by the OS.
  497. // See the APCI spec, Section 9.14.1,
  498. // and the PCI FW spec, Section 4.6.
  499. // See also:
  500. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  501. //
  502. Method (_DSM, 0x4, Serialized) {
  503. //
  504. // Match against the _DSM PCI GUID.
  505. //
  506. If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  507. Switch (ToInteger(Arg2)) {
  508. //
  509. // Function 0: Return supported functions as a bitfield
  510. // with one bit for each supported function.
  511. // Bit 0 must always be set, as that represents
  512. // function 0 (which is what is being called here).
  513. // Support for different functions may depend on
  514. // the revision ID of the interface, passed as Arg1.
  515. //
  516. Case (0) {
  517. //
  518. // Functions 0-7 are supported.
  519. //
  520. Return (Buffer() {0x01})
  521. }
  522. }
  523. }
  524. //
  525. // If not one of the function identifiers we recognize, then return a buffer
  526. // with bit 0 set to 0 indicating no functions supported.
  527. //
  528. Return (Buffer() {0})
  529. }
  530. //
  531. // Root Port 0 Device within the Root Complex.
  532. //
  533. Device (RP0) {
  534. //
  535. // Device 0, Function 0.
  536. //
  537. Name (_ADR, 0x00000000)
  538. }
  539. Method (_PXM, 0, NotSerialized) {
  540. // Patch by code
  541. Return(0xFF)
  542. }
  543. } // PCIB RCA3
  544. // PCIC RCA4
  545. Device (PCIC) {
  546. //
  547. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  548. // Section 6.1.5
  549. //
  550. Name (_HID, "PNP0A08")
  551. Name (_CCA, ONE)
  552. Method (_STA, 0, NotSerialized) {
  553. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  554. // run-time patching as the representation of 0 is special
  555. // encoding and cannot be patched to expand with extra bytes
  556. // easily. As such, we default to 0xF and patch this based
  557. // on whether the port was enabled or not by the BIOS.
  558. }
  559. //
  560. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  561. // root complex for use with pre-PCIe operating systems.
  562. // Section 6.1.2
  563. //
  564. Name (_CID, "PNP0A03")
  565. //
  566. // Declare the segment number of this root complex. Most systems only
  567. // have one segment, which is numbered 0.
  568. // Section 6.5.6
  569. //
  570. Name (_SEG, 8)
  571. //
  572. // Declare the base bus number, which is the bus number of the root
  573. // bus in this root complex. This is usually 0, but need not be.
  574. // For root complexes supporting multiple root busses, this should
  575. // be the lowest numbered root bus.
  576. // Section 6.5.5
  577. //
  578. Name (_BBN, 0)
  579. //
  580. // The _UID value provides a way of uniquely identifying a device
  581. // in the case where more than one instance of a specific device
  582. // is implemented with the same _HID/_CID. For systems with a
  583. // single root complex, this is usually just 0. For systems with
  584. // multiple root complexes, this should be different for each
  585. // root complex.
  586. // Section 6.1.12
  587. //
  588. Name (_UID, "PCIC")
  589. Name (_STR, Unicode("PCIe 12 Device"))
  590. //
  591. // Declare the PCI Routing Table.
  592. // This defines SPI mappings of the four line-based interrupts
  593. // associated with the root complex and hierarchy below it.
  594. // Section 6.2.12
  595. //
  596. Name (_PRT, Package() {
  597. //
  598. // Routing for device 0, all functions.
  599. // Note: ARM doesn't support LNK nodes, so the third param
  600. // is 0 and the fourth param is the SPI number of the interrupt
  601. // line. In this example, the A/B/C/D interrupts are wired to
  602. // SPI lines 144/145/146/147 + 320 respectively. PCIC RCA4
  603. //
  604. Package() {0x0001FFFF, 0, 0, 464},
  605. Package() {0x0001FFFF, 1, 0, 465},
  606. Package() {0x0001FFFF, 2, 0, 466},
  607. Package() {0x0001FFFF, 3, 0, 467},
  608. Package() {0x0002FFFF, 0, 0, 464},
  609. Package() {0x0002FFFF, 1, 0, 465},
  610. Package() {0x0002FFFF, 2, 0, 466},
  611. Package() {0x0002FFFF, 3, 0, 467},
  612. Package() {0x0003FFFF, 0, 0, 464},
  613. Package() {0x0003FFFF, 1, 0, 465},
  614. Package() {0x0003FFFF, 2, 0, 466},
  615. Package() {0x0003FFFF, 3, 0, 467},
  616. Package() {0x0004FFFF, 0, 0, 464},
  617. Package() {0x0004FFFF, 1, 0, 465},
  618. Package() {0x0004FFFF, 2, 0, 466},
  619. Package() {0x0004FFFF, 3, 0, 467},
  620. Package() {0x0005FFFF, 0, 0, 464},
  621. Package() {0x0005FFFF, 1, 0, 465},
  622. Package() {0x0005FFFF, 2, 0, 466},
  623. Package() {0x0005FFFF, 3, 0, 467},
  624. Package() {0x0006FFFF, 0, 0, 464},
  625. Package() {0x0006FFFF, 1, 0, 465},
  626. Package() {0x0006FFFF, 2, 0, 466},
  627. Package() {0x0006FFFF, 3, 0, 467},
  628. Package() {0x0007FFFF, 0, 0, 464},
  629. Package() {0x0007FFFF, 1, 0, 465},
  630. Package() {0x0007FFFF, 2, 0, 466},
  631. Package() {0x0007FFFF, 3, 0, 467},
  632. Package() {0x0008FFFF, 0, 0, 464},
  633. Package() {0x0008FFFF, 1, 0, 465},
  634. Package() {0x0008FFFF, 2, 0, 466},
  635. Package() {0x0008FFFF, 3, 0, 467},
  636. })
  637. //
  638. // Declare the resources assigned to this root complex.
  639. // Section 6.2.2
  640. //
  641. Method (_CBA, 0, Serialized) {
  642. Return (0x63FFF0000000)
  643. }
  644. Name (RBUF, ResourceTemplate () {
  645. //
  646. // Declare the range of bus numbers assigned to this root
  647. // complex. In this example, the minimum bus number will be
  648. // 0, the maximum bus number will be 0xFF, supporting
  649. // 256 busses total.
  650. // Section 19.5.141
  651. //
  652. WordBusNumber (
  653. ResourceProducer,
  654. MinFixed, // IsMinFixed
  655. MaxFixed, // IsMaxFixed
  656. PosDecode, // Decode
  657. 0, // AddressGranularity
  658. 0, // AddressMinimum - Minimum Bus Number
  659. 255, // AddressMaximum - Maximum Bus Number
  660. 0, // AddressTranslation - Set to 0
  661. 256) // RangeLength - Number of Busses
  662. //
  663. // Declare the memory range to be used for BAR memory
  664. // windows. This declares a 4GB region starting at
  665. // 0x4000000000.
  666. // Section 19.5.80
  667. //
  668. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  669. QWordMemory (
  670. ResourceProducer, // ResourceUsage
  671. PosDecode, // Decode
  672. MinFixed, // IsMinFixed
  673. MaxFixed, // IsMaxFixed
  674. NonCacheable, // NonCacheable
  675. ReadWrite, // ReadAndWrite
  676. 0x0000000000000000, // AddressGranularity - GRA
  677. 0x0000000040000000, // AddressMinimum - MIN
  678. 0x0000000047FFFFFF, // AddressMinimum - MAX
  679. 0x0000000000000000, // AddressTranslation - TRA
  680. 0x0000000008000000 // RangeLength - LEN
  681. )
  682. QWordMemory (
  683. ResourceProducer, // ResourceUsage
  684. PosDecode, // Decode
  685. MinFixed, // IsMinFixed
  686. MaxFixed, // IsMaxFixed
  687. NonCacheable, // NonCacheable
  688. ReadWrite, // ReadAndWrite
  689. 0x0000000000000000, // AddressGranularity - GRA
  690. 0x0000600000000000, // AddressMinimum - MIN
  691. 0x000063FFDFFFFFFF, // AddressMaximum - MAX
  692. 0x0000000000000000, // AddressTranslation - TRA
  693. 0x000003FFE0000000 // RangeLength - LEN
  694. )
  695. })
  696. Method (_CRS, 0, Serialized) {
  697. Return (RBUF)
  698. }
  699. //
  700. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  701. //
  702. // Argments:
  703. // Arg0 A Buffer containing a UUID
  704. // Arg1 An Integer containing a Revision ID of the buffer format
  705. // Arg2 An Integer containing a count of entries in Arg3
  706. // Arg3 A Buffer containing a list of DWORD capabilities
  707. // Return Value:
  708. // A Buffer containing a list of capabilities
  709. // See the APCI spec, Section 6.2.10,
  710. // and the PCI FW spec, Section 4.5.
  711. //
  712. // The following is an example, and may need modification for
  713. // specific implementations.
  714. //
  715. Name (SUPP,0) // PCI _OSC Support Field value
  716. Name (CTRL,0) // PCI _OSC Control Field value
  717. Method (_OSC, 4) {
  718. //
  719. // Look for the PCI Host Bridge Interface UUID.
  720. // Section 6.2.10.3
  721. //
  722. //
  723. // Create DWord-adressable fields from the Capabilities Buffer
  724. // Create CDW1 outside the test as it's used in the else clause.
  725. //
  726. CreateDWordField (Arg3, 0, CDW1)
  727. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  728. CreateDWordField (Arg3, 4, CDW2)
  729. CreateDWordField (Arg3, 8, CDW3)
  730. //
  731. // Save Capabilities DWord 2 & 3
  732. //
  733. Store (CDW2, SUPP)
  734. Store (CDW3, CTRL)
  735. //
  736. // Only allow native hot plug control if OS supports:
  737. // ASPM
  738. // Clock PM
  739. // MSI/MSI-X
  740. //
  741. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  742. //
  743. // Mask bit 0 (and undefined bits)
  744. //
  745. And (CTRL, 0x1E, CTRL)
  746. }
  747. //
  748. // Never allow native Hot plug, PME.
  749. // Never allow SHPC (no SHPC controller in this system).
  750. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  751. // Allows PCI Express Capability Structure control
  752. //
  753. if (AERF) {
  754. And (CTRL, 0x10, CTRL)
  755. } Else {
  756. And (CTRL, 0x18, CTRL)
  757. }
  758. //
  759. // Check for unknown revision.
  760. //
  761. If (LNotEqual (Arg1, One)) {
  762. Or (CDW1, 0x08, CDW1)
  763. }
  764. //
  765. // Check if capabilities bits were masked.
  766. //
  767. If (LNotEqual (CDW3, CTRL)) {
  768. Or (CDW1, 0x10, CDW1)
  769. }
  770. //
  771. // Update DWORD3 in the buffer.
  772. //
  773. Store (CTRL, CDW3)
  774. Return (Arg3)
  775. } Else {
  776. //
  777. // Unrecognized UUID
  778. //
  779. Or (CDW1, 4, CDW1)
  780. Return (Arg3)
  781. }
  782. } // End _OSC
  783. //
  784. // Declare a _DSM method for various functions called by the OS.
  785. // See the APCI spec, Section 9.14.1,
  786. // and the PCI FW spec, Section 4.6.
  787. // See also:
  788. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  789. //
  790. Method (_DSM, 0x4, Serialized) {
  791. //
  792. // Match against the _DSM PCI GUID.
  793. //
  794. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  795. Switch (ToInteger(Arg2)) {
  796. //
  797. // Function 0: Return supported functions as a bitfield
  798. // with one bit for each supported function.
  799. // Bit 0 must always be set, as that represents
  800. // function 0 (which is what is being called here).
  801. // Support for different functions may depend on
  802. // the revision ID of the interface, passed as Arg1.
  803. //
  804. Case (0) {
  805. //
  806. // Functions 0-7 are supported.
  807. //
  808. Return (Buffer() {0x01})
  809. }
  810. }
  811. }
  812. //
  813. // If not one of the function identifiers we recognize, then return a buffer
  814. // with bit 0 set to 0 indicating no functions supported.
  815. //
  816. Return (Buffer() {0})
  817. }
  818. //
  819. // Root Port 0 Device within the Root Complex.
  820. //
  821. Device (RP0) {
  822. //
  823. // Device 0, Function 0.
  824. //
  825. Name (_ADR, 0x00000000)
  826. }
  827. Method (_PXM, 0, NotSerialized) {
  828. // Patch by code
  829. Return(0xFF)
  830. }
  831. } // PCIC RCA4
  832. // PCID RCA5
  833. Device (PCID) {
  834. //
  835. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  836. // Section 6.1.5
  837. //
  838. Name (_HID, "PNP0A08")
  839. Name (_CCA, ONE)
  840. Method (_STA, 0, NotSerialized) {
  841. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  842. // run-time patching as the representation of 0 is special
  843. // encoding and cannot be patched to expand with extra bytes
  844. // easily. As such, we default to 0xF and patch this based
  845. // on whether the port was enabled or not by the BIOS.
  846. }
  847. //
  848. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  849. // root complex for use with pre-PCIe operating systems.
  850. // Section 6.1.2
  851. //
  852. Name (_CID, "PNP0A03")
  853. //
  854. // Declare the segment number of this root complex. Most systems only
  855. // have one segment, which is numbered 0.
  856. // Section 6.5.6
  857. //
  858. Name (_SEG, 9)
  859. //
  860. // Declare the base bus number, which is the bus number of the root
  861. // bus in this root complex. This is usually 0, but need not be.
  862. // For root complexes supporting multiple root busses, this should
  863. // be the lowest numbered root bus.
  864. // Section 6.5.5
  865. //
  866. Name (_BBN, 0)
  867. //
  868. // The _UID value provides a way of uniquely identifying a device
  869. // in the case where more than one instance of a specific device
  870. // is implemented with the same _HID/_CID. For systems with a
  871. // single root complex, this is usually just 0. For systems with
  872. // multiple root complexes, this should be different for each
  873. // root complex.
  874. // Section 6.1.12
  875. //
  876. Name (_UID, "PCID")
  877. Name (_STR, Unicode("PCIe 13 Device"))
  878. //
  879. // Declare the PCI Routing Table.
  880. // This defines SPI mappings of the four line-based interrupts
  881. // associated with the root complex and hierarchy below it.
  882. // Section 6.2.12
  883. //
  884. Name (_PRT, Package() {
  885. //
  886. // Routing for device 0, all functions.
  887. // Note: ARM doesn't support LNK nodes, so the third param
  888. // is 0 and the fourth param is the SPI number of the interrupt
  889. // line. In this example, the A/B/C/D interrupts are wired to
  890. // SPI lines 148/149/150/151 + 320 respectively. PCID RCA5
  891. //
  892. Package() {0x0001FFFF, 0, 0, 468},
  893. Package() {0x0001FFFF, 1, 0, 469},
  894. Package() {0x0001FFFF, 2, 0, 470},
  895. Package() {0x0001FFFF, 3, 0, 471},
  896. Package() {0x0002FFFF, 0, 0, 468},
  897. Package() {0x0002FFFF, 1, 0, 469},
  898. Package() {0x0002FFFF, 2, 0, 470},
  899. Package() {0x0002FFFF, 3, 0, 471},
  900. Package() {0x0003FFFF, 0, 0, 468},
  901. Package() {0x0003FFFF, 1, 0, 469},
  902. Package() {0x0003FFFF, 2, 0, 470},
  903. Package() {0x0003FFFF, 3, 0, 471},
  904. Package() {0x0004FFFF, 0, 0, 468},
  905. Package() {0x0004FFFF, 1, 0, 469},
  906. Package() {0x0004FFFF, 2, 0, 470},
  907. Package() {0x0004FFFF, 3, 0, 471},
  908. Package() {0x0005FFFF, 0, 0, 468},
  909. Package() {0x0005FFFF, 1, 0, 469},
  910. Package() {0x0005FFFF, 2, 0, 470},
  911. Package() {0x0005FFFF, 3, 0, 471},
  912. Package() {0x0006FFFF, 0, 0, 468},
  913. Package() {0x0006FFFF, 1, 0, 469},
  914. Package() {0x0006FFFF, 2, 0, 470},
  915. Package() {0x0006FFFF, 3, 0, 471},
  916. Package() {0x0007FFFF, 0, 0, 468},
  917. Package() {0x0007FFFF, 1, 0, 469},
  918. Package() {0x0007FFFF, 2, 0, 470},
  919. Package() {0x0007FFFF, 3, 0, 471},
  920. Package() {0x0008FFFF, 0, 0, 468},
  921. Package() {0x0008FFFF, 1, 0, 469},
  922. Package() {0x0008FFFF, 2, 0, 470},
  923. Package() {0x0008FFFF, 3, 0, 471},
  924. })
  925. //
  926. // Declare the resources assigned to this root complex.
  927. // Section 6.2.2
  928. //
  929. Method (_CBA, 0, Serialized) {
  930. Return (0x67FFF0000000)
  931. }
  932. Name (RBUF, ResourceTemplate () {
  933. //
  934. // Declare the range of bus numbers assigned to this root
  935. // complex. In this example, the minimum bus number will be
  936. // 0, the maximum bus number will be 0xFF, supporting
  937. // 256 busses total.
  938. // Section 19.5.141
  939. //
  940. WordBusNumber (
  941. ResourceProducer,
  942. MinFixed, // IsMinFixed
  943. MaxFixed, // IsMaxFixed
  944. PosDecode, // Decode
  945. 0, // AddressGranularity
  946. 0, // AddressMinimum - Minimum Bus Number
  947. 255, // AddressMaximum - Maximum Bus Number
  948. 0, // AddressTranslation - Set to 0
  949. 256) // RangeLength - Number of Busses
  950. //
  951. // Declare the memory range to be used for BAR memory
  952. // windows. This declares a 4GB region starting at
  953. // 0x4000000000.
  954. // Section 19.5.80
  955. //
  956. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  957. QWordMemory (
  958. ResourceProducer, // ResourceUsage
  959. PosDecode, // Decode
  960. MinFixed, // IsMinFixed
  961. MaxFixed, // IsMaxFixed
  962. NonCacheable, // NonCacheable
  963. ReadWrite, // ReadAndWrite
  964. 0x0000000000000000, // AddressGranularity - GRA
  965. 0x0000000048000000, // AddressMinimum - MIN
  966. 0x000000004FFFFFFF, // AddressMinimum - MAX
  967. 0x0000000000000000, // AddressTranslation - TRA
  968. 0x0000000008000000 // RangeLength - LEN
  969. )
  970. QWordMemory (
  971. ResourceProducer, // ResourceUsage
  972. PosDecode, // Decode
  973. MinFixed, // IsMinFixed
  974. MaxFixed, // IsMaxFixed
  975. NonCacheable, // NonCacheable
  976. ReadWrite, // ReadAndWrite
  977. 0x0000000000000000, // AddressGranularity - GRA
  978. 0x0000640000000000, // AddressMinimum - MIN
  979. 0x000067FFDFFFFFFF, // AddressMaximum - MAX
  980. 0x0000000000000000, // AddressTranslation - TRA
  981. 0x000003FFE0000000 // RangeLength - LEN
  982. )
  983. })
  984. Method (_CRS, 0, Serialized) {
  985. Return (RBUF)
  986. }
  987. //
  988. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  989. //
  990. // Argments:
  991. // Arg0 A Buffer containing a UUID
  992. // Arg1 An Integer containing a Revision ID of the buffer format
  993. // Arg2 An Integer containing a count of entries in Arg3
  994. // Arg3 A Buffer containing a list of DWORD capabilities
  995. // Return Value:
  996. // A Buffer containing a list of capabilities
  997. // See the APCI spec, Section 6.2.10,
  998. // and the PCI FW spec, Section 4.5.
  999. //
  1000. // The following is an example, and may need modification for
  1001. // specific implementations.
  1002. //
  1003. Name (SUPP,0) // PCI _OSC Support Field value
  1004. Name (CTRL,0) // PCI _OSC Control Field value
  1005. Method (_OSC, 4) {
  1006. //
  1007. // Look for the PCI Host Bridge Interface UUID.
  1008. // Section 6.2.10.3
  1009. //
  1010. //
  1011. // Create DWord-adressable fields from the Capabilities Buffer
  1012. // Create CDW1 outside the test as it's used in the else clause.
  1013. //
  1014. CreateDWordField (Arg3, 0, CDW1)
  1015. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1016. CreateDWordField (Arg3, 4, CDW2)
  1017. CreateDWordField (Arg3, 8, CDW3)
  1018. //
  1019. // Save Capabilities DWord 2 & 3
  1020. //
  1021. Store (CDW2, SUPP)
  1022. Store (CDW3, CTRL)
  1023. //
  1024. // Only allow native hot plug control if OS supports:
  1025. // ASPM
  1026. // Clock PM
  1027. // MSI/MSI-X
  1028. //
  1029. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1030. //
  1031. // Mask bit 0 (and undefined bits)
  1032. //
  1033. And (CTRL, 0x1E, CTRL)
  1034. }
  1035. //
  1036. // Never allow native Hot plug, PME.
  1037. // Never allow SHPC (no SHPC controller in this system).
  1038. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1039. // Allows PCI Express Capability Structure control
  1040. //
  1041. if (AERF) {
  1042. And (CTRL, 0x10, CTRL)
  1043. } Else {
  1044. And (CTRL, 0x18, CTRL)
  1045. }
  1046. //
  1047. // Check for unknown revision.
  1048. //
  1049. If (LNotEqual (Arg1, One)) {
  1050. Or (CDW1, 0x08, CDW1)
  1051. }
  1052. //
  1053. // Check if capabilities bits were masked.
  1054. //
  1055. If (LNotEqual (CDW3, CTRL)) {
  1056. Or (CDW1, 0x10, CDW1)
  1057. }
  1058. //
  1059. // Update DWORD3 in the buffer.
  1060. //
  1061. Store (CTRL, CDW3)
  1062. Return (Arg3)
  1063. } Else {
  1064. //
  1065. // Unrecognized UUID
  1066. //
  1067. Or (CDW1, 4, CDW1)
  1068. Return (Arg3)
  1069. }
  1070. } // End _OSC
  1071. //
  1072. // Declare a _DSM method for various functions called by the OS.
  1073. // See the APCI spec, Section 9.14.1,
  1074. // and the PCI FW spec, Section 4.6.
  1075. // See also:
  1076. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1077. //
  1078. Method (_DSM, 0x4, Serialized) {
  1079. //
  1080. // Match against the _DSM PCI GUID.
  1081. //
  1082. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1083. Switch (ToInteger(Arg2)) {
  1084. //
  1085. // Function 0: Return supported functions as a bitfield
  1086. // with one bit for each supported function.
  1087. // Bit 0 must always be set, as that represents
  1088. // function 0 (which is what is being called here).
  1089. // Support for different functions may depend on
  1090. // the revision ID of the interface, passed as Arg1.
  1091. //
  1092. Case (0) {
  1093. //
  1094. // Functions 0-7 are supported.
  1095. //
  1096. Return (Buffer() {0x01})
  1097. }
  1098. }
  1099. }
  1100. //
  1101. // If not one of the function identifiers we recognize, then return a buffer
  1102. // with bit 0 set to 0 indicating no functions supported.
  1103. //
  1104. Return (Buffer() {0})
  1105. }
  1106. //
  1107. // Root Port 0 Device within the Root Complex.
  1108. //
  1109. Device (RP0) {
  1110. //
  1111. // Device 0, Function 0.
  1112. //
  1113. Name (_ADR, 0x00000000)
  1114. }
  1115. Method (_PXM, 0, NotSerialized) {
  1116. // Patch by code
  1117. Return(0xFF)
  1118. }
  1119. } // PCID RCA5
  1120. // PCIE RCA6
  1121. Device (PCIE) {
  1122. //
  1123. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  1124. // Section 6.1.5
  1125. //
  1126. Name (_HID, "PNP0A08")
  1127. Name (_CCA, ONE)
  1128. Method (_STA, 0, NotSerialized) {
  1129. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  1130. // run-time patching as the representation of 0 is special
  1131. // encoding and cannot be patched to expand with extra bytes
  1132. // easily. As such, we default to 0xF and patch this based
  1133. // on whether the port was enabled or not by the BIOS.
  1134. }
  1135. //
  1136. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  1137. // root complex for use with pre-PCIe operating systems.
  1138. // Section 6.1.2
  1139. //
  1140. Name (_CID, "PNP0A03")
  1141. //
  1142. // Declare the segment number of this root complex. Most systems only
  1143. // have one segment, which is numbered 0.
  1144. // Section 6.5.6
  1145. //
  1146. Name (_SEG, 10)
  1147. //
  1148. // Declare the base bus number, which is the bus number of the root
  1149. // bus in this root complex. This is usually 0, but need not be.
  1150. // For root complexes supporting multiple root busses, this should
  1151. // be the lowest numbered root bus.
  1152. // Section 6.5.5
  1153. //
  1154. Name (_BBN, 0)
  1155. //
  1156. // The _UID value provides a way of uniquely identifying a device
  1157. // in the case where more than one instance of a specific device
  1158. // is implemented with the same _HID/_CID. For systems with a
  1159. // single root complex, this is usually just 0. For systems with
  1160. // multiple root complexes, this should be different for each
  1161. // root complex.
  1162. // Section 6.1.12
  1163. //
  1164. Name (_UID, "PCIE")
  1165. Name (_STR, Unicode("PCIe 14 Device"))
  1166. //
  1167. // Declare the PCI Routing Table.
  1168. // This defines SPI mappings of the four line-based interrupts
  1169. // associated with the root complex and hierarchy below it.
  1170. // Section 6.2.12
  1171. //
  1172. Name (_PRT, Package() {
  1173. //
  1174. // Routing for device 0, all functions.
  1175. // Note: ARM doesn't support LNK nodes, so the third param
  1176. // is 0 and the fourth param is the SPI number of the interrupt
  1177. // line. In this example, the A/B/C/D interrupts are wired to
  1178. // SPI lines 152/153/154/155 + 320 respectively. PCIE RCA6
  1179. //
  1180. Package() {0x0001FFFF, 0, 0, 472},
  1181. Package() {0x0001FFFF, 1, 0, 473},
  1182. Package() {0x0001FFFF, 2, 0, 474},
  1183. Package() {0x0001FFFF, 3, 0, 475},
  1184. Package() {0x0002FFFF, 0, 0, 472},
  1185. Package() {0x0002FFFF, 1, 0, 473},
  1186. Package() {0x0002FFFF, 2, 0, 474},
  1187. Package() {0x0002FFFF, 3, 0, 475},
  1188. Package() {0x0003FFFF, 0, 0, 472},
  1189. Package() {0x0003FFFF, 1, 0, 473},
  1190. Package() {0x0003FFFF, 2, 0, 474},
  1191. Package() {0x0003FFFF, 3, 0, 475},
  1192. Package() {0x0004FFFF, 0, 0, 472},
  1193. Package() {0x0004FFFF, 1, 0, 473},
  1194. Package() {0x0004FFFF, 2, 0, 474},
  1195. Package() {0x0004FFFF, 3, 0, 475},
  1196. Package() {0x0005FFFF, 0, 0, 472},
  1197. Package() {0x0005FFFF, 1, 0, 473},
  1198. Package() {0x0005FFFF, 2, 0, 474},
  1199. Package() {0x0005FFFF, 3, 0, 475},
  1200. Package() {0x0006FFFF, 0, 0, 472},
  1201. Package() {0x0006FFFF, 1, 0, 473},
  1202. Package() {0x0006FFFF, 2, 0, 474},
  1203. Package() {0x0006FFFF, 3, 0, 475},
  1204. Package() {0x0007FFFF, 0, 0, 472},
  1205. Package() {0x0007FFFF, 1, 0, 473},
  1206. Package() {0x0007FFFF, 2, 0, 474},
  1207. Package() {0x0007FFFF, 3, 0, 475},
  1208. Package() {0x0008FFFF, 0, 0, 472},
  1209. Package() {0x0008FFFF, 1, 0, 473},
  1210. Package() {0x0008FFFF, 2, 0, 474},
  1211. Package() {0x0008FFFF, 3, 0, 475},
  1212. })
  1213. //
  1214. // Declare the resources assigned to this root complex.
  1215. // Section 6.2.2
  1216. //
  1217. Method (_CBA, 0, Serialized) {
  1218. Return (0x6BFFF0000000)
  1219. }
  1220. Name (RBUF, ResourceTemplate () {
  1221. //
  1222. // Declare the range of bus numbers assigned to this root
  1223. // complex. In this example, the minimum bus number will be
  1224. // 0, the maximum bus number will be 0xFF, supporting
  1225. // 256 busses total.
  1226. // Section 19.5.141
  1227. //
  1228. WordBusNumber (
  1229. ResourceProducer,
  1230. MinFixed, // IsMinFixed
  1231. MaxFixed, // IsMaxFixed
  1232. PosDecode, // Decode
  1233. 0, // AddressGranularity
  1234. 0, // AddressMinimum - Minimum Bus Number
  1235. 255, // AddressMaximum - Maximum Bus Number
  1236. 0, // AddressTranslation - Set to 0
  1237. 256) // RangeLength - Number of Busses
  1238. //
  1239. // Declare the memory range to be used for BAR memory
  1240. // windows. This declares a 4GB region starting at
  1241. // 0x4000000000.
  1242. // Section 19.5.80
  1243. //
  1244. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  1245. QWordMemory (
  1246. ResourceProducer, // ResourceUsage
  1247. PosDecode, // Decode
  1248. MinFixed, // IsMinFixed
  1249. MaxFixed, // IsMaxFixed
  1250. NonCacheable, // NonCacheable
  1251. ReadWrite, // ReadAndWrite
  1252. 0x0000000000000000, // AddressGranularity - GRA
  1253. 0x0000000050000000, // AddressMinimum - MIN
  1254. 0x0000000057FFFFFF, // AddressMaximum - MAX
  1255. 0x0000000000000000, // AddressTranslation - TRA
  1256. 0x0000000008000000 // RangeLength - LEN
  1257. )
  1258. QWordMemory (
  1259. ResourceProducer, // ResourceUsage
  1260. PosDecode, // Decode
  1261. MinFixed, // IsMinFixed
  1262. MaxFixed, // IsMaxFixed
  1263. NonCacheable, // NonCacheable
  1264. ReadWrite, // ReadAndWrite
  1265. 0x0000000000000000, // AddressGranularity - GRA
  1266. 0x0000680000000000, // AddressMinimum - MIN
  1267. 0x00006BFFDFFFFFFF, // AddressMinimum - MAX
  1268. 0x0000000000000000, // AddressTranslation - TRA
  1269. 0x000003FFE0000000 // RangeLength - LEN
  1270. )
  1271. })
  1272. Method (_CRS, 0, Serialized) {
  1273. Return (RBUF)
  1274. }
  1275. //
  1276. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  1277. //
  1278. // Argments:
  1279. // Arg0 A Buffer containing a UUID
  1280. // Arg1 An Integer containing a Revision ID of the buffer format
  1281. // Arg2 An Integer containing a count of entries in Arg3
  1282. // Arg3 A Buffer containing a list of DWORD capabilities
  1283. // Return Value:
  1284. // A Buffer containing a list of capabilities
  1285. // See the APCI spec, Section 6.2.10,
  1286. // and the PCI FW spec, Section 4.5.
  1287. //
  1288. // The following is an example, and may need modification for
  1289. // specific implementations.
  1290. //
  1291. Name (SUPP,0) // PCI _OSC Support Field value
  1292. Name (CTRL,0) // PCI _OSC Control Field value
  1293. Method (_OSC, 4) {
  1294. //
  1295. // Look for the PCI Host Bridge Interface UUID.
  1296. // Section 6.2.10.3
  1297. //
  1298. //
  1299. // Create DWord-adressable fields from the Capabilities Buffer
  1300. // Create CDW1 outside the test as it's used in the else clause.
  1301. //
  1302. CreateDWordField (Arg3, 0, CDW1)
  1303. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1304. CreateDWordField (Arg3, 4, CDW2)
  1305. CreateDWordField (Arg3, 8, CDW3)
  1306. //
  1307. // Save Capabilities DWord 2 & 3
  1308. //
  1309. Store (CDW2, SUPP)
  1310. Store (CDW3, CTRL)
  1311. //
  1312. // Only allow native hot plug control if OS supports:
  1313. // ASPM
  1314. // Clock PM
  1315. // MSI/MSI-X
  1316. //
  1317. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1318. //
  1319. // Mask bit 0 (and undefined bits)
  1320. //
  1321. And (CTRL, 0x1E, CTRL)
  1322. }
  1323. //
  1324. // Never allow native Hot plug, PME.
  1325. // Never allow SHPC (no SHPC controller in this system).
  1326. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1327. // Allows PCI Express Capability Structure control
  1328. //
  1329. if (AERF) {
  1330. And (CTRL, 0x10, CTRL)
  1331. } Else {
  1332. And (CTRL, 0x18, CTRL)
  1333. }
  1334. //
  1335. // Check for unknown revision.
  1336. //
  1337. If (LNotEqual (Arg1, One)) {
  1338. Or (CDW1, 0x08, CDW1)
  1339. }
  1340. //
  1341. // Check if capabilities bits were masked.
  1342. //
  1343. If (LNotEqual (CDW3, CTRL)) {
  1344. Or (CDW1, 0x10, CDW1)
  1345. }
  1346. //
  1347. // Update DWORD3 in the buffer.
  1348. //
  1349. Store (CTRL, CDW3)
  1350. Return (Arg3)
  1351. } Else {
  1352. //
  1353. // Unrecognized UUID
  1354. //
  1355. Or (CDW1, 4, CDW1)
  1356. Return (Arg3)
  1357. }
  1358. } // End _OSC
  1359. //
  1360. // Declare a _DSM method for various functions called by the OS.
  1361. // See the APCI spec, Section 9.14.1,
  1362. // and the PCI FW spec, Section 4.6.
  1363. // See also:
  1364. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1365. //
  1366. Method (_DSM, 0x4, Serialized) {
  1367. //
  1368. // Match against the _DSM PCI GUID.
  1369. //
  1370. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1371. Switch (ToInteger(Arg2)) {
  1372. //
  1373. // Function 0: Return supported functions as a bitfield
  1374. // with one bit for each supported function.
  1375. // Bit 0 must always be set, as that represents
  1376. // function 0 (which is what is being called here).
  1377. // Support for different functions may depend on
  1378. // the revision ID of the interface, passed as Arg1.
  1379. //
  1380. Case (0) {
  1381. //
  1382. // Functions 0-7 are supported.
  1383. //
  1384. Return (Buffer() {0x01})
  1385. }
  1386. }
  1387. }
  1388. //
  1389. // If not one of the function identifiers we recognize, then return a buffer
  1390. // with bit 0 set to 0 indicating no functions supported.
  1391. //
  1392. Return (Buffer() {0})
  1393. }
  1394. //
  1395. // Root Port 0 Device within the Root Complex.
  1396. //
  1397. Device (RP0) {
  1398. //
  1399. // Device 0, Function 0.
  1400. //
  1401. Name (_ADR, 0x00000000)
  1402. }
  1403. Method (_PXM, 0, NotSerialized) {
  1404. // Patch by code
  1405. Return(0xFF)
  1406. }
  1407. } // PCIE RCA6
  1408. // PCIF RCA7
  1409. Device (PCIF) {
  1410. //
  1411. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  1412. // Section 6.1.5
  1413. //
  1414. Name (_HID, "PNP0A08")
  1415. Name (_CCA, ONE)
  1416. Method (_STA, 0, NotSerialized) {
  1417. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  1418. // run-time patching as the representation of 0 is special
  1419. // encoding and cannot be patched to expand with extra bytes
  1420. // easily. As such, we default to 0xF and patch this based
  1421. // on whether the port was enabled or not by the BIOS.
  1422. }
  1423. //
  1424. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  1425. // root complex for use with pre-PCIe operating systems.
  1426. // Section 6.1.2
  1427. //
  1428. Name (_CID, "PNP0A03")
  1429. //
  1430. // Declare the segment number of this root complex. Most systems only
  1431. // have one segment, which is numbered 0.
  1432. // Section 6.5.6
  1433. //
  1434. Name (_SEG, 11)
  1435. //
  1436. // Declare the base bus number, which is the bus number of the root
  1437. // bus in this root complex. This is usually 0, but need not be.
  1438. // For root complexes supporting multiple root busses, this should
  1439. // be the lowest numbered root bus.
  1440. // Section 6.5.5
  1441. //
  1442. Name (_BBN, 0)
  1443. //
  1444. // The _UID value provides a way of uniquely identifying a device
  1445. // in the case where more than one instance of a specific device
  1446. // is implemented with the same _HID/_CID. For systems with a
  1447. // single root complex, this is usually just 0. For systems with
  1448. // multiple root complexes, this should be different for each
  1449. // root complex.
  1450. // Section 6.1.12
  1451. //
  1452. Name (_UID, "PCIF")
  1453. Name (_STR, Unicode("PCIe 15 Device"))
  1454. //
  1455. // Declare the PCI Routing Table.
  1456. // This defines SPI mappings of the four line-based interrupts
  1457. // associated with the root complex and hierarchy below it.
  1458. // Section 6.2.12
  1459. //
  1460. Name (_PRT, Package() {
  1461. //
  1462. // Routing for device 0, all functions.
  1463. // Note: ARM doesn't support LNK nodes, so the third param
  1464. // is 0 and the fourth param is the SPI number of the interrupt
  1465. // line. In this example, the A/B/C/D interrupts are wired to
  1466. // SPI lines 156/157/158/159 + 320 respectively. PCIF RCA7
  1467. //
  1468. Package() {0x0001FFFF, 0, 0, 476},
  1469. Package() {0x0001FFFF, 1, 0, 477},
  1470. Package() {0x0001FFFF, 2, 0, 478},
  1471. Package() {0x0001FFFF, 3, 0, 479},
  1472. Package() {0x0002FFFF, 0, 0, 476},
  1473. Package() {0x0002FFFF, 1, 0, 477},
  1474. Package() {0x0002FFFF, 2, 0, 478},
  1475. Package() {0x0002FFFF, 3, 0, 479},
  1476. Package() {0x0003FFFF, 0, 0, 476},
  1477. Package() {0x0003FFFF, 1, 0, 477},
  1478. Package() {0x0003FFFF, 2, 0, 478},
  1479. Package() {0x0003FFFF, 3, 0, 479},
  1480. Package() {0x0004FFFF, 0, 0, 476},
  1481. Package() {0x0004FFFF, 1, 0, 477},
  1482. Package() {0x0004FFFF, 2, 0, 478},
  1483. Package() {0x0004FFFF, 3, 0, 479},
  1484. Package() {0x0005FFFF, 0, 0, 476},
  1485. Package() {0x0005FFFF, 1, 0, 477},
  1486. Package() {0x0005FFFF, 2, 0, 478},
  1487. Package() {0x0005FFFF, 3, 0, 479},
  1488. Package() {0x0006FFFF, 0, 0, 476},
  1489. Package() {0x0006FFFF, 1, 0, 477},
  1490. Package() {0x0006FFFF, 2, 0, 478},
  1491. Package() {0x0006FFFF, 3, 0, 479},
  1492. Package() {0x0007FFFF, 0, 0, 476},
  1493. Package() {0x0007FFFF, 1, 0, 477},
  1494. Package() {0x0007FFFF, 2, 0, 478},
  1495. Package() {0x0007FFFF, 3, 0, 479},
  1496. Package() {0x0008FFFF, 0, 0, 476},
  1497. Package() {0x0008FFFF, 1, 0, 477},
  1498. Package() {0x0008FFFF, 2, 0, 478},
  1499. Package() {0x0008FFFF, 3, 0, 479},
  1500. })
  1501. //
  1502. // Declare the resources assigned to this root complex.
  1503. // Section 6.2.2
  1504. //
  1505. Method (_CBA, 0, Serialized) {
  1506. Return (0x6FFFF0000000)
  1507. }
  1508. Name (RBUF, ResourceTemplate () {
  1509. //
  1510. // Declare the range of bus numbers assigned to this root
  1511. // complex. In this example, the minimum bus number will be
  1512. // 0, the maximum bus number will be 0xFF, supporting
  1513. // 256 busses total.
  1514. // Section 19.5.141
  1515. //
  1516. WordBusNumber (
  1517. ResourceProducer,
  1518. MinFixed, // IsMinFixed
  1519. MaxFixed, // IsMaxFixed
  1520. PosDecode, // Decode
  1521. 0, // AddressGranularity
  1522. 0, // AddressMinimum - Minimum Bus Number
  1523. 255, // AddressMaximum - Maximum Bus Number
  1524. 0, // AddressTranslation - Set to 0
  1525. 256) // RangeLength - Number of Busses
  1526. //
  1527. // Declare the memory range to be used for BAR memory
  1528. // windows. This declares a 4GB region starting at
  1529. // 0x4000000000.
  1530. // Section 19.5.80
  1531. //
  1532. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  1533. QWordMemory (
  1534. ResourceProducer, // ResourceUsage
  1535. PosDecode, // Decode
  1536. MinFixed, // IsMinFixed
  1537. MaxFixed, // IsMaxFixed
  1538. NonCacheable, // NonCacheable
  1539. ReadWrite, // ReadAndWrite
  1540. 0x0000000000000000, // AddressGranularity - GRA
  1541. 0x0000000058000000, // AddressMinimum - MIN
  1542. 0x000000005FFFFFFF, // AddressMinimum - MAX
  1543. 0x0000000000000000, // AddressTranslation - TRA
  1544. 0x0000000008000000 // RangeLength - LEN
  1545. )
  1546. QWordMemory (
  1547. ResourceProducer, // ResourceUsage
  1548. PosDecode, // Decode
  1549. MinFixed, // IsMinFixed
  1550. MaxFixed, // IsMaxFixed
  1551. NonCacheable, // NonCacheable
  1552. ReadWrite, // ReadAndWrite
  1553. 0x0000000000000000, // AddressGranularity - GRA
  1554. 0x00006C0000000000, // AddressMinimum - MIN
  1555. 0x00006FFFDFFFFFFF, // AddressMinimum - MAX
  1556. 0x0000000000000000, // AddressTranslation - TRA
  1557. 0x000003FFE0000000 // RangeLength - LEN
  1558. )
  1559. })
  1560. Method (_CRS, 0, Serialized) {
  1561. Return (RBUF)
  1562. }
  1563. //
  1564. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  1565. //
  1566. // Argments:
  1567. // Arg0 A Buffer containing a UUID
  1568. // Arg1 An Integer containing a Revision ID of the buffer format
  1569. // Arg2 An Integer containing a count of entries in Arg3
  1570. // Arg3 A Buffer containing a list of DWORD capabilities
  1571. // Return Value:
  1572. // A Buffer containing a list of capabilities
  1573. // See the APCI spec, Section 6.2.10,
  1574. // and the PCI FW spec, Section 4.5.
  1575. //
  1576. // The following is an example, and may need modification for
  1577. // specific implementations.
  1578. //
  1579. Name (SUPP,0) // PCI _OSC Support Field value
  1580. Name (CTRL,0) // PCI _OSC Control Field value
  1581. Method (_OSC, 4) {
  1582. //
  1583. // Look for the PCI Host Bridge Interface UUID.
  1584. // Section 6.2.10.3
  1585. //
  1586. //
  1587. // Create DWord-adressable fields from the Capabilities Buffer
  1588. // Create CDW1 outside the test as it's used in the else clause.
  1589. //
  1590. CreateDWordField (Arg3, 0, CDW1)
  1591. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1592. CreateDWordField (Arg3, 4, CDW2)
  1593. CreateDWordField (Arg3, 8, CDW3)
  1594. //
  1595. // Save Capabilities DWord 2 & 3
  1596. //
  1597. Store (CDW2, SUPP)
  1598. Store (CDW3, CTRL)
  1599. //
  1600. // Only allow native hot plug control if OS supports:
  1601. // ASPM
  1602. // Clock PM
  1603. // MSI/MSI-X
  1604. //
  1605. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1606. //
  1607. // Mask bit 0 (and undefined bits)
  1608. //
  1609. And (CTRL, 0x1E, CTRL)
  1610. }
  1611. //
  1612. // Never allow native Hot plug, PME.
  1613. // Never allow SHPC (no SHPC controller in this system).
  1614. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1615. // Allows PCI Express Capability Structure control
  1616. //
  1617. if (AERF) {
  1618. And (CTRL, 0x10, CTRL)
  1619. } Else {
  1620. And (CTRL, 0x18, CTRL)
  1621. }
  1622. //
  1623. // Check for unknown revision.
  1624. //
  1625. If (LNotEqual (Arg1, One)) {
  1626. Or (CDW1, 0x08, CDW1)
  1627. }
  1628. //
  1629. // Check if capabilities bits were masked.
  1630. //
  1631. If (LNotEqual (CDW3, CTRL)) {
  1632. Or (CDW1, 0x10, CDW1)
  1633. }
  1634. //
  1635. // Update DWORD3 in the buffer.
  1636. //
  1637. Store (CTRL, CDW3)
  1638. Return (Arg3)
  1639. } Else {
  1640. //
  1641. // Unrecognized UUID
  1642. //
  1643. Or (CDW1, 4, CDW1)
  1644. Return (Arg3)
  1645. }
  1646. } // End _OSC
  1647. //
  1648. // Declare a _DSM method for various functions called by the OS.
  1649. // See the APCI spec, Section 9.14.1,
  1650. // and the PCI FW spec, Section 4.6.
  1651. // See also:
  1652. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1653. //
  1654. Method (_DSM, 0x4, Serialized) {
  1655. //
  1656. // Match against the _DSM PCI GUID.
  1657. //
  1658. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1659. Switch (ToInteger(Arg2)) {
  1660. //
  1661. // Function 0: Return supported functions as a bitfield
  1662. // with one bit for each supported function.
  1663. // Bit 0 must always be set, as that represents
  1664. // function 0 (which is what is being called here).
  1665. // Support for different functions may depend on
  1666. // the revision ID of the interface, passed as Arg1.
  1667. //
  1668. Case (0) {
  1669. //
  1670. // Functions 0-7 are supported.
  1671. //
  1672. Return (Buffer() {0x01})
  1673. }
  1674. }
  1675. }
  1676. //
  1677. // If not one of the function identifiers we recognize, then return a buffer
  1678. // with bit 0 set to 0 indicating no functions supported.
  1679. //
  1680. Return (Buffer() {0})
  1681. }
  1682. //
  1683. // Root Port 0 Device within the Root Complex.
  1684. //
  1685. Device (RP0) {
  1686. //
  1687. // Device 0, Function 0.
  1688. //
  1689. Name (_ADR, 0x00000000)
  1690. }
  1691. Method (_PXM, 0, NotSerialized) {
  1692. // Patch by code
  1693. Return(0xFF)
  1694. }
  1695. } // PCIF RCA7