PCI-S0.asi 56 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041
  1. /** @file
  2. Copyright (c) 2023, Ampere Computing LLC. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. // PCI2 RCA2
  6. Device (PCI2) {
  7. //
  8. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  9. // Section 6.1.5
  10. //
  11. Name (_HID, "PNP0A08")
  12. Name (_CCA, ONE)
  13. Method (_STA, 0, NotSerialized) {
  14. Return (0xF)
  15. }
  16. //
  17. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  18. // root complex for use with pre-PCIe operating systems.
  19. // Section 6.1.2
  20. //
  21. Name (_CID, "PNP0A03")
  22. //
  23. // Declare the segment number of this root complex. Most systems only
  24. // have one segment, which is numbered 0.
  25. // Section 6.5.6
  26. //
  27. Name (_SEG, 1)
  28. //
  29. // Declare the base bus number, which is the bus number of the root
  30. // bus in this root complex. This is usually 0, but need not be.
  31. // For root complexes supporting multiple root busses, this should
  32. // be the lowest numbered root bus.
  33. // Section 6.5.5
  34. //
  35. Name (_BBN, 0)
  36. //
  37. // The _UID value provides a way of uniquely identifying a device
  38. // in the case where more than one instance of a specific device
  39. // is implemented with the same _HID/_CID. For systems with a
  40. // single root complex, this is usually just 0. For systems with
  41. // multiple root complexes, this should be different for each
  42. // root complex.
  43. // Section 6.1.12
  44. //
  45. Name (_UID, "PCI2")
  46. Name (_STR, Unicode("PCIe 2 Device"))
  47. //
  48. // Declare the PCI Routing Table.
  49. // This defines SPI mappings of the four line-based interrupts
  50. // associated with the root complex and hierarchy below it.
  51. // Section 6.2.12
  52. //
  53. Name (_PRT, Package() {
  54. //
  55. // Routing for device 0, all functions.
  56. // Note: ARM doesn't support LNK nodes, so the third param
  57. // is 0 and the fourth param is the SPI number of the interrupt
  58. // line. In this example, the A/B/C/D interrupts are wired to
  59. // SPI lines 136/137/138/139 respectively. PCI2 RCA2
  60. //
  61. Package() {0x0001FFFF, 0, 0, 136},
  62. Package() {0x0001FFFF, 1, 0, 137},
  63. Package() {0x0001FFFF, 2, 0, 138},
  64. Package() {0x0001FFFF, 3, 0, 139},
  65. Package() {0x0002FFFF, 0, 0, 136},
  66. Package() {0x0002FFFF, 1, 0, 137},
  67. Package() {0x0002FFFF, 2, 0, 138},
  68. Package() {0x0002FFFF, 3, 0, 139},
  69. Package() {0x0003FFFF, 0, 0, 136},
  70. Package() {0x0003FFFF, 1, 0, 137},
  71. Package() {0x0003FFFF, 2, 0, 138},
  72. Package() {0x0003FFFF, 3, 0, 139},
  73. Package() {0x0004FFFF, 0, 0, 136},
  74. Package() {0x0004FFFF, 1, 0, 137},
  75. Package() {0x0004FFFF, 2, 0, 138},
  76. Package() {0x0004FFFF, 3, 0, 139},
  77. })
  78. //
  79. // Declare the resources assigned to this root complex.
  80. // Section 6.2.2
  81. //
  82. Method (_CBA, 0, Serialized) {
  83. Return (0x3BFFF0000000)
  84. }
  85. Name (RBUF, ResourceTemplate () {
  86. //
  87. // Declare the range of bus numbers assigned to this root
  88. // complex. In this example, the minimum bus number will be
  89. // 0, the maximum bus number will be 0xFF, supporting
  90. // 256 busses total.
  91. // Section 19.5.141
  92. //
  93. WordBusNumber (
  94. ResourceProducer,
  95. MinFixed, // IsMinFixed
  96. MaxFixed, // IsMaxFixed
  97. PosDecode, // Decode
  98. 0, // AddressGranularity
  99. 0, // AddressMinimum - Minimum Bus Number
  100. 255, // AddressMaximum - Maximum Bus Number
  101. 0, // AddressTranslation - Set to 0
  102. 256) // RangeLength - Number of Busses
  103. //
  104. // Declare the memory range to be used for BAR memory
  105. // windows. This declares a 4GB region starting at
  106. // 0x4000000000.
  107. // Section 19.5.80
  108. //
  109. // Memory32Fixed (ReadWrite, 0x1FE80000, 0x10000, )
  110. QWordMemory (
  111. ResourceProducer, // ResourceUsage
  112. PosDecode, // Decode
  113. MinFixed, // IsMinFixed
  114. MaxFixed, // IsMaxFixed
  115. NonCacheable, // NonCacheable
  116. ReadWrite, // ReadAndWrite
  117. 0x0000000000000000, // AddressGranularity - GRA
  118. 0x0000000030000000, // AddressMinimum - MIN
  119. 0x0000000037FFFFFF, // AddressMinimum - MAX
  120. 0x0000000000000000, // AddressTranslation - TRA
  121. 0x0000000008000000 // RangeLength - LEN
  122. )
  123. QWordMemory (
  124. ResourceProducer, // ResourceUsage
  125. PosDecode, // Decode
  126. MinFixed, // IsMinFixed
  127. MaxFixed, // IsMaxFixed
  128. NonCacheable, // NonCacheable
  129. ReadWrite, // ReadAndWrite
  130. 0x0000000000000000, // AddressGranularity - GRA
  131. 0x0000380000000000, // AddressMinimum - MIN
  132. 0x00003BFFDFFFFFFF, // AddressMaximum - MAX
  133. 0x0000000000000000, // AddressTranslation - TRA
  134. 0x000003FFE0000000 // RangeLength - LEN
  135. )
  136. })
  137. Method (_CRS, 0, Serialized) {
  138. Return (RBUF)
  139. }
  140. //
  141. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  142. //
  143. // Argments:
  144. // Arg0 A Buffer containing a UUID
  145. // Arg1 An Integer containing a Revision ID of the buffer format
  146. // Arg2 An Integer containing a count of entries in Arg3
  147. // Arg3 A Buffer containing a list of DWORD capabilities
  148. // Return Value:
  149. // A Buffer containing a list of capabilities
  150. // See the APCI spec, Section 6.2.10,
  151. // and the PCI FW spec, Section 4.5.
  152. //
  153. // The following is an example, and may need modification for
  154. // specific implementations.
  155. //
  156. Name (SUPP, 0) // PCI _OSC Support Field value
  157. Name (CTRL, 0) // PCI _OSC Control Field value
  158. Method (_OSC, 4) {
  159. //
  160. // Look for the PCI Host Bridge Interface UUID.
  161. // Section 6.2.10.3
  162. //
  163. //
  164. // Create DWord-adressable fields from the Capabilities Buffer
  165. // Create CDW1 outside the test as it's used in the else clause.
  166. //
  167. CreateDWordField (Arg3,0,CDW1)
  168. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  169. CreateDWordField (Arg3, 4, CDW2)
  170. CreateDWordField (Arg3, 8, CDW3)
  171. //
  172. // Save Capabilities DWord 2 & 3
  173. //
  174. Store (CDW2, SUPP)
  175. Store (CDW3, CTRL)
  176. //
  177. // Only allow native hot plug control if OS supports:
  178. // ASPM
  179. // Clock PM
  180. // MSI/MSI-X
  181. //
  182. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  183. //
  184. // Mask bit 0 (and undefined bits)
  185. //
  186. And (CTRL, 0x1E, CTRL)
  187. }
  188. //
  189. // Never allow native Hot plug, PME.
  190. // Never allow SHPC (no SHPC controller in this system).
  191. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  192. // Allows PCI Express Capability Structure control
  193. //
  194. if (AERF) {
  195. And (CTRL, 0x10, CTRL)
  196. } Else {
  197. And (CTRL, 0x18, CTRL)
  198. }
  199. //
  200. // Check for unknown revision.
  201. //
  202. If (LNotEqual (Arg1, One)) {
  203. Or (CDW1, 0x08, CDW1)
  204. }
  205. //
  206. // Check if capabilities bits were masked.
  207. //
  208. If (LNotEqual (CDW3, CTRL)) {
  209. Or (CDW1, 0x10, CDW1)
  210. }
  211. //
  212. // Update DWORD3 in the buffer.
  213. //
  214. Store (CTRL, CDW3)
  215. Return (Arg3)
  216. } Else {
  217. //
  218. // Unrecognized UUID
  219. //
  220. Or (CDW1, 4, CDW1)
  221. Return (Arg3)
  222. }
  223. } // End _OSC
  224. //
  225. // Declare a _DSM method for various functions called by the OS.
  226. // See the APCI spec, Section 9.14.1,
  227. // and the PCI FW spec, Section 4.6.
  228. // See also:
  229. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  230. //
  231. Method (_DSM, 0x4, Serialized) {
  232. //
  233. // Match against the _DSM PCI GUID.
  234. //
  235. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  236. Switch (ToInteger(Arg2)) {
  237. //
  238. // Function 0: Return supported functions as a bitfield
  239. // with one bit for each supported function.
  240. // Bit 0 must always be set, as that represents
  241. // function 0 (which is what is being called here).
  242. // Support for different functions may depend on
  243. // the revision ID of the interface, passed as Arg1.
  244. //
  245. Case (0) {
  246. //
  247. // Functions 0-7 are supported.
  248. //
  249. Return (Buffer() {0x01})
  250. }
  251. }
  252. }
  253. //
  254. // If not one of the function identifiers we recognize, then return a buffer
  255. // with bit 0 set to 0 indicating no functions supported.
  256. //
  257. Return (Buffer() {0})
  258. }
  259. //
  260. // Root Port 0 Device within the Root Complex.
  261. //
  262. Device (RP0) {
  263. //
  264. // Device 0, Function 0.
  265. //
  266. Name (_ADR, 0x00000000)
  267. }
  268. Method (_PXM, 0, NotSerialized) {
  269. // Patch by code
  270. Return(0xFF)
  271. }
  272. } // PCI2 RCA2
  273. // PCI3 RCA3
  274. Device (PCI3) {
  275. //
  276. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  277. // Section 6.1.5
  278. //
  279. Name (_HID, "PNP0A08")
  280. Name (_CCA, ONE)
  281. Method (_STA, 0, NotSerialized) {
  282. Return (0xF)
  283. }
  284. //
  285. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  286. // root complex for use with pre-PCIe operating systems.
  287. // Section 6.1.2
  288. //
  289. Name (_CID, "PNP0A03")
  290. //
  291. // Declare the segment number of this root complex. Most systems only
  292. // have one segment, which is numbered 0.
  293. // Section 6.5.6
  294. //
  295. Name (_SEG, 0)
  296. //
  297. // Declare the base bus number, which is the bus number of the root
  298. // bus in this root complex. This is usually 0, but need not be.
  299. // For root complexes supporting multiple root busses, this should
  300. // be the lowest numbered root bus.
  301. // Section 6.5.5
  302. //
  303. Name (_BBN, 0)
  304. //
  305. // The _UID value provides a way of uniquely identifying a device
  306. // in the case where more than one instance of a specific device
  307. // is implemented with the same _HID/_CID. For systems with a
  308. // single root complex, this is usually just 0. For systems with
  309. // multiple root complexes, this should be different for each
  310. // root complex.
  311. // Section 6.1.12
  312. //
  313. Name (_UID, "PCI3")
  314. Name (_STR, Unicode("PCIe 3 Device"))
  315. //
  316. // Declare the PCI Routing Table.
  317. // This defines SPI mappings of the four line-based interrupts
  318. // associated with the root complex and hierarchy below it.
  319. // Section 6.2.12
  320. //
  321. Name (_PRT, Package() {
  322. //
  323. // Routing for device 0, all functions.
  324. // Note: ARM doesn't support LNK nodes, so the third param
  325. // is 0 and the fourth param is the SPI number of the interrupt
  326. // line. In this example, the A/B/C/D interrupts are wired to
  327. // SPI lines 140/141/142/143 respectively. PCI3 RCA3
  328. //
  329. Package() {0x0001FFFF, 0, 0, 140},
  330. Package() {0x0001FFFF, 1, 0, 141},
  331. Package() {0x0001FFFF, 2, 0, 142},
  332. Package() {0x0001FFFF, 3, 0, 143},
  333. Package() {0x0002FFFF, 0, 0, 140},
  334. Package() {0x0002FFFF, 1, 0, 141},
  335. Package() {0x0002FFFF, 2, 0, 142},
  336. Package() {0x0002FFFF, 3, 0, 143},
  337. Package() {0x0003FFFF, 0, 0, 140},
  338. Package() {0x0003FFFF, 1, 0, 141},
  339. Package() {0x0003FFFF, 2, 0, 142},
  340. Package() {0x0003FFFF, 3, 0, 143},
  341. Package() {0x0004FFFF, 0, 0, 140},
  342. Package() {0x0004FFFF, 1, 0, 141},
  343. Package() {0x0004FFFF, 2, 0, 142},
  344. Package() {0x0004FFFF, 3, 0, 143},
  345. })
  346. //
  347. // Declare the resources assigned to this root complex.
  348. // Section 6.2.2
  349. //
  350. Method (_CBA, 0, Serialized) {
  351. Return (0x3FFFF0000000)
  352. }
  353. Name (RBUF, ResourceTemplate () {
  354. //
  355. // Declare the range of bus numbers assigned to this root
  356. // complex. In this example, the minimum bus number will be
  357. // 0, the maximum bus number will be 0xFF, supporting
  358. // 256 busses total.
  359. // Section 19.5.141
  360. //
  361. WordBusNumber (
  362. ResourceProducer,
  363. MinFixed, // IsMinFixed
  364. MaxFixed, // IsMaxFixed
  365. PosDecode, // Decode
  366. 0, // AddressGranularity
  367. 0, // AddressMinimum - Minimum Bus Number
  368. 255, // AddressMaximum - Maximum Bus Number
  369. 0, // AddressTranslation - Set to 0
  370. 256) // RangeLength - Number of Busses
  371. //
  372. // Declare the memory range to be used for BAR memory
  373. // windows. This declares a 4GB region starting at
  374. // 0x4000000000.
  375. // Section 19.5.80
  376. //
  377. // Memory32Fixed (ReadWrite, 0x1FE00000, 0x10000, )
  378. QWordMemory (
  379. ResourceProducer, // ResourceUsage
  380. PosDecode, // Decode
  381. MinFixed, // IsMinFixed
  382. MaxFixed, // IsMaxFixed
  383. NonCacheable, // NonCacheable
  384. ReadWrite, // ReadAndWrite
  385. 0x0000000000000000, // AddressGranularity - GRA
  386. 0x0000000038000000, // AddressMinimum - MIN
  387. 0x000000003FFFFFFF, // AddressMinimum - MAX
  388. 0x0000000000000000, // AddressTranslation - TRA
  389. 0x0000000008000000 // RangeLength - LEN
  390. )
  391. QWordMemory (
  392. ResourceProducer, // ResourceUsage
  393. PosDecode, // Decode
  394. MinFixed, // IsMinFixed
  395. MaxFixed, // IsMaxFixed
  396. NonCacheable, // NonCacheable
  397. ReadWrite, // ReadAndWrite
  398. 0x0000000000000000, // AddressGranularity - GRA
  399. 0x00003C0000000000, // AddressMinimum - MIN
  400. 0x00003FFFDFFFFFFF, // AddressMaximum - MAX
  401. 0x0000000000000000, // AddressTranslation - TRA
  402. 0x000003FFE0000000 // RangeLength - LEN
  403. )
  404. })
  405. Method (_CRS, 0, Serialized) {
  406. Return (RBUF)
  407. }
  408. //
  409. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  410. //
  411. // Argments:
  412. // Arg0 A Buffer containing a UUID
  413. // Arg1 An Integer containing a Revision ID of the buffer format
  414. // Arg2 An Integer containing a count of entries in Arg3
  415. // Arg3 A Buffer containing a list of DWORD capabilities
  416. // Return Value:
  417. // A Buffer containing a list of capabilities
  418. // See the APCI spec, Section 6.2.10,
  419. // and the PCI FW spec, Section 4.5.
  420. //
  421. // The following is an example, and may need modification for
  422. // specific implementations.
  423. //
  424. Name (SUPP, 0) // PCI _OSC Support Field value
  425. Name (CTRL, 0) // PCI _OSC Control Field value
  426. Method (_OSC, 4) {
  427. //
  428. // Look for the PCI Host Bridge Interface UUID.
  429. // Section 6.2.10.3
  430. //
  431. //
  432. // Create DWord-adressable fields from the Capabilities Buffer
  433. // Create CDW1 outside the test as it's used in the else clause.
  434. //
  435. CreateDWordField (Arg3, 0, CDW1)
  436. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  437. CreateDWordField (Arg3, 4, CDW2)
  438. CreateDWordField (Arg3, 8, CDW3)
  439. //
  440. // Save Capabilities DWord 2 & 3
  441. //
  442. Store (CDW2, SUPP)
  443. Store (CDW3, CTRL)
  444. //
  445. // Only allow native hot plug control if OS supports:
  446. // ASPM
  447. // Clock PM
  448. // MSI/MSI-X
  449. //
  450. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  451. //
  452. // Mask bit 0 (and undefined bits)
  453. //
  454. And (CTRL, 0x1E, CTRL)
  455. }
  456. //
  457. // Never allow native Hot plug, PME.
  458. // Never allow SHPC (no SHPC controller in this system).
  459. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  460. // Allows PCI Express Capability Structure control
  461. //
  462. if (AERF) {
  463. And (CTRL, 0x10, CTRL)
  464. } Else {
  465. And (CTRL, 0x18, CTRL)
  466. }
  467. //
  468. // Check for unknown revision.
  469. //
  470. If (LNotEqual (Arg1, One)) {
  471. Or (CDW1, 0x08, CDW1)
  472. }
  473. //
  474. // Check if capabilities bits were masked.
  475. //
  476. If (LNotEqual (CDW3, CTRL)) {
  477. Or (CDW1, 0x10, CDW1)
  478. }
  479. //
  480. // Update DWORD3 in the buffer.
  481. //
  482. Store (CTRL, CDW3)
  483. Return (Arg3)
  484. } Else {
  485. //
  486. // Unrecognized UUID
  487. //
  488. Or (CDW1, 4, CDW1)
  489. Return (Arg3)
  490. }
  491. } // End _OSC
  492. //
  493. // Declare a _DSM method for various functions called by the OS.
  494. // See the APCI spec, Section 9.14.1,
  495. // and the PCI FW spec, Section 4.6.
  496. // See also:
  497. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  498. //
  499. Method (_DSM, 0x4, Serialized) {
  500. //
  501. // Match against the _DSM PCI GUID.
  502. //
  503. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  504. Switch (ToInteger(Arg2)) {
  505. //
  506. // Function 0: Return supported functions as a bitfield
  507. // with one bit for each supported function.
  508. // Bit 0 must always be set, as that represents
  509. // function 0 (which is what is being called here).
  510. // Support for different functions may depend on
  511. // the revision ID of the interface, passed as Arg1.
  512. //
  513. Case (0) {
  514. //
  515. // Functions 0-7 are supported.
  516. //
  517. Return (Buffer() {0x01})
  518. }
  519. }
  520. }
  521. //
  522. // If not one of the function identifiers we recognize, then return a buffer
  523. // with bit 0 set to 0 indicating no functions supported.
  524. //
  525. Return (Buffer() {0})
  526. }
  527. //
  528. // Root Port 0 Device within the Root Complex.
  529. //
  530. Device (RP0) {
  531. //
  532. // Device 0, Function 0.
  533. //
  534. Name (_ADR, 0x00000000)
  535. }
  536. Method (_PXM, 0, NotSerialized) {
  537. // Patch by code
  538. Return(0xFF)
  539. }
  540. } // PCI3 RCA3
  541. // PCI4 RCA4
  542. Device (PCI4) {
  543. //
  544. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  545. // Section 6.1.5
  546. //
  547. Name (_HID, "PNP0A08")
  548. Name (_CCA, ONE)
  549. Method (_STA, 0, NotSerialized) {
  550. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  551. // run-time patching as the representation of 0 is special
  552. // encoding and cannot be patched to expand with extra bytes
  553. // easily. As such, we default to 0xF and patch this based
  554. // on whether the port was enabled or not by the BIOS.
  555. }
  556. //
  557. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  558. // root complex for use with pre-PCIe operating systems.
  559. // Section 6.1.2
  560. //
  561. Name (_CID, "PNP0A03")
  562. //
  563. // Declare the segment number of this root complex. Most systems only
  564. // have one segment, which is numbered 0.
  565. // Section 6.5.6
  566. //
  567. Name (_SEG, 2)
  568. //
  569. // Declare the base bus number, which is the bus number of the root
  570. // bus in this root complex. This is usually 0, but need not be.
  571. // For root complexes supporting multiple root busses, this should
  572. // be the lowest numbered root bus.
  573. // Section 6.5.5
  574. //
  575. Name (_BBN, 0)
  576. //
  577. // The _UID value provides a way of uniquely identifying a device
  578. // in the case where more than one instance of a specific device
  579. // is implemented with the same _HID/_CID. For systems with a
  580. // single root complex, this is usually just 0. For systems with
  581. // multiple root complexes, this should be different for each
  582. // root complex.
  583. // Section 6.1.12
  584. //
  585. Name (_UID, "PCI4")
  586. Name (_STR, Unicode("PCIe 4 Device"))
  587. //
  588. // Declare the PCI Routing Table.
  589. // This defines SPI mappings of the four line-based interrupts
  590. // associated with the root complex and hierarchy below it.
  591. // Section 6.2.12
  592. //
  593. Name (_PRT, Package() {
  594. //
  595. // Routing for device 0, all functions.
  596. // Note: ARM doesn't support LNK nodes, so the third param
  597. // is 0 and the fourth param is the SPI number of the interrupt
  598. // line. In this example, the A/B/C/D interrupts are wired to
  599. // SPI lines 144/145/146/147 respectively. PCI4 RCA4
  600. //
  601. Package() {0x0001FFFF, 0, 0, 144},
  602. Package() {0x0001FFFF, 1, 0, 145},
  603. Package() {0x0001FFFF, 2, 0, 146},
  604. Package() {0x0001FFFF, 3, 0, 147},
  605. Package() {0x0002FFFF, 0, 0, 144},
  606. Package() {0x0002FFFF, 1, 0, 145},
  607. Package() {0x0002FFFF, 2, 0, 146},
  608. Package() {0x0002FFFF, 3, 0, 147},
  609. Package() {0x0003FFFF, 0, 0, 144},
  610. Package() {0x0003FFFF, 1, 0, 145},
  611. Package() {0x0003FFFF, 2, 0, 146},
  612. Package() {0x0003FFFF, 3, 0, 147},
  613. Package() {0x0004FFFF, 0, 0, 144},
  614. Package() {0x0004FFFF, 1, 0, 145},
  615. Package() {0x0004FFFF, 2, 0, 146},
  616. Package() {0x0004FFFF, 3, 0, 147},
  617. Package() {0x0005FFFF, 0, 0, 144},
  618. Package() {0x0005FFFF, 1, 0, 145},
  619. Package() {0x0005FFFF, 2, 0, 146},
  620. Package() {0x0005FFFF, 3, 0, 147},
  621. Package() {0x0006FFFF, 0, 0, 144},
  622. Package() {0x0006FFFF, 1, 0, 145},
  623. Package() {0x0006FFFF, 2, 0, 146},
  624. Package() {0x0006FFFF, 3, 0, 147},
  625. Package() {0x0007FFFF, 0, 0, 144},
  626. Package() {0x0007FFFF, 1, 0, 145},
  627. Package() {0x0007FFFF, 2, 0, 146},
  628. Package() {0x0007FFFF, 3, 0, 147},
  629. Package() {0x0008FFFF, 0, 0, 144},
  630. Package() {0x0008FFFF, 1, 0, 145},
  631. Package() {0x0008FFFF, 2, 0, 146},
  632. Package() {0x0008FFFF, 3, 0, 147},
  633. })
  634. //
  635. // Declare the resources assigned to this root complex.
  636. // Section 6.2.2
  637. //
  638. Method (_CBA, 0, Serialized) {
  639. Return (0x23FFF0000000)
  640. }
  641. Name (RBUF, ResourceTemplate () {
  642. //
  643. // Declare the range of bus numbers assigned to this root
  644. // complex. In this example, the minimum bus number will be
  645. // 0, the maximum bus number will be 0xFF, supporting
  646. // 256 busses total.
  647. // Section 19.5.141
  648. //
  649. WordBusNumber (
  650. ResourceProducer,
  651. MinFixed, // IsMinFixed
  652. MaxFixed, // IsMaxFixed
  653. PosDecode, // Decode
  654. 0, // AddressGranularity
  655. 0, // AddressMinimum - Minimum Bus Number
  656. 255, // AddressMaximum - Maximum Bus Number
  657. 0, // AddressTranslation - Set to 0
  658. 256) // RangeLength - Number of Busses
  659. //
  660. // Declare the memory range to be used for BAR memory
  661. // windows. This declares a 4GB region starting at
  662. // 0x4000000000.
  663. // Section 19.5.80
  664. //
  665. // Memory32Fixed (ReadWrite, 0x1FEC0000, 0x10000, )
  666. QWordMemory (
  667. ResourceProducer, // ResourceUsage
  668. PosDecode, // Decode
  669. MinFixed, // IsMinFixed
  670. MaxFixed, // IsMaxFixed
  671. NonCacheable, // NonCacheable
  672. ReadWrite, // ReadAndWrite
  673. 0x0000000000000000, // AddressGranularity - GRA
  674. 0x0000000004000000, // AddressMinimum - MIN
  675. 0x0000000007FFFFFF, // AddressMinimum - MAX
  676. 0x0000000000000000, // AddressTranslation - TRA
  677. 0x0000000004000000 // RangeLength - LEN
  678. )
  679. QWordMemory (
  680. ResourceProducer, // ResourceUsage
  681. PosDecode, // Decode
  682. MinFixed, // IsMinFixed
  683. MaxFixed, // IsMaxFixed
  684. NonCacheable, // NonCacheable
  685. ReadWrite, // ReadAndWrite
  686. 0x0000000000000000, // AddressGranularity - GRA
  687. 0x0000200000000000, // AddressMinimum - MIN
  688. 0x000023FFDFFFFFFF, // AddressMaximum - MAX
  689. 0x0000000000000000, // AddressTranslation - TRA
  690. 0x000003FFE0000000 // RangeLength - LEN
  691. )
  692. })
  693. Method (_CRS, 0, Serialized) {
  694. Return (RBUF)
  695. }
  696. //
  697. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  698. //
  699. // Argments:
  700. // Arg0 A Buffer containing a UUID
  701. // Arg1 An Integer containing a Revision ID of the buffer format
  702. // Arg2 An Integer containing a count of entries in Arg3
  703. // Arg3 A Buffer containing a list of DWORD capabilities
  704. // Return Value:
  705. // A Buffer containing a list of capabilities
  706. // See the APCI spec, Section 6.2.10,
  707. // and the PCI FW spec, Section 4.5.
  708. //
  709. // The following is an example, and may need modification for
  710. // specific implementations.
  711. //
  712. Name (SUPP,0) // PCI _OSC Support Field value
  713. Name (CTRL,0) // PCI _OSC Control Field value
  714. Method (_OSC, 4) {
  715. //
  716. // Look for the PCI Host Bridge Interface UUID.
  717. // Section 6.2.10.3
  718. //
  719. //
  720. // Create DWord-adressable fields from the Capabilities Buffer
  721. // Create CDW1 outside the test as it's used in the else clause.
  722. //
  723. CreateDWordField (Arg3, 0, CDW1)
  724. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  725. CreateDWordField (Arg3, 4, CDW2)
  726. CreateDWordField (Arg3, 8, CDW3)
  727. //
  728. // Save Capabilities DWord 2 & 3
  729. //
  730. Store (CDW2, SUPP)
  731. Store (CDW3, CTRL)
  732. //
  733. // Only allow native hot plug control if OS supports:
  734. // ASPM
  735. // Clock PM
  736. // MSI/MSI-X
  737. //
  738. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  739. //
  740. // Mask bit 0 (and undefined bits)
  741. //
  742. And (CTRL, 0x1E, CTRL)
  743. }
  744. //
  745. // Never allow native Hot plug, PME.
  746. // Never allow SHPC (no SHPC controller in this system).
  747. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  748. // Allows PCI Express Capability Structure control
  749. //
  750. if (AERF) {
  751. And (CTRL, 0x10, CTRL)
  752. } Else {
  753. And (CTRL, 0x18, CTRL)
  754. }
  755. //
  756. // Check for unknown revision.
  757. //
  758. If (LNotEqual (Arg1, One)) {
  759. Or (CDW1, 0x08, CDW1)
  760. }
  761. //
  762. // Check if capabilities bits were masked.
  763. //
  764. If (LNotEqual (CDW3, CTRL)) {
  765. Or (CDW1, 0x10, CDW1)
  766. }
  767. //
  768. // Update DWORD3 in the buffer.
  769. //
  770. Store (CTRL, CDW3)
  771. Return (Arg3)
  772. } Else {
  773. //
  774. // Unrecognized UUID
  775. //
  776. Or (CDW1, 4, CDW1)
  777. Return (Arg3)
  778. }
  779. } // End _OSC
  780. //
  781. // Declare a _DSM method for various functions called by the OS.
  782. // See the APCI spec, Section 9.14.1,
  783. // and the PCI FW spec, Section 4.6.
  784. // See also:
  785. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  786. //
  787. Method (_DSM, 0x4, Serialized) {
  788. //
  789. // Match against the _DSM PCI GUID.
  790. //
  791. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  792. Switch (ToInteger(Arg2))
  793. {
  794. //
  795. // Function 0: Return supported functions as a bitfield
  796. // with one bit for each supported function.
  797. // Bit 0 must always be set, as that represents
  798. // function 0 (which is what is being called here).
  799. // Support for different functions may depend on
  800. // the revision ID of the interface, passed as Arg1.
  801. //
  802. Case (0) {
  803. //
  804. // Functions 0-7 are supported.
  805. //
  806. Return (Buffer() {0x01})
  807. }
  808. }
  809. }
  810. //
  811. // If not one of the function identifiers we recognize, then return a buffer
  812. // with bit 0 set to 0 indicating no functions supported.
  813. //
  814. Return (Buffer() {0})
  815. }
  816. //
  817. // Root Port 0 Device within the Root Complex.
  818. //
  819. Device (RP0) {
  820. //
  821. // Device 0, Function 0.
  822. //
  823. Name (_ADR, 0x00000000)
  824. }
  825. Method (_PXM, 0, NotSerialized) {
  826. // Patch by code
  827. Return(0xFF)
  828. }
  829. } // PCI4 RCA4
  830. // PCI5 RCA5
  831. Device (PCI5) {
  832. //
  833. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  834. // Section 6.1.5
  835. //
  836. Name (_HID, "PNP0A08")
  837. Name (_CCA, ONE)
  838. Method (_STA, 0, NotSerialized) {
  839. Return (0xF)
  840. }
  841. //
  842. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  843. // root complex for use with pre-PCIe operating systems.
  844. // Section 6.1.2
  845. //
  846. Name (_CID,"PNP0A03")
  847. //
  848. // Declare the segment number of this root complex. Most systems only
  849. // have one segment, which is numbered 0.
  850. // Section 6.5.6
  851. //
  852. Name (_SEG, 3)
  853. //
  854. // Declare the base bus number, which is the bus number of the root
  855. // bus in this root complex. This is usually 0, but need not be.
  856. // For root complexes supporting multiple root busses, this should
  857. // be the lowest numbered root bus.
  858. // Section 6.5.5
  859. //
  860. Name (_BBN, 0)
  861. //
  862. // The _UID value provides a way of uniquely identifying a device
  863. // in the case where more than one instance of a specific device
  864. // is implemented with the same _HID/_CID. For systems with a
  865. // single root complex, this is usually just 0. For systems with
  866. // multiple root complexes, this should be different for each
  867. // root complex.
  868. // Section 6.1.12
  869. //
  870. Name (_UID, "PCI5")
  871. Name (_STR, Unicode("PCIe 5 Device"))
  872. //
  873. // Declare the PCI Routing Table.
  874. // This defines SPI mappings of the four line-based interrupts
  875. // associated with the root complex and hierarchy below it.
  876. // Section 6.2.12
  877. //
  878. Name (_PRT, Package() {
  879. //
  880. // Routing for device 0, all functions.
  881. // Note: ARM doesn't support LNK nodes, so the third param
  882. // is 0 and the fourth param is the SPI number of the interrupt
  883. // line. In this example, the A/B/C/D interrupts are wired to
  884. // SPI lines 148/149/150/151 respectively. PCI5 RCA5
  885. //
  886. Package() {0x0001FFFF, 0, 0, 148},
  887. Package() {0x0001FFFF, 1, 0, 149},
  888. Package() {0x0001FFFF, 2, 0, 150},
  889. Package() {0x0001FFFF, 3, 0, 151},
  890. Package() {0x0002FFFF, 0, 0, 148},
  891. Package() {0x0002FFFF, 1, 0, 149},
  892. Package() {0x0002FFFF, 2, 0, 150},
  893. Package() {0x0002FFFF, 3, 0, 151},
  894. Package() {0x0003FFFF, 0, 0, 148},
  895. Package() {0x0003FFFF, 1, 0, 149},
  896. Package() {0x0003FFFF, 2, 0, 150},
  897. Package() {0x0003FFFF, 3, 0, 151},
  898. Package() {0x0004FFFF, 0, 0, 148},
  899. Package() {0x0004FFFF, 1, 0, 149},
  900. Package() {0x0004FFFF, 2, 0, 150},
  901. Package() {0x0004FFFF, 3, 0, 151},
  902. Package() {0x0005FFFF, 0, 0, 148},
  903. Package() {0x0005FFFF, 1, 0, 149},
  904. Package() {0x0005FFFF, 2, 0, 150},
  905. Package() {0x0005FFFF, 3, 0, 151},
  906. Package() {0x0006FFFF, 0, 0, 148},
  907. Package() {0x0006FFFF, 1, 0, 149},
  908. Package() {0x0006FFFF, 2, 0, 150},
  909. Package() {0x0006FFFF, 3, 0, 151},
  910. Package() {0x0007FFFF, 0, 0, 148},
  911. Package() {0x0007FFFF, 1, 0, 149},
  912. Package() {0x0007FFFF, 2, 0, 150},
  913. Package() {0x0007FFFF, 3, 0, 151},
  914. Package() {0x0008FFFF, 0, 0, 148},
  915. Package() {0x0008FFFF, 1, 0, 149},
  916. Package() {0x0008FFFF, 2, 0, 150},
  917. Package() {0x0008FFFF, 3, 0, 151},
  918. })
  919. //
  920. // Declare the resources assigned to this root complex.
  921. // Section 6.2.2
  922. //
  923. Method (_CBA, 0, Serialized) {
  924. Return (0x27FFF0000000)
  925. }
  926. Name (RBUF, ResourceTemplate () {
  927. //
  928. // Declare the range of bus numbers assigned to this root
  929. // complex. In this example, the minimum bus number will be
  930. // 0, the maximum bus number will be 0xFF, supporting
  931. // 256 busses total.
  932. // Section 19.5.141
  933. //
  934. WordBusNumber (
  935. ResourceProducer,
  936. MinFixed, // IsMinFixed
  937. MaxFixed, // IsMaxFixed
  938. PosDecode, // Decode
  939. 0, // AddressGranularity
  940. 0, // AddressMinimum - Minimum Bus Number
  941. 255, // AddressMaximum - Maximum Bus Number
  942. 0, // AddressTranslation - Set to 0
  943. 256) // RangeLength - Number of Busses
  944. //
  945. // Declare the memory range to be used for BAR memory
  946. // windows. This declares a 4GB region starting at
  947. // 0x4000000000.
  948. // Section 19.5.80
  949. //
  950. // Memory32Fixed (ReadWrite, 0x1FF00000, 0x10000, )
  951. QWordMemory (
  952. ResourceProducer, // ResourceUsage
  953. PosDecode, // Decode
  954. MinFixed, // IsMinFixed
  955. MaxFixed, // IsMaxFixed
  956. NonCacheable, // NonCacheable
  957. ReadWrite, // ReadAndWrite
  958. 0x0000000000000000, // AddressGranularity - GRA
  959. 0x0000000008000000, // AddressMinimum - MIN
  960. 0x000000000FFFFFFF, // AddressMinimum - MAX
  961. 0x0000000000000000, // AddressTranslation - TRA
  962. 0x0000000008000000 // RangeLength - LEN
  963. )
  964. QWordMemory (
  965. ResourceProducer, // ResourceUsage
  966. PosDecode, // Decode
  967. MinFixed, // IsMinFixed
  968. MaxFixed, // IsMaxFixed
  969. NonCacheable, // NonCacheable
  970. ReadWrite, // ReadAndWrite
  971. 0x0000000000000000, // AddressGranularity - GRA
  972. 0x0000240000000000, // AddressMinimum - MIN
  973. 0x000027FFDFFFFFFF, // AddressMaximum - MAX
  974. 0x0000000000000000, // AddressTranslation - TRA
  975. 0x000003FFE0000000 // RangeLength - LEN
  976. )
  977. })
  978. Method (_CRS, 0, Serialized) {
  979. Return (RBUF)
  980. }
  981. //
  982. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  983. //
  984. // Argments:
  985. // Arg0 A Buffer containing a UUID
  986. // Arg1 An Integer containing a Revision ID of the buffer format
  987. // Arg2 An Integer containing a count of entries in Arg3
  988. // Arg3 A Buffer containing a list of DWORD capabilities
  989. // Return Value:
  990. // A Buffer containing a list of capabilities
  991. // See the APCI spec, Section 6.2.10,
  992. // and the PCI FW spec, Section 4.5.
  993. //
  994. // The following is an example, and may need modification for
  995. // specific implementations.
  996. //
  997. Name (SUPP, 0) // PCI _OSC Support Field value
  998. Name (CTRL, 0) // PCI _OSC Control Field value
  999. Method (_OSC, 4) {
  1000. //
  1001. // Look for the PCI Host Bridge Interface UUID.
  1002. // Section 6.2.10.3
  1003. //
  1004. //
  1005. // Create DWord-adressable fields from the Capabilities Buffer
  1006. // Create CDW1 outside the test as it's used in the else clause.
  1007. //
  1008. CreateDWordField (Arg3, 0, CDW1)
  1009. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1010. CreateDWordField (Arg3, 4, CDW2)
  1011. CreateDWordField (Arg3, 8, CDW3)
  1012. //
  1013. // Save Capabilities DWord 2 & 3
  1014. //
  1015. Store (CDW2, SUPP)
  1016. Store (CDW3, CTRL)
  1017. //
  1018. // Only allow native hot plug control if OS supports:
  1019. // ASPM
  1020. // Clock PM
  1021. // MSI/MSI-X
  1022. //
  1023. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1024. //
  1025. // Mask bit 0 (and undefined bits)
  1026. //
  1027. And (CTRL, 0x1E, CTRL)
  1028. }
  1029. //
  1030. // Never allow native Hot plug, PME.
  1031. // Never allow SHPC (no SHPC controller in this system).
  1032. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1033. // Allows PCI Express Capability Structure control
  1034. //
  1035. if (AERF) {
  1036. And (CTRL, 0x10, CTRL)
  1037. } Else {
  1038. And (CTRL, 0x18, CTRL)
  1039. }
  1040. //
  1041. // Check for unknown revision.
  1042. //
  1043. If (LNotEqual (Arg1, One)) {
  1044. Or (CDW1, 0x08, CDW1)
  1045. }
  1046. //
  1047. // Check if capabilities bits were masked.
  1048. //
  1049. If (LNotEqual (CDW3, CTRL)) {
  1050. Or (CDW1, 0x10, CDW1)
  1051. }
  1052. //
  1053. // Update DWORD3 in the buffer.
  1054. //
  1055. Store (CTRL, CDW3)
  1056. Return (Arg3)
  1057. } Else {
  1058. //
  1059. // Unrecognized UUID
  1060. //
  1061. Or (CDW1, 4, CDW1)
  1062. Return (Arg3)
  1063. }
  1064. } // End _OSC
  1065. //
  1066. // Declare a _DSM method for various functions called by the OS.
  1067. // See the APCI spec, Section 9.14.1,
  1068. // and the PCI FW spec, Section 4.6.
  1069. // See also:
  1070. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1071. //
  1072. Method (_DSM, 0x4, Serialized) {
  1073. //
  1074. // Match against the _DSM PCI GUID.
  1075. //
  1076. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1077. Switch (ToInteger(Arg2))
  1078. {
  1079. //
  1080. // Function 0: Return supported functions as a bitfield
  1081. // with one bit for each supported function.
  1082. // Bit 0 must always be set, as that represents
  1083. // function 0 (which is what is being called here).
  1084. // Support for different functions may depend on
  1085. // the revision ID of the interface, passed as Arg1.
  1086. //
  1087. Case (0) {
  1088. //
  1089. // Functions 0-7 are supported.
  1090. //
  1091. Return (Buffer() {0x01})
  1092. }
  1093. }
  1094. }
  1095. //
  1096. // If not one of the function identifiers we recognize, then return a buffer
  1097. // with bit 0 set to 0 indicating no functions supported.
  1098. //
  1099. Return (Buffer() {0})
  1100. }
  1101. //
  1102. // Root Port 0 Device within the Root Complex.
  1103. //
  1104. Device (RP0) {
  1105. //
  1106. // Device 0, Function 0.
  1107. //
  1108. Name (_ADR, 0x00000000)
  1109. }
  1110. Method (_PXM, 0, NotSerialized) {
  1111. // Patch by code
  1112. Return(0xFF)
  1113. }
  1114. } // PCI5 RCA5
  1115. // PCI6 RCA6
  1116. Device (PCI6) {
  1117. //
  1118. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  1119. // Section 6.1.5
  1120. //
  1121. Name (_HID,"PNP0A08")
  1122. Name (_CCA, ONE)
  1123. Method (_STA, 0, NotSerialized) {
  1124. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  1125. // run-time patching as the representation of 0 is special
  1126. // encoding and cannot be patched to expand with extra bytes
  1127. // easily. As such, we default to 0xF and patch this based
  1128. // on whether the port was enabled or not by the BIOS.
  1129. }
  1130. //
  1131. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  1132. // root complex for use with pre-PCIe operating systems.
  1133. // Section 6.1.2
  1134. //
  1135. Name (_CID,"PNP0A03")
  1136. //
  1137. // Declare the segment number of this root complex. Most systems only
  1138. // have one segment, which is numbered 0.
  1139. // Section 6.5.6
  1140. //
  1141. Name (_SEG, 4)
  1142. //
  1143. // Declare the base bus number, which is the bus number of the root
  1144. // bus in this root complex. This is usually 0, but need not be.
  1145. // For root complexes supporting multiple root busses, this should
  1146. // be the lowest numbered root bus.
  1147. // Section 6.5.5
  1148. //
  1149. Name (_BBN, 0)
  1150. //
  1151. // The _UID value provides a way of uniquely identifying a device
  1152. // in the case where more than one instance of a specific device
  1153. // is implemented with the same _HID/_CID. For systems with a
  1154. // single root complex, this is usually just 0. For systems with
  1155. // multiple root complexes, this should be different for each
  1156. // root complex.
  1157. // Section 6.1.12
  1158. //
  1159. Name (_UID, "PCI6")
  1160. Name (_STR, Unicode("PCIe 6 Device"))
  1161. //
  1162. // Declare the PCI Routing Table.
  1163. // This defines SPI mappings of the four line-based interrupts
  1164. // associated with the root complex and hierarchy below it.
  1165. // Section 6.2.12
  1166. //
  1167. Name (_PRT, Package() {
  1168. //
  1169. // Routing for device 0, all functions.
  1170. // Note: ARM doesn't support LNK nodes, so the third param
  1171. // is 0 and the fourth param is the SPI number of the interrupt
  1172. // line. In this example, the A/B/C/D interrupts are wired to
  1173. // SPI lines 152/153/154/155 respectively. PCI6 RCA6
  1174. //
  1175. Package() {0x0001FFFF, 0, 0, 152},
  1176. Package() {0x0001FFFF, 1, 0, 153},
  1177. Package() {0x0001FFFF, 2, 0, 154},
  1178. Package() {0x0001FFFF, 3, 0, 155},
  1179. Package() {0x0002FFFF, 0, 0, 152},
  1180. Package() {0x0002FFFF, 1, 0, 153},
  1181. Package() {0x0002FFFF, 2, 0, 154},
  1182. Package() {0x0002FFFF, 3, 0, 155},
  1183. Package() {0x0003FFFF, 0, 0, 152},
  1184. Package() {0x0003FFFF, 1, 0, 153},
  1185. Package() {0x0003FFFF, 2, 0, 154},
  1186. Package() {0x0003FFFF, 3, 0, 155},
  1187. Package() {0x0004FFFF, 0, 0, 152},
  1188. Package() {0x0004FFFF, 1, 0, 153},
  1189. Package() {0x0004FFFF, 2, 0, 154},
  1190. Package() {0x0004FFFF, 3, 0, 155},
  1191. Package() {0x0005FFFF, 0, 0, 152},
  1192. Package() {0x0005FFFF, 1, 0, 153},
  1193. Package() {0x0005FFFF, 2, 0, 154},
  1194. Package() {0x0005FFFF, 3, 0, 155},
  1195. Package() {0x0006FFFF, 0, 0, 152},
  1196. Package() {0x0006FFFF, 1, 0, 153},
  1197. Package() {0x0006FFFF, 2, 0, 154},
  1198. Package() {0x0006FFFF, 3, 0, 155},
  1199. Package() {0x0007FFFF, 0, 0, 152},
  1200. Package() {0x0007FFFF, 1, 0, 153},
  1201. Package() {0x0007FFFF, 2, 0, 154},
  1202. Package() {0x0007FFFF, 3, 0, 155},
  1203. Package() {0x0008FFFF, 0, 0, 152},
  1204. Package() {0x0008FFFF, 1, 0, 153},
  1205. Package() {0x0008FFFF, 2, 0, 154},
  1206. Package() {0x0008FFFF, 3, 0, 155},
  1207. })
  1208. //
  1209. // Declare the resources assigned to this root complex.
  1210. // Section 6.2.2
  1211. //
  1212. Method (_CBA, 0, Serialized) {
  1213. Return (0x2BFFF0000000)
  1214. }
  1215. Name (RBUF, ResourceTemplate () {
  1216. //
  1217. // Declare the range of bus numbers assigned to this root
  1218. // complex. In this example, the minimum bus number will be
  1219. // 0, the maximum bus number will be 0xFF, supporting
  1220. // 256 busses total.
  1221. // Section 19.5.141
  1222. //
  1223. WordBusNumber (
  1224. ResourceProducer,
  1225. MinFixed, // IsMinFixed
  1226. MaxFixed, // IsMaxFixed
  1227. PosDecode, // Decode
  1228. 0, // AddressGranularity
  1229. 0, // AddressMinimum - Minimum Bus Number
  1230. 255, // AddressMaximum - Maximum Bus Number
  1231. 0, // AddressTranslation - Set to 0
  1232. 256) // RangeLength - Number of Busses
  1233. //
  1234. // Declare the memory range to be used for BAR memory
  1235. // windows. This declares a 4GB region starting at
  1236. // 0x4000000000.
  1237. // Section 19.5.80
  1238. //
  1239. // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, )
  1240. QWordMemory (
  1241. ResourceProducer, // ResourceUsage
  1242. PosDecode, // Decode
  1243. MinFixed, // IsMinFixed
  1244. MaxFixed, // IsMaxFixed
  1245. NonCacheable, // NonCacheable
  1246. ReadWrite, // ReadAndWrite
  1247. 0x0000000000000000, // AddressGranularity - GRA
  1248. 0x0000000010000000, // AddressMinimum - MIN
  1249. 0x0000000017FFFFFF, // AddressMinimum - MAX
  1250. 0x0000000000000000, // AddressTranslation - TRA
  1251. 0x0000000008000000 // RangeLength - LEN
  1252. )
  1253. QWordMemory (
  1254. ResourceProducer, // ResourceUsage
  1255. PosDecode, // Decode
  1256. MinFixed, // IsMinFixed
  1257. MaxFixed, // IsMaxFixed
  1258. NonCacheable, // NonCacheable
  1259. ReadWrite, // ReadAndWrite
  1260. 0x0000000000000000, // AddressGranularity - GRA
  1261. 0x0000280000000000, // AddressMinimum - MIN
  1262. 0x00002BFFDFFFFFFF, // AddressMaximum - MAX
  1263. 0x0000000000000000, // AddressTranslation - TRA
  1264. 0x000003FFE0000000 // RangeLength - LEN
  1265. )
  1266. })
  1267. Method (_CRS, 0, Serialized) {
  1268. Return (RBUF)
  1269. }
  1270. //
  1271. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  1272. //
  1273. // Argments:
  1274. // Arg0 A Buffer containing a UUID
  1275. // Arg1 An Integer containing a Revision ID of the buffer format
  1276. // Arg2 An Integer containing a count of entries in Arg3
  1277. // Arg3 A Buffer containing a list of DWORD capabilities
  1278. // Return Value:
  1279. // A Buffer containing a list of capabilities
  1280. // See the APCI spec, Section 6.2.10,
  1281. // and the PCI FW spec, Section 4.5.
  1282. //
  1283. // The following is an example, and may need modification for
  1284. // specific implementations.
  1285. //
  1286. Name (SUPP,0) // PCI _OSC Support Field value
  1287. Name (CTRL,0) // PCI _OSC Control Field value
  1288. Method (_OSC, 4) {
  1289. //
  1290. // Look for the PCI Host Bridge Interface UUID.
  1291. // Section 6.2.10.3
  1292. //
  1293. //
  1294. // Create DWord-adressable fields from the Capabilities Buffer
  1295. // Create CDW1 outside the test as it's used in the else clause.
  1296. //
  1297. CreateDWordField (Arg3,0,CDW1)
  1298. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1299. CreateDWordField (Arg3,4,CDW2)
  1300. CreateDWordField (Arg3,8,CDW3)
  1301. //
  1302. // Save Capabilities DWord 2 & 3
  1303. //
  1304. Store (CDW2,SUPP)
  1305. Store (CDW3,CTRL)
  1306. //
  1307. // Only allow native hot plug control if OS supports:
  1308. // ASPM
  1309. // Clock PM
  1310. // MSI/MSI-X
  1311. //
  1312. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1313. //
  1314. // Mask bit 0 (and undefined bits)
  1315. //
  1316. And (CTRL,0x1E,CTRL)
  1317. }
  1318. //
  1319. // Never allow native Hot plug, PME.
  1320. // Never allow SHPC (no SHPC controller in this system).
  1321. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1322. // Allows PCI Express Capability Structure control
  1323. //
  1324. if (AERF) {
  1325. And (CTRL, 0x10, CTRL)
  1326. } Else {
  1327. And (CTRL, 0x18, CTRL)
  1328. }
  1329. //
  1330. // Check for unknown revision.
  1331. //
  1332. If (LNotEqual (Arg1,One)) {
  1333. Or (CDW1,0x08,CDW1)
  1334. }
  1335. //
  1336. // Check if capabilities bits were masked.
  1337. //
  1338. If (LNotEqual (CDW3,CTRL)) {
  1339. Or (CDW1,0x10,CDW1)
  1340. }
  1341. //
  1342. // Update DWORD3 in the buffer.
  1343. //
  1344. Store (CTRL,CDW3)
  1345. Return (Arg3)
  1346. } Else {
  1347. //
  1348. // Unrecognized UUID
  1349. //
  1350. Or (CDW1,4,CDW1)
  1351. Return (Arg3)
  1352. }
  1353. } // End _OSC
  1354. //
  1355. // Declare a _DSM method for various functions called by the OS.
  1356. // See the APCI spec, Section 9.14.1,
  1357. // and the PCI FW spec, Section 4.6.
  1358. // See also:
  1359. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1360. //
  1361. Method (_DSM, 0x4, Serialized) {
  1362. //
  1363. // Match against the _DSM PCI GUID.
  1364. //
  1365. If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1366. Switch (ToInteger(Arg2)) {
  1367. //
  1368. // Function 0: Return supported functions as a bitfield
  1369. // with one bit for each supported function.
  1370. // Bit 0 must always be set, as that represents
  1371. // function 0 (which is what is being called here).
  1372. // Support for different functions may depend on
  1373. // the revision ID of the interface, passed as Arg1.
  1374. //
  1375. Case (0) {
  1376. //
  1377. // Functions 0-7 are supported.
  1378. //
  1379. Return (Buffer() {0x01})
  1380. }
  1381. }
  1382. }
  1383. //
  1384. // If not one of the function identifiers we recognize, then return a buffer
  1385. // with bit 0 set to 0 indicating no functions supported.
  1386. //
  1387. Return (Buffer() {0})
  1388. }
  1389. //
  1390. // Root Port 0 Device within the Root Complex.
  1391. //
  1392. Device (RP0) {
  1393. //
  1394. // Device 0, Function 0.
  1395. //
  1396. Name (_ADR, 0x00000000)
  1397. }
  1398. Method (_PXM, 0, NotSerialized) {
  1399. // Patch by code
  1400. Return(0xFF)
  1401. }
  1402. } // PCI6 RCA6
  1403. // PCI7 RCA7
  1404. Device (PCI7) {
  1405. //
  1406. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  1407. // Section 6.1.5
  1408. //
  1409. Name (_HID,"PNP0A08")
  1410. Name (_CCA, ONE)
  1411. Method (_STA, 0, NotSerialized) {
  1412. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  1413. // run-time patching as the representation of 0 is special
  1414. // encoding and cannot be patched to expand with extra bytes
  1415. // easily. As such, we default to 0xF and patch this based
  1416. // on whether the port was enabled or not by the BIOS.
  1417. }
  1418. //
  1419. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  1420. // root complex for use with pre-PCIe operating systems.
  1421. // Section 6.1.2
  1422. //
  1423. Name (_CID,"PNP0A03")
  1424. //
  1425. // Declare the segment number of this root complex. Most systems only
  1426. // have one segment, which is numbered 0.
  1427. // Section 6.5.6
  1428. //
  1429. Name (_SEG, 5)
  1430. //
  1431. // Declare the base bus number, which is the bus number of the root
  1432. // bus in this root complex. This is usually 0, but need not be.
  1433. // For root complexes supporting multiple root busses, this should
  1434. // be the lowest numbered root bus.
  1435. // Section 6.5.5
  1436. //
  1437. Name (_BBN, 0)
  1438. //
  1439. // The _UID value provides a way of uniquely identifying a device
  1440. // in the case where more than one instance of a specific device
  1441. // is implemented with the same _HID/_CID. For systems with a
  1442. // single root complex, this is usually just 0. For systems with
  1443. // multiple root complexes, this should be different for each
  1444. // root complex.
  1445. // Section 6.1.12
  1446. //
  1447. Name (_UID, "PCI7")
  1448. Name (_STR, Unicode("PCIe 7 Device"))
  1449. //
  1450. // Declare the PCI Routing Table.
  1451. // This defines SPI mappings of the four line-based interrupts
  1452. // associated with the root complex and hierarchy below it.
  1453. // Section 6.2.12
  1454. //
  1455. Name (_PRT, Package() {
  1456. //
  1457. // Routing for device 0, all functions.
  1458. // Note: ARM doesn't support LNK nodes, so the third param
  1459. // is 0 and the fourth param is the SPI number of the interrupt
  1460. // line. In this example, the A/B/C/D interrupts are wired to
  1461. // SPI lines 156/157/158/159 respectively. PCI7 RCA7
  1462. //
  1463. Package() {0x0001FFFF, 0, 0, 156},
  1464. Package() {0x0001FFFF, 1, 0, 157},
  1465. Package() {0x0001FFFF, 2, 0, 158},
  1466. Package() {0x0001FFFF, 3, 0, 159},
  1467. Package() {0x0002FFFF, 0, 0, 156},
  1468. Package() {0x0002FFFF, 1, 0, 157},
  1469. Package() {0x0002FFFF, 2, 0, 158},
  1470. Package() {0x0002FFFF, 3, 0, 159},
  1471. Package() {0x0003FFFF, 0, 0, 156},
  1472. Package() {0x0003FFFF, 1, 0, 157},
  1473. Package() {0x0003FFFF, 2, 0, 158},
  1474. Package() {0x0003FFFF, 3, 0, 159},
  1475. Package() {0x0004FFFF, 0, 0, 156},
  1476. Package() {0x0004FFFF, 1, 0, 157},
  1477. Package() {0x0004FFFF, 2, 0, 158},
  1478. Package() {0x0004FFFF, 3, 0, 159},
  1479. Package() {0x0005FFFF, 0, 0, 156},
  1480. Package() {0x0005FFFF, 1, 0, 157},
  1481. Package() {0x0005FFFF, 2, 0, 158},
  1482. Package() {0x0005FFFF, 3, 0, 159},
  1483. Package() {0x0006FFFF, 0, 0, 156},
  1484. Package() {0x0006FFFF, 1, 0, 157},
  1485. Package() {0x0006FFFF, 2, 0, 158},
  1486. Package() {0x0006FFFF, 3, 0, 159},
  1487. Package() {0x0007FFFF, 0, 0, 156},
  1488. Package() {0x0007FFFF, 1, 0, 157},
  1489. Package() {0x0007FFFF, 2, 0, 158},
  1490. Package() {0x0007FFFF, 3, 0, 159},
  1491. Package() {0x0008FFFF, 0, 0, 156},
  1492. Package() {0x0008FFFF, 1, 0, 157},
  1493. Package() {0x0008FFFF, 2, 0, 158},
  1494. Package() {0x0008FFFF, 3, 0, 159},
  1495. })
  1496. //
  1497. // Declare the resources assigned to this root complex.
  1498. // Section 6.2.2
  1499. //
  1500. Method (_CBA, 0, Serialized) {
  1501. Return (0x2FFFF0000000)
  1502. }
  1503. Name (RBUF, ResourceTemplate () {
  1504. //
  1505. // Declare the range of bus numbers assigned to this root
  1506. // complex. In this example, the minimum bus number will be
  1507. // 0, the maximum bus number will be 0xFF, supporting
  1508. // 256 busses total.
  1509. // Section 19.5.141
  1510. //
  1511. WordBusNumber (
  1512. ResourceProducer,
  1513. MinFixed, // IsMinFixed
  1514. MaxFixed, // IsMaxFixed
  1515. PosDecode, // Decode
  1516. 0, // AddressGranularity
  1517. 0, // AddressMinimum - Minimum Bus Number
  1518. 255, // AddressMaximum - Maximum Bus Number
  1519. 0, // AddressTranslation - Set to 0
  1520. 256) // RangeLength - Number of Busses
  1521. //
  1522. // Declare the memory range to be used for BAR memory
  1523. // windows. This declares a 4GB region starting at
  1524. // 0x4000000000.
  1525. // Section 19.5.80
  1526. //
  1527. // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, )
  1528. QWordMemory (
  1529. ResourceProducer, // ResourceUsage
  1530. PosDecode, // Decode
  1531. MinFixed, // IsMinFixed
  1532. MaxFixed, // IsMaxFixed
  1533. NonCacheable, // NonCacheable
  1534. ReadWrite, // ReadAndWrite
  1535. 0x0000000000000000, // AddressGranularity - GRA
  1536. 0x0000000018000000, // AddressMinimum - MIN
  1537. 0x000000001FFFFFFF, // AddressMinimum - MAX
  1538. 0x0000000000000000, // AddressTranslation - TRA
  1539. 0x0000000008000000 // RangeLength - LEN
  1540. )
  1541. QWordMemory (
  1542. ResourceProducer, // ResourceUsage
  1543. PosDecode, // Decode
  1544. MinFixed, // IsMinFixed
  1545. MaxFixed, // IsMaxFixed
  1546. NonCacheable, // NonCacheable
  1547. ReadWrite, // ReadAndWrite
  1548. 0x0000000000000000, // AddressGranularity - GRA
  1549. 0x00002C0000000000, // AddressMinimum - MIN
  1550. 0x00002FFFDFFFFFFF, // AddressMaximum - MAX
  1551. 0x0000000000000000, // AddressTranslation - TRA
  1552. 0x000003FFE0000000 // RangeLength - LEN
  1553. )
  1554. })
  1555. Method (_CRS, 0, Serialized) {
  1556. Return (RBUF)
  1557. }
  1558. //
  1559. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  1560. //
  1561. // Argments:
  1562. // Arg0 A Buffer containing a UUID
  1563. // Arg1 An Integer containing a Revision ID of the buffer format
  1564. // Arg2 An Integer containing a count of entries in Arg3
  1565. // Arg3 A Buffer containing a list of DWORD capabilities
  1566. // Return Value:
  1567. // A Buffer containing a list of capabilities
  1568. // See the APCI spec, Section 6.2.10,
  1569. // and the PCI FW spec, Section 4.5.
  1570. //
  1571. // The following is an example, and may need modification for
  1572. // specific implementations.
  1573. //
  1574. Name (SUPP,0) // PCI _OSC Support Field value
  1575. Name (CTRL,0) // PCI _OSC Control Field value
  1576. Method (_OSC, 4) {
  1577. //
  1578. // Look for the PCI Host Bridge Interface UUID.
  1579. // Section 6.2.10.3
  1580. //
  1581. //
  1582. // Create DWord-adressable fields from the Capabilities Buffer
  1583. // Create CDW1 outside the test as it's used in the else clause.
  1584. //
  1585. CreateDWordField (Arg3,0,CDW1)
  1586. If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  1587. CreateDWordField (Arg3,4,CDW2)
  1588. CreateDWordField (Arg3,8,CDW3)
  1589. //
  1590. // Save Capabilities DWord 2 & 3
  1591. //
  1592. Store (CDW2,SUPP)
  1593. Store (CDW3,CTRL)
  1594. //
  1595. // Only allow native hot plug control if OS supports:
  1596. // ASPM
  1597. // Clock PM
  1598. // MSI/MSI-X
  1599. //
  1600. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  1601. //
  1602. // Mask bit 0 (and undefined bits)
  1603. //
  1604. And (CTRL,0x1E,CTRL)
  1605. }
  1606. //
  1607. // Never allow native Hot plug, PME.
  1608. // Never allow SHPC (no SHPC controller in this system).
  1609. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  1610. // Allows PCI Express Capability Structure control
  1611. //
  1612. if (AERF) {
  1613. And (CTRL, 0x10, CTRL)
  1614. } Else {
  1615. And (CTRL, 0x18, CTRL)
  1616. }
  1617. //
  1618. // Check for unknown revision.
  1619. //
  1620. If (LNotEqual (Arg1,One)) {
  1621. Or (CDW1,0x08,CDW1)
  1622. }
  1623. //
  1624. // Check if capabilities bits were masked.
  1625. //
  1626. If (LNotEqual (CDW3,CTRL)) {
  1627. Or (CDW1,0x10,CDW1)
  1628. }
  1629. //
  1630. // Update DWORD3 in the buffer.
  1631. //
  1632. Store (CTRL,CDW3)
  1633. Return (Arg3)
  1634. } Else {
  1635. //
  1636. // Unrecognized UUID
  1637. //
  1638. Or (CDW1,4,CDW1)
  1639. Return (Arg3)
  1640. }
  1641. } // End _OSC
  1642. //
  1643. // Declare a _DSM method for various functions called by the OS.
  1644. // See the APCI spec, Section 9.14.1,
  1645. // and the PCI FW spec, Section 4.6.
  1646. // See also:
  1647. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  1648. //
  1649. Method (_DSM, 0x4, Serialized) {
  1650. //
  1651. // Match against the _DSM PCI GUID.
  1652. //
  1653. If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  1654. Switch (ToInteger(Arg2)) {
  1655. //
  1656. // Function 0: Return supported functions as a bitfield
  1657. // with one bit for each supported function.
  1658. // Bit 0 must always be set, as that represents
  1659. // function 0 (which is what is being called here).
  1660. // Support for different functions may depend on
  1661. // the revision ID of the interface, passed as Arg1.
  1662. //
  1663. Case (0) {
  1664. //
  1665. // Functions 0-7 are supported.
  1666. //
  1667. Return (Buffer() {0x01})
  1668. }
  1669. }
  1670. }
  1671. //
  1672. // If not one of the function identifiers we recognize, then return a buffer
  1673. // with bit 0 set to 0 indicating no functions supported.
  1674. //
  1675. Return (Buffer() {0})
  1676. }
  1677. //
  1678. // Root Port 0 Device within the Root Complex.
  1679. //
  1680. Device (RP0) {
  1681. //
  1682. // Device 0, Function 0.
  1683. //
  1684. Name (_ADR, 0x00000000)
  1685. }
  1686. Method (_PXM, 0, NotSerialized) {
  1687. // Patch by code
  1688. Return(0xFF)
  1689. }
  1690. } // PCI7 RCA7