SsdtEvents.asl 3.7 KB

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  1. /** @file
  2. Secondary System Description Table (SSDT) for hardware reduced events.
  3. Arm Reference Design platforms implement the HW-Reduced ACPI model and do not
  4. support legacy ACPI Fixed Hardware interfaces.
  5. GPIO Signalled ACPI event is one of the methods for signalling events in
  6. HW-Reduced ACPI model. In this method, ACPI events can be signaled when a GPIO
  7. Interrupt is received by OSPM and that GPIO Interrupt Connection is listed in
  8. a GPIO controller device’s _AEI object.
  9. Interrupt Signalled ACPI event is another method of signalling events in
  10. HW-Reduced ACPI model. In this method, ACPI event is generated when an
  11. interrupt is received by the OSPM which is listed in the Generic Event Device
  12. (GED) _CRS object.
  13. Copyright (c) 2021, ARM Limited. All rights reserved.
  14. SPDX-License-Identifier: BSD-2-Clause-Patent
  15. @par Specification Reference:
  16. - ACPI 6.4, Chapter 5.6.5, GPIO-signaled ACPI Events
  17. - Arm Base Boot Requirements 1.0, Issue F, Chapter 8.5.3, GPIO controllers
  18. - ACPI 6.4, Chapter 5.6.9, Interrupt-signaled ACPI events
  19. - Arm Base Boot Requirements 1.0, Issue F, Chapter 8.5.4 Generic Event
  20. Devices
  21. **/
  22. #include "SgiAcpiHeader.h"
  23. DefinitionBlock("SsdtEvent.aml", "SSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) {
  24. /* GPIO Controller 0 device. Use _AEI object to configure pin 0 for
  25. signalling HW-Reduced events and the _L00 method to handle the event
  26. generated by pin 0.
  27. */
  28. Device (\_SB.GPI0)
  29. {
  30. Name (_HID, "ARMH0061") /* PrimeCell GPIO */
  31. Name (_UID, 0)
  32. /* Resource setting for GPIO controller 0 */
  33. Name (_CRS, ResourceTemplate () {
  34. Memory32Fixed (
  35. ReadWrite,
  36. FixedPcdGet32 (PcdGpioController0BaseAddress),
  37. FixedPcdGet32 (PcdGpioController0Size)
  38. )
  39. Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
  40. FixedPcdGet32 (PcdGpioController0Interrupt)
  41. }
  42. })
  43. /* ACPI Event information for GPIO controller 0 */
  44. Name (_AEI, ResourceTemplate() {
  45. GpioInt (Level, ActiveHigh, Exclusive, PullDown, , "\\_SB.GPI0") {0}
  46. })
  47. /* Event handler for pin0 */
  48. Method (_L00) {
  49. Printf ("GPIO0 Pin0 Toggled")
  50. Store (1, INC0)
  51. }
  52. /* Mapping for interrupt clear register */
  53. OperationRegion (
  54. GIO0,
  55. SystemMemory,
  56. FixedPcdGet32 (PcdGpioController0BaseAddress),
  57. FixedPcdGet32 (PcdGpioController0Size)
  58. )
  59. Field (GIO0, ByteAcc, NoLock, Preserve) {
  60. Offset (0x41C), /* WO Intr clear on writing 1 to resp bit */
  61. INC0, 8
  62. }
  63. }
  64. /* ACPI GED object Template. Arm's reference design platforms include a SP804
  65. dual timer which is implemented as part of the RoS sub-system. The SP804
  66. interrupt is used in GED as interrupt source. */
  67. Device (\_SB.GED0) {
  68. Name (_HID, "ACPI0013")
  69. Name (_UID, 0)
  70. /* Resource setting for GED */
  71. Name (_CRS, ResourceTemplate () {
  72. Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
  73. FixedPcdGet32 (PcdSp804DualTimerInterrupt)
  74. }
  75. })
  76. Method (_STA, 0x0, NotSerialized) {
  77. return (0xF);
  78. }
  79. /* Register map for interrupt clear register */
  80. OperationRegion (
  81. DTIM,
  82. SystemMemory,
  83. FixedPcdGet32 (PcdSp804DualTimerBaseAddress),
  84. FixedPcdGet32 (PcdSp804DualTimerSize))
  85. Field (DTIM, DWordAcc, NoLock, Preserve) {
  86. Offset (0x0C),
  87. T1IC, 32, /* 0x0C Timer 1 Interrupt clear */
  88. }
  89. /* GED event handler */
  90. Method (_EVT, 1, Serialized) {
  91. switch (ToInteger (Arg0))
  92. {
  93. case (FixedPcdGet32 (PcdSp804DualTimerInterrupt)) {
  94. Store (0x01, T1IC)
  95. }
  96. }
  97. }
  98. } /* Device (\_SB.GED0) */
  99. }