PciHostBridgeLib.c 13 KB

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  1. /** @file
  2. SIMICS QSP's instance of the PCI Host Bridge Library.
  3. Copyright (C) 2016, Red Hat, Inc.
  4. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <PiDxe.h>
  8. #include <IndustryStandard/Pci.h>
  9. #include <Register/X58Ich10.h>
  10. #include <Protocol/PciHostBridgeResourceAllocation.h>
  11. #include <Protocol/PciRootBridgeIo.h>
  12. #include <Library/BaseMemoryLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/DevicePathLib.h>
  15. #include <Library/MemoryAllocationLib.h>
  16. #include <Library/PciHostBridgeLib.h>
  17. #include <Library/PciLib.h>
  18. #include "PciHostBridge.h"
  19. #pragma pack(1)
  20. typedef struct {
  21. ACPI_HID_DEVICE_PATH AcpiDevicePath;
  22. EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
  23. } OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH;
  24. #pragma pack ()
  25. GLOBAL_REMOVE_IF_UNREFERENCED
  26. CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
  27. L"Mem", L"I/O", L"Bus"
  28. };
  29. STATIC
  30. CONST
  31. OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
  32. {
  33. {
  34. ACPI_DEVICE_PATH,
  35. ACPI_DP,
  36. {
  37. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  38. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  39. }
  40. },
  41. EISA_PNP_ID(0x0A03), // HID
  42. 0 // UID
  43. },
  44. {
  45. END_DEVICE_PATH_TYPE,
  46. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  47. {
  48. END_DEVICE_PATH_LENGTH,
  49. 0
  50. }
  51. }
  52. };
  53. STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };
  54. /**
  55. Initialize a PCI_ROOT_BRIDGE structure.
  56. @param[in] Supports Supported attributes.
  57. @param[in] Attributes Initial attributes.
  58. @param[in] AllocAttributes Allocation attributes.
  59. @param[in] RootBusNumber The bus number to store in RootBus.
  60. @param[in] MaxSubBusNumber The inclusive maximum bus number that can be
  61. assigned to any subordinate bus found behind any
  62. PCI bridge hanging off this root bus.
  63. The caller is repsonsible for ensuring that
  64. RootBusNumber <= MaxSubBusNumber. If
  65. RootBusNumber equals MaxSubBusNumber, then the
  66. root bus has no room for subordinate buses.
  67. @param[in] Io IO aperture.
  68. @param[in] Mem MMIO aperture.
  69. @param[in] MemAbove4G MMIO aperture above 4G.
  70. @param[in] PMem Prefetchable MMIO aperture.
  71. @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
  72. @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
  73. caller) that should be filled in by this
  74. function.
  75. @retval EFI_SUCCESS Initialization successful. A device path
  76. consisting of an ACPI device path node, with
  77. UID = RootBusNumber, has been allocated and
  78. linked into RootBus.
  79. @retval EFI_OUT_OF_RESOURCES Memory allocation failed.
  80. **/
  81. EFI_STATUS
  82. InitRootBridge (
  83. IN UINT64 Supports,
  84. IN UINT64 Attributes,
  85. IN UINT64 AllocAttributes,
  86. IN UINT8 RootBusNumber,
  87. IN UINT8 MaxSubBusNumber,
  88. IN PCI_ROOT_BRIDGE_APERTURE *Io,
  89. IN PCI_ROOT_BRIDGE_APERTURE *Mem,
  90. IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
  91. IN PCI_ROOT_BRIDGE_APERTURE *PMem,
  92. IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
  93. OUT PCI_ROOT_BRIDGE *RootBus
  94. )
  95. {
  96. OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
  97. //
  98. // Be safe if other fields are added to PCI_ROOT_BRIDGE later.
  99. //
  100. ZeroMem (RootBus, sizeof *RootBus);
  101. RootBus->Segment = 0;
  102. RootBus->Supports = Supports;
  103. RootBus->Attributes = Attributes;
  104. RootBus->DmaAbove4G = FALSE;
  105. RootBus->AllocationAttributes = AllocAttributes;
  106. RootBus->Bus.Base = RootBusNumber;
  107. RootBus->Bus.Limit = MaxSubBusNumber;
  108. CopyMem (&RootBus->Io, Io, sizeof (*Io));
  109. CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
  110. CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
  111. CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
  112. CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
  113. RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdSimicsX58HostBridgePciDevId) !=
  114. INTEL_ICH10_DEVICE_ID);
  115. DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,
  116. &mRootBridgeDevicePathTemplate);
  117. if (DevicePath == NULL) {
  118. DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
  119. return EFI_OUT_OF_RESOURCES;
  120. }
  121. DevicePath->AcpiDevicePath.UID = RootBusNumber;
  122. RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
  123. DEBUG ((EFI_D_INFO,
  124. "%a: populated root bus %d, with room for %d subordinate bus(es)\n",
  125. __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
  126. return EFI_SUCCESS;
  127. }
  128. /**
  129. Uninitialize a PCI_ROOT_BRIDGE structure set up with InitRootBridge().
  130. param[in] RootBus The PCI_ROOT_BRIDGE structure, allocated by the caller and
  131. initialized with InitRootBridge(), that should be
  132. uninitialized. This function doesn't free RootBus.
  133. **/
  134. STATIC
  135. VOID
  136. UninitRootBridge (
  137. IN PCI_ROOT_BRIDGE *RootBus
  138. )
  139. {
  140. FreePool (RootBus->DevicePath);
  141. }
  142. /**
  143. Return all the root bridge instances in an array.
  144. @param Count Return the count of root bridge instances.
  145. @return All the root bridge instances in an array.
  146. The array should be passed into PciHostBridgeFreeRootBridges()
  147. when it's not used.
  148. **/
  149. PCI_ROOT_BRIDGE *
  150. EFIAPI
  151. PciHostBridgeGetRootBridges (
  152. UINTN *Count
  153. )
  154. {
  155. EFI_STATUS Status;
  156. UINT64 ExtraRootBridges;
  157. PCI_ROOT_BRIDGE *Bridges;
  158. UINTN Initialized;
  159. UINTN LastRootBridgeNumber;
  160. UINTN RootBridgeNumber;
  161. UINT64 Attributes;
  162. UINT64 AllocationAttributes;
  163. PCI_ROOT_BRIDGE_APERTURE Io;
  164. PCI_ROOT_BRIDGE_APERTURE Mem;
  165. PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
  166. ZeroMem (&Io, sizeof (Io));
  167. ZeroMem (&Mem, sizeof (Mem));
  168. ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
  169. Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
  170. EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
  171. EFI_PCI_ATTRIBUTE_ISA_IO_16 |
  172. EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
  173. EFI_PCI_ATTRIBUTE_VGA_MEMORY |
  174. EFI_PCI_ATTRIBUTE_VGA_IO_16 |
  175. EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
  176. AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
  177. if (PcdGet64 (PcdPciMmio64Size) > 0) {
  178. AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
  179. MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
  180. MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +
  181. PcdGet64 (PcdPciMmio64Size) - 1;
  182. } else {
  183. CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));
  184. }
  185. Io.Base = PcdGet64 (PcdPciIoBase);
  186. Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);
  187. Mem.Base = PcdGet64 (PcdPciMmio32Base);
  188. Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);
  189. *Count = 0;
  190. ExtraRootBridges = 0;
  191. //
  192. // Allocate the "main" root bridge, and any extra root bridges.
  193. //
  194. Bridges = AllocatePool ((1 + (UINTN)ExtraRootBridges) * sizeof *Bridges);
  195. if (Bridges == NULL) {
  196. DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
  197. return NULL;
  198. }
  199. Initialized = 0;
  200. //
  201. // The "main" root bus is always there.
  202. //
  203. LastRootBridgeNumber = 0;
  204. //
  205. // Scan all other root buses. If function 0 of any device on a bus returns a
  206. // VendorId register value different from all-bits-one, then that bus is
  207. // alive.
  208. //
  209. for (RootBridgeNumber = 1;
  210. RootBridgeNumber <= PCI_MAX_BUS && Initialized < ExtraRootBridges;
  211. ++RootBridgeNumber) {
  212. UINTN Device;
  213. for (Device = 0; Device <= PCI_MAX_DEVICE; ++Device) {
  214. if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,
  215. PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {
  216. break;
  217. }
  218. }
  219. if (Device <= PCI_MAX_DEVICE) {
  220. //
  221. // Found the next root bus. We can now install the *previous* one,
  222. // because now we know how big a bus number range *that* one has, for any
  223. // subordinate buses that might exist behind PCI bridges hanging off it.
  224. //
  225. Status = InitRootBridge (
  226. Attributes,
  227. Attributes,
  228. AllocationAttributes,
  229. (UINT8) LastRootBridgeNumber,
  230. (UINT8) (RootBridgeNumber - 1),
  231. &Io,
  232. &Mem,
  233. &MemAbove4G,
  234. &mNonExistAperture,
  235. &mNonExistAperture,
  236. &Bridges[Initialized]
  237. );
  238. if (EFI_ERROR (Status)) {
  239. goto FreeBridges;
  240. }
  241. ++Initialized;
  242. LastRootBridgeNumber = RootBridgeNumber;
  243. }
  244. }
  245. //
  246. // Install the last root bus (which might be the only, ie. main, root bus, if
  247. // we've found no extra root buses).
  248. //
  249. Status = InitRootBridge (
  250. Attributes,
  251. Attributes,
  252. AllocationAttributes,
  253. (UINT8) LastRootBridgeNumber,
  254. PCI_MAX_BUS,
  255. &Io,
  256. &Mem,
  257. &MemAbove4G,
  258. &mNonExistAperture,
  259. &mNonExistAperture,
  260. &Bridges[Initialized]
  261. );
  262. if (EFI_ERROR (Status)) {
  263. goto FreeBridges;
  264. }
  265. ++Initialized;
  266. *Count = Initialized;
  267. return Bridges;
  268. FreeBridges:
  269. while (Initialized > 0) {
  270. --Initialized;
  271. UninitRootBridge (&Bridges[Initialized]);
  272. }
  273. FreePool (Bridges);
  274. return NULL;
  275. }
  276. /**
  277. Free the root bridge instances array returned from
  278. PciHostBridgeGetRootBridges().
  279. @param The root bridge instances array.
  280. @param The count of the array.
  281. **/
  282. VOID
  283. EFIAPI
  284. PciHostBridgeFreeRootBridges (
  285. PCI_ROOT_BRIDGE *Bridges,
  286. UINTN Count
  287. )
  288. {
  289. if (Bridges == NULL && Count == 0) {
  290. return;
  291. }
  292. ASSERT (Bridges != NULL && Count > 0);
  293. do {
  294. --Count;
  295. UninitRootBridge (&Bridges[Count]);
  296. } while (Count > 0);
  297. FreePool (Bridges);
  298. }
  299. /**
  300. Inform the platform that the resource conflict happens.
  301. @param HostBridgeHandle Handle of the Host Bridge.
  302. @param Configuration Pointer to PCI I/O and PCI memory resource
  303. descriptors. The Configuration contains the resources
  304. for all the root bridges. The resource for each root
  305. bridge is terminated with END descriptor and an
  306. additional END is appended indicating the end of the
  307. entire resources. The resource descriptor field
  308. values follow the description in
  309. EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  310. .SubmitResources().
  311. **/
  312. VOID
  313. EFIAPI
  314. PciHostBridgeResourceConflict (
  315. EFI_HANDLE HostBridgeHandle,
  316. VOID *Configuration
  317. )
  318. {
  319. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
  320. UINTN RootBridgeIndex;
  321. DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
  322. RootBridgeIndex = 0;
  323. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
  324. while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
  325. DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
  326. for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
  327. ASSERT (Descriptor->ResType <
  328. (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
  329. sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
  330. )
  331. );
  332. DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
  333. mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
  334. Descriptor->AddrLen, Descriptor->AddrRangeMax
  335. ));
  336. if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
  337. DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
  338. Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
  339. ((Descriptor->SpecificFlag &
  340. EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
  341. ) != 0) ? L" (Prefetchable)" : L""
  342. ));
  343. }
  344. }
  345. //
  346. // Skip the END descriptor for root bridge
  347. //
  348. ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
  349. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
  350. (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
  351. );
  352. }
  353. }