PeiBoardPolicyUpdate.c 13 KB

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  1. /** @file
  2. This file configures Aspire VN7-572G board-specific policies.
  3. Copyright (c) 2021, Baruch Binyamin Doron
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <ConfigBlock.h>
  7. #include <Library/ConfigBlockLib.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/PcdLib.h>
  10. #include <CpuPolicyCommon.h>
  11. #include <PchPolicyCommon.h>
  12. #include <PchPreMemPolicyCommon.h>
  13. #include <SaPolicyCommon.h>
  14. /* FIXME/NB: Bring back in-line with API mode policies */
  15. #define SA_VR 0
  16. #define IA_VR 1
  17. #define GT_UNSLICED_VR 2
  18. #define GT_SLICED_VR 3
  19. /**
  20. Performs the remainder of board-specific FSP Policy initialization.
  21. @param[in] Policy Policy PPI pointer.
  22. @retval EFI_SUCCESS FSP UPD Data is updated.
  23. @retval EFI_NOT_FOUND Fail to locate required PPI.
  24. @retval Other FSP UPD Data update process fail.
  25. **/
  26. EFI_STATUS
  27. EFIAPI
  28. PeiFspBoardPolicyUpdatePreMem (
  29. IN VOID *Policy
  30. )
  31. {
  32. EFI_STATUS Status;
  33. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
  34. MEMORY_CONFIGURATION *MemConfig;
  35. PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
  36. // Retrieve the config blocks we depend on
  37. Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
  38. ASSERT_EFI_ERROR (Status);
  39. if (MiscPeiPreMemConfig == NULL) {
  40. return EFI_NOT_FOUND;
  41. }
  42. Status = GetConfigBlock (Policy, &gMemoryConfigGuid, (VOID *) &MemConfig);
  43. ASSERT_EFI_ERROR (Status);
  44. if (MemConfig == NULL) {
  45. return EFI_NOT_FOUND;
  46. }
  47. Status = GetConfigBlock (Policy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
  48. ASSERT_EFI_ERROR (Status);
  49. if (HpetPreMemConfig == NULL) {
  50. return EFI_NOT_FOUND;
  51. }
  52. /* System Agent config */
  53. MiscPeiPreMemConfig->UserBd = PcdGet8(PcdSaMiscUserBd);
  54. MemConfig->DqPinsInterleaved = (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved);
  55. MemConfig->CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig);
  56. MemConfig->SaGv = 3; // Enabled
  57. // TODO: Why should this be here?
  58. // FSP should program it's default BDF value (but where is bus 0xF0?)
  59. HpetPreMemConfig->BdfValid = 1;
  60. /* iGFX config */
  61. //FIXME FspmUpd->FspmConfig.PrimaryDisplay = 4; // Switchable Graphics
  62. return EFI_SUCCESS;
  63. }
  64. /**
  65. Performs the remainder of board-specific FSP Policy initialization.
  66. @param[in] Policy Policy PPI pointer.
  67. @retval EFI_SUCCESS FSP UPD Data is updated.
  68. @retval EFI_NOT_FOUND Fail to locate required PPI.
  69. @retval Other FSP UPD Data update process fail.
  70. **/
  71. EFI_STATUS
  72. EFIAPI
  73. PeiFspBoardPolicyUpdate (
  74. IN VOID *Policy
  75. )
  76. {
  77. EFI_STATUS Status;
  78. PCH_LOCK_DOWN_CONFIG *LockDownConfig;
  79. PCH_GENERAL_CONFIG *PchGeneralConfig;
  80. CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
  81. CPU_POWER_MGMT_VR_CONFIG *CpuPowerMgmtVrConfig;
  82. PCH_USB_CONFIG *UsbConfig;
  83. PCH_SATA_CONFIG *SataConfig;
  84. PCH_PCIE_CONFIG *PchPcieConfig;
  85. PCH_PM_CONFIG *PmConfig;
  86. PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
  87. PCH_HDAUDIO_CONFIG *HdAudioConfig;
  88. PCH_IOAPIC_CONFIG *IoApicConfig;
  89. INTN Index;
  90. // Retrieve the config blocks we depend on (all are expected to be installed)
  91. Status = GetConfigBlock (Policy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
  92. ASSERT_EFI_ERROR (Status);
  93. if (LockDownConfig == NULL) {
  94. return EFI_NOT_FOUND;
  95. }
  96. Status = GetConfigBlock (Policy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
  97. ASSERT_EFI_ERROR (Status);
  98. if (PchGeneralConfig == NULL) {
  99. return EFI_NOT_FOUND;
  100. }
  101. Status = GetConfigBlock (Policy, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
  102. ASSERT_EFI_ERROR (Status);
  103. if (CpuPowerMgmtBasicConfig == NULL) {
  104. return EFI_NOT_FOUND;
  105. }
  106. Status = GetConfigBlock (Policy, &gCpuPowerMgmtVrConfigGuid, (VOID *) &CpuPowerMgmtVrConfig);
  107. ASSERT_EFI_ERROR (Status);
  108. if (CpuPowerMgmtVrConfig == NULL) {
  109. return EFI_NOT_FOUND;
  110. }
  111. Status = GetConfigBlock (Policy, &gUsbConfigGuid, (VOID *) &UsbConfig);
  112. ASSERT_EFI_ERROR (Status);
  113. if (UsbConfig == NULL) {
  114. return EFI_NOT_FOUND;
  115. }
  116. Status = GetConfigBlock (Policy, &gSataConfigGuid, (VOID *) &SataConfig);
  117. ASSERT_EFI_ERROR (Status);
  118. if (SataConfig == NULL) {
  119. return EFI_NOT_FOUND;
  120. }
  121. Status = GetConfigBlock (Policy, &gPcieRpConfigGuid, (VOID *) &PchPcieConfig);
  122. ASSERT_EFI_ERROR (Status);
  123. if (PchPcieConfig == NULL) {
  124. return EFI_NOT_FOUND;
  125. }
  126. Status = GetConfigBlock (Policy, &gPmConfigGuid, (VOID *) &PmConfig);
  127. ASSERT_EFI_ERROR (Status);
  128. if (PmConfig == NULL) {
  129. return EFI_NOT_FOUND;
  130. }
  131. Status = GetConfigBlock (Policy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
  132. ASSERT_EFI_ERROR (Status);
  133. if (SerialIrqConfig == NULL) {
  134. return EFI_NOT_FOUND;
  135. }
  136. Status = GetConfigBlock (Policy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
  137. ASSERT_EFI_ERROR (Status);
  138. if (HdAudioConfig == NULL) {
  139. return EFI_NOT_FOUND;
  140. }
  141. Status = GetConfigBlock (Policy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
  142. ASSERT_EFI_ERROR (Status);
  143. if (IoApicConfig == NULL) {
  144. return EFI_NOT_FOUND;
  145. }
  146. // FIXME/NB: This is insecure and not production-ready!
  147. // TODO: Configure SPI lockdown by variable on FrontPage?
  148. LockDownConfig->BiosLock = 0;
  149. LockDownConfig->SpiEiss = 0;
  150. // TODO: Why should this be here?
  151. // FSP should program it's default BDF value (but where is bus 0xF0?)
  152. IoApicConfig->BdfValid = 1;
  153. // Note: SerialIoDevMode default is satisfactory, but not entirely accurate.
  154. // Board has no GPIO expander on I2C4 (despite SetupUtility claim
  155. // that it does - this appears to be static text?) and is UART0 merely supporting
  156. // the UART2 devfn?
  157. // Acer IDs (TODO: "Newgate" IDs)
  158. //FIXME FspsUpd->FspsConfig.DefaultSvid = 0x1025;
  159. //FIXME FspsUpd->FspsConfig.DefaultSid = 0x1037;
  160. PchGeneralConfig->SubSystemVendorId = 0x1025;
  161. PchGeneralConfig->SubSystemId = 0x1037;
  162. /* System Agent config */
  163. // Set the Thermal Control Circuit (TCC) activation value to 97C
  164. // even though FSP integration guide says to set it to 100C for SKL-U
  165. // (offset at 0), because when the TCC activates at 100C, the CPU
  166. // will have already shut itself down from overheating protection.
  167. CpuPowerMgmtBasicConfig->TccActivationOffset = 3;
  168. // VR Slew rate setting for improving audible noise
  169. CpuPowerMgmtVrConfig->AcousticNoiseMitigation = 1;
  170. CpuPowerMgmtVrConfig->SlowSlewRateForIa = 3; // Fast/16
  171. CpuPowerMgmtVrConfig->SlowSlewRateForGt = 3; // Fast/16
  172. CpuPowerMgmtVrConfig->SlowSlewRateForSa = 0; // Fast/2
  173. CpuPowerMgmtVrConfig->FastPkgCRampDisableIa = 0;
  174. CpuPowerMgmtVrConfig->FastPkgCRampDisableGt = 0;
  175. CpuPowerMgmtVrConfig->FastPkgCRampDisableSa = 0;
  176. // VR domain configuration (copied from board port, before VR config moved
  177. // to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1
  178. CpuPowerMgmtVrConfig->AcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
  179. CpuPowerMgmtVrConfig->DcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
  180. CpuPowerMgmtVrConfig->Psi1Threshold[SA_VR] = 80; // 20A (in 1/4 increments)
  181. CpuPowerMgmtVrConfig->Psi2Threshold[SA_VR] = 16; // 4A (in 1/4 increments)
  182. CpuPowerMgmtVrConfig->Psi3Threshold[SA_VR] = 4; // 1A (in 1/4 increments)
  183. CpuPowerMgmtVrConfig->IccMax[SA_VR] = 18; // 4.5A (in 1/4 increments)
  184. CpuPowerMgmtVrConfig->VrVoltageLimit[SA_VR] = 1520; // 1520mV
  185. CpuPowerMgmtVrConfig->AcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
  186. CpuPowerMgmtVrConfig->DcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
  187. CpuPowerMgmtVrConfig->Psi1Threshold[IA_VR] = 80; // 20A (in 1/4 increments)
  188. CpuPowerMgmtVrConfig->Psi2Threshold[IA_VR] = 20; // 5A (in 1/4 increments)
  189. CpuPowerMgmtVrConfig->Psi3Threshold[IA_VR] = 4; // 1A (in 1/4 increments)
  190. CpuPowerMgmtVrConfig->IccMax[IA_VR] = 116; // 29A (in 1/4 increments)
  191. CpuPowerMgmtVrConfig->VrVoltageLimit[IA_VR] = 1520; // 1520mV
  192. CpuPowerMgmtVrConfig->AcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
  193. CpuPowerMgmtVrConfig->DcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
  194. CpuPowerMgmtVrConfig->Psi1Threshold[GT_UNSLICED_VR] = 80; // 20A (in 1/4 increments)
  195. CpuPowerMgmtVrConfig->Psi2Threshold[GT_UNSLICED_VR] = 20; // 5A (in 1/4 increments)
  196. CpuPowerMgmtVrConfig->Psi3Threshold[GT_UNSLICED_VR] = 4; // 1A (in 1/4 increments)
  197. CpuPowerMgmtVrConfig->IccMax[GT_UNSLICED_VR] = 124; // 31A (in 1/4 increments)
  198. CpuPowerMgmtVrConfig->VrVoltageLimit[GT_UNSLICED_VR] = 1520; // 1520mV
  199. CpuPowerMgmtVrConfig->AcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
  200. CpuPowerMgmtVrConfig->DcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
  201. CpuPowerMgmtVrConfig->Psi1Threshold[GT_SLICED_VR] = 80; // 20A (in 1/4 increments)
  202. CpuPowerMgmtVrConfig->Psi2Threshold[GT_SLICED_VR] = 20; // 5A (in 1/4 increments)
  203. CpuPowerMgmtVrConfig->Psi3Threshold[GT_SLICED_VR] = 4; // 1A (in 1/4 increments)
  204. CpuPowerMgmtVrConfig->IccMax[GT_SLICED_VR] = 124; // 31A (in 1/4 increments)
  205. CpuPowerMgmtVrConfig->VrVoltageLimit[GT_SLICED_VR] = 1520; // 1520mV
  206. // PL1, PL2 override 35W, PL4 override 43W (in 125 mW increments)
  207. CpuPowerMgmtBasicConfig->PowerLimit1 = 280;
  208. CpuPowerMgmtBasicConfig->PowerLimit2Power = 280;
  209. CpuPowerMgmtBasicConfig->PowerLimit4 = 344;
  210. // ISL95857 VR
  211. // Send VR specific command for PS4 exit issue
  212. CpuPowerMgmtVrConfig->SendVrMbxCmd1 = 2;
  213. // Send VR mailbox command for IA/GT/SA rails
  214. //FIXME FspsUpd->FspsConfig.IslVrCmd = 2;
  215. /* Skycam config */
  216. // FspsUpd->FspsConfig.SaImguEnable = 0;
  217. // FspsUpd->FspsConfig.PchCio2Enable = 0;
  218. /* Sensor hub config */
  219. // FspsUpd->FspsConfig.PchIshEnable = 0;
  220. /* xHCI config */
  221. // FspsUpd->FspsConfig.SsicPortEnable = 0;
  222. // Configure USB2 ports in two blocks
  223. for (Index = 0; Index < 3; Index++) {
  224. UsbConfig->PortUsb20[Index].Afe.Txiset = 0x2; // 16.9mV
  225. UsbConfig->PortUsb20[Index].Afe.Predeemp = 1; // De-emphasis on
  226. UsbConfig->PortUsb20[Index].Afe.Petxiset = 0x3;// 28.15mV
  227. UsbConfig->PortUsb20[Index].Afe.Pehalfbit = 1; // Half-bit
  228. }
  229. for (Index = 3; Index < 9; Index++) {
  230. UsbConfig->PortUsb20[Index].Afe.Txiset = 0; // 0mV
  231. UsbConfig->PortUsb20[Index].Afe.Predeemp = 0x2;// Pre-emphasis and de-emphasis on
  232. UsbConfig->PortUsb20[Index].Afe.Petxiset = 0x7;// 56.3mV
  233. UsbConfig->PortUsb20[Index].Afe.Pehalfbit = 1; // Half-bit
  234. }
  235. // Configure all USB3 ports
  236. for (Index = 0; Index < 4; Index++) {
  237. UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable = 1;
  238. UsbConfig->PortUsb30[Index].HsioTxDeEmph = 0x29; // Default (approximately -3.5dB de-emphasis)
  239. }
  240. // Disable all OC pins
  241. for (Index = 0; Index < 9; Index++) {
  242. UsbConfig->PortUsb20[Index].OverCurrentPin = PchUsbOverCurrentPinSkip;
  243. }
  244. for (Index = 0; Index < 4; Index++) {
  245. UsbConfig->PortUsb30[Index].OverCurrentPin = PchUsbOverCurrentPinSkip;
  246. }
  247. /* xDCI config */
  248. // FspsUpd->FspsConfig.XdciEnable = 0;
  249. /* SATA config */
  250. // This is a hard silicon requirement, discovered several times by coreboot boards
  251. SataConfig->PwrOptEnable = 1;
  252. /* PCIe config */
  253. // Port 1 (dGPU; x4)
  254. PchPcieConfig->RootPort[0].AdvancedErrorReporting = 1;
  255. PchPcieConfig->RootPort[0].LtrEnable = 1;
  256. PchPcieConfig->RootPort[0].ClkReqSupported = 1;
  257. PchPcieConfig->RootPort[0].ClkReqNumber = 0x0;
  258. PchPcieConfig->RootPort[0].MaxPayload = PchPcieMaxPayload256;
  259. // Port 7 (NGFF; x2)
  260. PchPcieConfig->RootPort[6].AdvancedErrorReporting = 1;
  261. PchPcieConfig->RootPort[6].LtrEnable = 1;
  262. PchPcieConfig->RootPort[6].ClkReqSupported = 1;
  263. PchPcieConfig->RootPort[6].ClkReqNumber = 0x3;
  264. PchPcieConfig->RootPort[6].MaxPayload = PchPcieMaxPayload256;
  265. // Port 9 (LAN)
  266. PchPcieConfig->RootPort[8].AdvancedErrorReporting = 1;
  267. PchPcieConfig->RootPort[8].LtrEnable = 1;
  268. PchPcieConfig->RootPort[8].ClkReqSupported = 1;
  269. PchPcieConfig->RootPort[8].ClkReqNumber = 0x1;
  270. PchPcieConfig->RootPort[8].MaxPayload = PchPcieMaxPayload256;
  271. // Port 10 (WLAN)
  272. PchPcieConfig->RootPort[9].AdvancedErrorReporting = 1;
  273. PchPcieConfig->RootPort[9].LtrEnable = 1;
  274. PchPcieConfig->RootPort[9].ClkReqSupported = 1;
  275. PchPcieConfig->RootPort[9].ClkReqNumber = 0x2;
  276. PchPcieConfig->RootPort[9].MaxPayload = PchPcieMaxPayload256;
  277. // ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
  278. PchPcieConfig->RootPort[9].Aspm = PchPcieAspmL1;
  279. /* LPC config */
  280. // EC/KBC requires continuous mode
  281. PmConfig->LpcClockRun = 1;
  282. SerialIrqConfig->SirqMode = PchContinuousMode;
  283. /* HDA config */
  284. HdAudioConfig->DspEndpointDmic = PchHdaDmic1chArray;
  285. /* SCS config */
  286. // Although platform NVS area shows this enabled, the SD card reader is connected over USB, not SCS
  287. // FspsUpd->FspsConfig.ScsEmmcEnabled = 0;
  288. // FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
  289. return EFI_SUCCESS;
  290. }