Armada7k8kLibMem.c 6.1 KB

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  1. /*******************************************************************************
  2. Copyright (C) 2016 Marvell International Ltd.
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. *******************************************************************************/
  5. #include <Uefi.h>
  6. #include <IndustryStandard/ArmStdSmc.h>
  7. #include <IndustryStandard/MvSmc.h>
  8. #include <Library/ArmadaBoardDescLib.h>
  9. #include <Library/ArmadaSoCDescLib.h>
  10. #include <Library/ArmPlatformLib.h>
  11. #include <Library/ArmSmcLib.h>
  12. #include <Library/DebugLib.h>
  13. #include <Library/HobLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/MemoryAllocationLib.h>
  16. #include "Armada7k8kLibMem.h"
  17. // The total number of descriptors, including the final "end-of-table" descriptor.
  18. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
  19. // DDR attributes
  20. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  21. #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  22. STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
  23. // Obtain DRAM size basing on register values filled by early firmware.
  24. STATIC
  25. UINT64
  26. GetDramSize (
  27. IN OUT UINT64 *MemSize
  28. )
  29. {
  30. #if defined(MDE_CPU_AARCH64)
  31. ARM_SMC_ARGS SmcRegs = {0};
  32. EFI_STATUS Status;
  33. SmcRegs.Arg0 = MV_SMC_ID_DRAM_SIZE;
  34. Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, 0);
  35. if (EFI_ERROR (Status)) {
  36. return Status;
  37. }
  38. ArmCallSmc (&SmcRegs);
  39. *MemSize = SmcRegs.Arg0;
  40. #else
  41. //
  42. // Use fixed value, as currently there is no support
  43. // in Armada early firmware for 32-bit SMC
  44. //
  45. *MemSize = FixedPcdGet64 (PcdSystemMemorySize);
  46. #endif
  47. return EFI_SUCCESS;
  48. }
  49. /**
  50. Return the Virtual Memory Map of your platform
  51. This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
  52. @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
  53. Virtual Memory mapping. This array must be ended by a zero-filled
  54. entry
  55. **/
  56. VOID
  57. ArmPlatformGetVirtualMemoryMap (
  58. IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
  59. )
  60. {
  61. UINTN Index = 0;
  62. UINT64 MemSize;
  63. UINT64 MemLowSize;
  64. UINT64 MemHighStart;
  65. UINT64 MemHighSize;
  66. UINT64 ConfigSpaceBaseAddr;
  67. UINTN PcieControllerCount;
  68. UINTN PcieIndex;
  69. MV_PCIE_CONTROLLER CONST *PcieControllers;
  70. EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
  71. EFI_STATUS Status;
  72. ASSERT (VirtualMemoryMap != NULL);
  73. ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
  74. // Obtain total memory size from the hardware.
  75. Status = GetDramSize (&MemSize);
  76. if (EFI_ERROR (Status)) {
  77. MemSize = FixedPcdGet64 (PcdSystemMemorySize);
  78. DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1024 / 1024));
  79. }
  80. if (DRAM_REMAP_ENABLED) {
  81. MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
  82. MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE;
  83. MemHighSize = MemSize - MemLowSize;
  84. } else {
  85. MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize);
  86. }
  87. ResourceAttributes = (
  88. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  89. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  90. EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  91. EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  92. EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  93. EFI_RESOURCE_ATTRIBUTE_TESTED
  94. );
  95. BuildResourceDescriptorHob (
  96. EFI_RESOURCE_SYSTEM_MEMORY,
  97. ResourceAttributes,
  98. FixedPcdGet64 (PcdSystemMemoryBase),
  99. MemLowSize
  100. );
  101. // DDR
  102. mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase);
  103. mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase);
  104. mVirtualMemoryTable[Index].Length = MemLowSize;
  105. mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
  106. // SoC MMIO configuration space
  107. mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr;
  108. mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr;
  109. mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr;
  110. mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  111. // PCIE ECAM
  112. Status = ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControllerCount);
  113. ASSERT_EFI_ERROR (Status);
  114. for (PcieIndex = 0; PcieIndex < PcieControllerCount; PcieIndex++) {
  115. mVirtualMemoryTable[++Index].PhysicalBase = PcieControllers[PcieIndex].ConfigSpaceAddress;
  116. mVirtualMemoryTable[Index].VirtualBase = PcieControllers[PcieIndex].ConfigSpaceAddress;
  117. mVirtualMemoryTable[Index].Length = (PcieControllers[PcieIndex].ConfigSpaceSize == 0) ?
  118. SIZE_256MB :
  119. PcieControllers[PcieIndex].ConfigSpaceSize;
  120. mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  121. }
  122. if (MemSize > MemLowSize) {
  123. //
  124. // If we have more than MemLowSize worth of DRAM, the remainder will be
  125. // mapped at the top of the remapped window.
  126. //
  127. mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart;
  128. mVirtualMemoryTable[Index].VirtualBase = MemHighStart;
  129. mVirtualMemoryTable[Index].Length = MemHighSize;
  130. mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
  131. BuildResourceDescriptorHob (
  132. EFI_RESOURCE_SYSTEM_MEMORY,
  133. ResourceAttributes,
  134. MemHighStart,
  135. MemHighSize
  136. );
  137. }
  138. // End of Table
  139. mVirtualMemoryTable[++Index].PhysicalBase = 0;
  140. mVirtualMemoryTable[Index].VirtualBase = 0;
  141. mVirtualMemoryTable[Index].Length = 0;
  142. mVirtualMemoryTable[Index].Attributes = 0;
  143. ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
  144. *VirtualMemoryMap = mVirtualMemoryTable;
  145. }