BoardClkGens.h 10.0 KB

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  1. /**@file
  2. Clock generator setting for multiplatform.
  3. This file includes package header files, library classes.
  4. Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _BOARD_CLK_GEN_H_
  8. #define _BOARD_CLK_GEN_H_
  9. #include <PiPei.h>
  10. #include <Library/HobLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Library/DebugLib.h>
  13. #include <Ppi/Smbus2.h>
  14. #include <IndustryStandard/SmBus.h>
  15. #include <Guid/PlatformInfo.h>
  16. #define CLOCK_GENERATOR_ADDRESS 0xd2
  17. #define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  18. #define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  19. #define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  20. typedef enum {
  21. ClockGeneratorCk410,
  22. ClockGeneratorCk505,
  23. ClockGeneratorMax
  24. } CLOCK_GENERATOR_TYPE;
  25. typedef struct {
  26. CLOCK_GENERATOR_TYPE ClockType;
  27. UINT8 ClockId;
  28. UINT8 SpreadSpectrumByteOffset;
  29. UINT8 SpreadSpectrumBitOffset;
  30. } CLOCK_GENERATOR_DETAILS;
  31. #define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
  32. //
  33. // CK410 Definitions
  34. //
  35. #define CK410_GENERATOR_ID 0x65
  36. #define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1
  37. #define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
  38. #define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4
  39. #define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)
  40. //
  41. // CK505 Definitions
  42. //
  43. #define VF_CK505_GENERATOR_ID 0x5
  44. #define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5
  45. #define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4
  46. #define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)
  47. #define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1
  48. #define CK505_GENERATOR_PERCENT_MASK ~(0xE)
  49. #define CK505_GENERATOR_PERCENT_250_VALUE 0xC
  50. #define CK505_GENERATOR_PERCENT_050_VALUE 0x4
  51. #define CK505_GENERATOR_PERCENT_000_VALUE 0x2
  52. //
  53. // IDT Definitions
  54. //
  55. #define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A
  56. #define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0
  57. #define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
  58. #define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5
  59. #define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF
  60. #define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3
  61. #define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE
  62. #define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF)
  63. #define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB
  64. #define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD
  65. //
  66. // CLOCK CONTROLLER
  67. // SmBus address to read DIMM SPD
  68. //
  69. #define SMBUS_BASE_ADDRESS 0xEFA0
  70. #define SMBUS_BUS_DEV_FUNC 0x1F0300
  71. #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4
  72. #define SMBUS_ADDR_CH_A_1 0xA0
  73. #define SMBUS_ADDR_CH_A_2 0xA2
  74. #define SMBUS_ADDR_CH_B_1 0xA4
  75. #define SMBUS_ADDR_CH_B_2 0xA6
  76. //
  77. // Bits for FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0)
  78. //
  79. #define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000
  80. #define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000
  81. #define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000
  82. #define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080
  83. #define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040
  84. //
  85. // An arbitrary maximum length for clock generator buffers
  86. //
  87. #define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
  88. //
  89. // SmBus Bus Device Function and Register Definitions
  90. //
  91. #define SMBUS_BUS_NUM 0
  92. #define SMBUS_DEV_NUM 31
  93. #define SMBUS_FUNC_NUM 3
  94. #define SMBUS_BUS_DEV_FUNC_NUM \
  95. SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)
  96. //
  97. //ICH7: SMBus I/O Space Equates;
  98. //
  99. #define BIT_SLAVE_ADDR BIT00
  100. #define BIT_COMMAND BIT01
  101. #define BIT_DATA BIT02
  102. #define BIT_COUNT BIT03
  103. #define BIT_WORD BIT04
  104. #define BIT_CONTROL BIT05
  105. #define BIT_PEC BIT06
  106. #define BIT_READ BIT07
  107. #define SMBUS_IO_READ_BIT BIT00
  108. #define SMB_CMD_QUICK 0x00
  109. #define SMB_CMD_BYTE 0x04
  110. #define SMB_CMD_BYTE_DATA 0x08
  111. #define SMB_CMD_WORD_DATA 0x0C
  112. #define SMB_CMD_PROCESS_CALL 0x10
  113. #define SMB_CMD_BLOCK 0x14
  114. #define SMB_CMD_I2C_READ 0x18
  115. #define SMB_CMD_RESERVED 0x1c
  116. #define HST_STS_BYTE_DONE 0x80
  117. #define SMB_HST_STS 0x000
  118. #define SMB_HST_CNT 0x002
  119. #define SMB_HST_CMD 0x003
  120. #define SMB_HST_ADD 0x004
  121. #define SMB_HST_DAT_0 0x005
  122. #define SMB_HST_DAT_1 0x006
  123. #define SMB_HST_BLK_DAT 0x007
  124. #define SMB_PEC 0x008
  125. #define SMB_RCV_SLVA 0x009
  126. #define SMB_SLV_DAT 0x00A
  127. #define SMB_AUX_STS 0x00C
  128. #define SMB_AUX_CTL 0x00D
  129. #define SMB_SMLINK_PIN_CTL 0x00E
  130. #define SMB_SMBUS_PIN_CTL 0x00F
  131. #define SMB_SLV_STS 0x010
  132. #define SMB_SLV_CMD 0x011
  133. #define SMB_NTFY_DADDR 0x014
  134. #define SMB_NTFY_DLOW 0x016
  135. #define SMB_NTFY_DHIGH 0x017
  136. //
  137. // PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below
  138. //
  139. #define R_COMMAND 0x04 // PCI Command Register, 16bit
  140. #define B_IOSE 0x01 // RW
  141. #define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O
  142. #define B_BASE_ADDRESS 0xFFE0 // RW
  143. #define R_HOST_CONFIGURATION 0x40 // SMBus Host Configuration Register
  144. #define B_HST_EN 0x01 // RW
  145. #define B_SMB_SMI_EN 0x02 // RW
  146. #define B_I2C_EN 0x04 // RW
  147. //
  148. // I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below
  149. //
  150. #define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W
  151. #define HST_STS_HOST_BUSY 0x01 // RO
  152. #define HST_STS_INTR 0x02 // R/WC
  153. #define HST_STS_DEV_ERR 0x04 // R/WC
  154. #define HST_STS_BUS_ERR 0x08 // R/WC
  155. #define HST_STS_FAILED 0x10 // R/WC
  156. #define SMBUS_B_SMBALERT_STS 0x20 // R/WC
  157. #define HST_STS_INUSE 0x40 // R/WC
  158. #define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC
  159. #define SMBUS_B_HSTS_ALL 0xFF // R/WC
  160. #define HOST_CONTROL_REGISTER 0x02 // Host Control Register R/W
  161. #define HST_CNT_INTREN 0x01 // RW
  162. #define HST_CNT_KILL 0x02 // RW
  163. #define SMBUS_B_SMB_CMD 0x1C // RW
  164. #define SMBUS_V_SMB_CMD_QUICK 0x00
  165. #define SMBUS_V_SMB_CMD_BYTE 0x04
  166. #define SMBUS_V_SMB_CMD_BYTE_DATA 0x08
  167. #define SMBUS_V_SMB_CMD_WORD_DATA 0x0C
  168. #define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10
  169. #define SMBUS_V_SMB_CMD_BLOCK 0x14
  170. #define SMBUS_V_SMB_CMD_IIC_READ 0x18
  171. #define SMBUS_B_LAST_BYTE 0x20 // WO
  172. #define HST_CNT_START 0x40 // WO
  173. #define HST_CNT_PEC_EN 0x80 // RW
  174. #define HOST_COMMAND_REGISTER 0x03 // Host Command Register R/W
  175. #define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave Address Register R/W
  176. #define SMBUS_B_RW_SEL 0x01 // RW
  177. #define SMBUS_B_ADDRESS 0xFE // RW
  178. #define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W
  179. #define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W
  180. #define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data Register R/W
  181. #define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W
  182. #define SMBUS_R_RSA 0x09 // Receive Slave Address Register R/W
  183. #define SMBUS_B_SLAVE_ADDR 0x7F // RW
  184. #define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W
  185. #define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC
  186. #define SMBUS_B_CRCE 0x01 //R/WC
  187. #define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control Register R/W
  188. #define SMBUS_B_AAC 0x01 //R/W
  189. #define SMBUS_B_E32B 0x02 //R/W
  190. #define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W
  191. #define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO
  192. #define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO
  193. #define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW
  194. #define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W
  195. #define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO
  196. #define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO
  197. #define SMBUS_B_SMBCLK_CTL 0x04 // RW
  198. #define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC
  199. #define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC
  200. #define SMBUS_R_SCMD 0x11 // Slave Command Register R/W
  201. #define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W
  202. #define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W
  203. #define SMBUS_B_SMBALERT_DIS 0x04 // R/W
  204. #define SMBUS_R_NDA 0x14 // Notify Device Address Register RO
  205. #define SMBUS_B_DEVICE_ADDRESS 0xFE // RO
  206. #define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO
  207. #define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register RO
  208. #define BUS_TRIES 3 // How many times to retry on Bus Errors
  209. #define SMBUS_NUM_RESERVED 21 // Number of device addresses that are
  210. // reserved by the SMBus spec.
  211. #define SMBUS_ADDRESS_ARP 0xC2 >> 1
  212. #define SMBUS_DATA_PREPARE_TO_ARP 0x01
  213. #define SMBUS_DATA_RESET_DEVICE 0x02
  214. #define SMBUS_DATA_GET_UDID_GENERAL 0x03
  215. #define SMBUS_DATA_ASSIGN_ADDRESS 0x04
  216. #define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address
  217. EFI_STATUS
  218. ConfigurePlatformClocks (
  219. IN EFI_PEI_SERVICES **PeiServices,
  220. IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
  221. IN VOID *SmbusPpi
  222. );
  223. #endif