PlatformInfo.h 12 KB

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  1. /*++
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformInfo.h
  6. Abstract:
  7. GUID used for Platform Info Data entries in the HOB list.
  8. --*/
  9. #ifndef _PLATFORM_INFO_GUID_H_
  10. #define _PLATFORM_INFO_GUID_H_
  11. #ifndef ECP_FLAG
  12. #include <PiPei.h>
  13. #include <Library/HobLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/DebugLib.h>
  16. #include <IndustryStandard/SmBus.h>
  17. #endif
  18. #define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.
  19. //
  20. // Start::BayLake Board Defines
  21. //
  22. #define BOARD_REVISION_DEFAULT = 0xff
  23. #define UNKNOWN_FABID 0x0F
  24. #define FAB_ID_MASK 0x0F
  25. #define BOARD_ID_2 0x01
  26. #define BOARD_ID_1 0x40
  27. #define BOARD_ID_0 0x04
  28. #define BOARD_ID_DT_CRB 0x0
  29. #define BOARD_ID_DT_VLVR 0x1
  30. #define BOARD_ID_SVP_VLV 0xC
  31. #define BOARD_ID_SVP_EV_VLV 0xD
  32. //
  33. // End::BayLake Board Defines
  34. //
  35. //
  36. // Start::Alpine Valley Board Defines
  37. //
  38. #define DC_ID_DDR3L 0x00
  39. #define DC_ID_DDR3 0x04
  40. #define DC_ID_LPDDR3 0x02
  41. #define DC_ID_LPDDR2 0x06
  42. #define DC_ID_DDR4 0x01
  43. #define DC_ID_DDR3L_ECC 0x05
  44. #define DC_ID_NO_MEM 0x07
  45. //
  46. // End::Alpine Valley Board Defines
  47. //
  48. #define MAX_FAB_ID_RETRY_COUNT 100
  49. #define MAX_FAB_ID_CHECK_COUNT 3
  50. #define PLATFORM_INFO_HOB_REVISION 0x1
  51. #define EFI_PLATFORM_INFO_GUID \
  52. { \
  53. 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
  54. }
  55. extern EFI_GUID gEfiPlatformInfoGuid;
  56. typedef enum {
  57. FlavorUnknown = 0,
  58. //
  59. // Mobile
  60. //
  61. FlavorMobile = 1,
  62. //
  63. // Desktop
  64. //
  65. FlavorDesktop = 2,
  66. //
  67. // Tablet
  68. //
  69. FlavorTablet = 3
  70. } PLATFORM_FLAVOR;
  71. #pragma pack(1)
  72. typedef struct {
  73. UINT16 PciResourceIoBase;
  74. UINT16 PciResourceIoLimit;
  75. UINT32 PciResourceMem32Base;
  76. UINT32 PciResourceMem32Limit;
  77. UINT64 PciResourceMem64Base;
  78. UINT64 PciResourceMem64Limit;
  79. UINT64 PciExpressBase;
  80. UINT32 PciExpressSize;
  81. UINT8 PciHostAddressWidth;
  82. UINT8 PciResourceMinSecBus;
  83. } EFI_PLATFORM_PCI_DATA;
  84. typedef struct {
  85. UINT8 CpuAddressWidth;
  86. UINT32 CpuFamilyStepping;
  87. } EFI_PLATFORM_CPU_DATA;
  88. typedef struct {
  89. UINT8 SysIoApicEnable;
  90. UINT8 SysSioExist;
  91. } EFI_PLATFORM_SYS_DATA;
  92. typedef struct {
  93. UINT32 MemTolm;
  94. UINT32 MemMaxTolm;
  95. UINT32 MemTsegSize;
  96. UINT32 MemTsegBase;
  97. UINT32 MemIedSize;
  98. UINT32 MemIgdSize;
  99. UINT32 MemIgdBase;
  100. UINT32 MemIgdGttSize;
  101. UINT32 MemIgdGttBase;
  102. UINT64 MemMir0;
  103. UINT64 MemMir1;
  104. UINT32 MemConfigSize;
  105. UINT16 MmioSize;
  106. UINT8 DdrFreq;
  107. UINT8 DdrType;
  108. UINT32 MemSize;
  109. BOOLEAN EccSupport;
  110. UINT8 Reserved[3];
  111. UINT16 DimmSize[2];
  112. } EFI_PLATFORM_MEM_DATA;
  113. typedef struct {
  114. UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
  115. UINT8 IgdBootType; // IGD Boot Display Device
  116. UINT8 IgdPanelType; // IGD Panel Type CMOs option
  117. UINT8 IgdTvFormat; // IGD TV Format CMOS option
  118. UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
  119. UINT8 IgdPanelScaling; // IGD Panel Scaling
  120. UINT8 IgdBlcConfig; // IGD BLC Configuration
  121. UINT8 IgdBiaConfig; // IGD BIA Configuration
  122. UINT8 IgdSscConfig; // IGD SSC Configuration
  123. UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
  124. UINT8 IgdFunc1Enable; // IGD Function 1 Enable
  125. UINT8 IgdHpllVco; // HPLL VCO
  126. UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
  127. UINT8 IgdPAVP; // IGD PAVP data
  128. } EFI_PLATFORM_IGD_DATA;
  129. typedef enum {
  130. BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board
  131. BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)
  132. BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011
  133. BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)
  134. BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)
  135. BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board
  136. BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board
  137. BOARD_ID_BS_RVP = 0x30, // Bakersport Board
  138. BOARD_ID_CVH = 0x90, // Crestview Hills
  139. BOARD_ID_MINNOW2 = 0xA0, // MinnowBorad Max
  140. BOARD_ID_MINNOW2_TURBOT = 0xB0 // MinnowBoard Turbot
  141. } BOARD_ID_LIST;
  142. typedef enum {
  143. FAB1 = 0,
  144. FAB2 = 1,
  145. FAB3 = 2
  146. } FAB_ID_LIST;
  147. typedef enum {
  148. PR0 = 0, // FFRD PR0
  149. PR05 = 1, // FFRD PR0.3 and PR 0.5
  150. PR1 = 2, // FFRD PR1
  151. PR11 = 3 // FFRD PR1.1
  152. } FFRD_ID_LIST;
  153. //
  154. // VLV2 GPIO GROUP OFFSET
  155. //
  156. #define GPIO_SCORE_OFFSET 0x0000
  157. #define GPIO_NCORE_OFFSET 0x1000
  158. #define GPIO_SSUS_OFFSET 0x2000
  159. //
  160. // GPIO Initialization Data Structure for BayLake.
  161. // SC = SCORE, SS= SSUS
  162. // Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
  163. //
  164. //
  165. // IO space
  166. //
  167. typedef struct{
  168. UINT32 Use_Sel_SC0;
  169. UINT32 Use_Sel_SC1;
  170. UINT32 Use_Sel_SC2;
  171. UINT32 Use_Sel_SS;
  172. UINT32 Io_Sel_SC0;
  173. UINT32 Io_Sel_SC1;
  174. UINT32 Io_Sel_SC2;
  175. UINT32 Io_Sel_SS;
  176. UINT32 GP_Lvl_SC0;
  177. UINT32 GP_Lvl_SC1;
  178. UINT32 GP_Lvl_SC2;
  179. UINT32 GP_Lvl_SS;
  180. UINT32 TPE_SC0;
  181. UINT32 TPE_SS;
  182. UINT32 TNE_SC0;
  183. UINT32 TNE_SS;
  184. UINT32 TS_SC0;
  185. UINT32 TS_SS;
  186. UINT32 WE_SS;
  187. } CFIO_INIT_STRUCT;
  188. //
  189. // CFIO PAD configuration Registers
  190. //
  191. //
  192. // Memory space
  193. //
  194. typedef union {
  195. UINT32 dw;
  196. struct {
  197. UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection
  198. UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
  199. UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
  200. UINT32 Pull_assign:2; // 7:8 Pull assignment
  201. UINT32 Pull_strength:2; // 9:10 Pull strength
  202. UINT32 Bypass_flop:1; // 11 Bypass flop
  203. UINT32 Filter_en:1; // 12 Filter Enable
  204. UINT32 Hist_ctrl:2; // 13:14 hysteresis control
  205. UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
  206. UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
  207. UINT32 Reserved:3; // 22:24 Reserved
  208. UINT32 TPE:1; // 25 Trigger Positive Edge Enable
  209. UINT32 TNE:1; // 26 Trigger Negative Edge Enable
  210. UINT32 Reserved2:3; // 27:29 Reserved
  211. UINT32 i1p5sel:1; // 30
  212. UINT32 IODEN:1; // 31 : Open Drain enable. Active high
  213. } r;
  214. } PAD_CONF0;
  215. typedef union{
  216. UINT32 dw;
  217. struct {
  218. UINT32 instr:16; // 0:15 Pad (N) strength.
  219. UINT32 ipstr:16; // 16:31 Pad (P) strength.
  220. }r;
  221. } PAD_CONF1;
  222. typedef union{
  223. UINT32 dw;
  224. struct {
  225. UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
  226. UINT32 ioutenb:1; // 1 output enable
  227. UINT32 iinenb:1; // 2 input enable
  228. UINT32 Reserved:29; // 3:31 Reserved
  229. }r;
  230. } PAD_VAL;
  231. typedef union{
  232. UINT32 GPI;
  233. struct {
  234. UINT32 ihbpen:1; // 0 Pad high by pass enable
  235. UINT32 ihbpinen:1; // 1 Pad high by pass input
  236. UINT32 instaticen:1; // 2 TBD
  237. UINT32 ipstaticen:1; // 3 TBD
  238. UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
  239. UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
  240. UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
  241. }r;
  242. } PAD_DFT;
  243. //
  244. // GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
  245. //
  246. typedef enum {
  247. Native = 0xFF, // Native, no need to set PAD_VALUE
  248. GPI = 2, // GPI, input only in PAD_VALUE
  249. GPO = 4, // GPO, output only in PAD_VALUE
  250. GPIO = 0, // GPIO, input & output
  251. TRISTS = 6, // Tri-State
  252. GPIO_NONE
  253. } GPIO_USAGE;
  254. typedef enum {
  255. LO = 0,
  256. HI = 1,
  257. NA = 0xFF
  258. } GPO_D4;
  259. typedef enum {
  260. F0 = 0,
  261. F1 = 1,
  262. F2 = 2,
  263. F3 = 3,
  264. F4 = 4,
  265. F5 = 5,
  266. F6 = 6,
  267. F7 = 7
  268. } GPIO_FUNC_NUM;
  269. //
  270. // Mapping to CONF0 bit 27:24
  271. // Note: Assume "Direct Irq En" is not set, unless specially notified.
  272. //
  273. typedef enum {
  274. TRIG_ = 0,
  275. TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
  276. TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
  277. TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
  278. TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High
  279. TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low
  280. } INT_TYPE;
  281. typedef enum {
  282. P_20K_H, // Pull Up 20K
  283. P_20K_L, // Pull Down 20K
  284. P_10K_H, // Pull Up 10K
  285. P_10K_L, // Pull Down 10K
  286. P_2K_H, // Pull Up 2K
  287. P_2K_L, // Pull Down 2K
  288. P_NONE // Pull None
  289. } PULL_TYPE;
  290. #ifdef EFI_DEBUG
  291. #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
  292. #else
  293. #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
  294. #endif
  295. //
  296. // GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
  297. // NC = NCORE, SC = SCORE, SS= SSUS
  298. //
  299. typedef struct {
  300. #ifdef EFI_DEBUG
  301. char pad_name[32];// GPIO Pin Name for debug purpose
  302. #endif
  303. GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
  304. GPO_D4 gpod4; // GPO default value
  305. GPIO_FUNC_NUM func; // Function Number (F0~F7)
  306. INT_TYPE int_type; // Edge or Level trigger, low or high active
  307. PULL_TYPE pull; // Pull Up or Down
  308. UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
  309. } GPIO_CONF_PAD_INIT;
  310. //
  311. //typedef UINT64 BOARD_FEATURES
  312. //
  313. typedef struct _EFI_PLATFORM_INFO_HOB {
  314. UINT16 PlatformType; // Platform Type
  315. UINT8 BoardId; // Board ID
  316. UINT8 BoardRev; // Board Revision
  317. PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
  318. UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
  319. UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
  320. UINT8 ECOId; // ECO applied on platform
  321. UINT16 IohSku;
  322. UINT8 IohRevision;
  323. UINT16 IchSku;
  324. UINT8 IchRevision;
  325. EFI_PLATFORM_PCI_DATA PciData;
  326. EFI_PLATFORM_CPU_DATA CpuData;
  327. EFI_PLATFORM_MEM_DATA MemData;
  328. EFI_PLATFORM_SYS_DATA SysData;
  329. EFI_PLATFORM_IGD_DATA IgdData;
  330. UINT8 RevisonId; // Structure Revision ID
  331. EFI_PHYSICAL_ADDRESS PlatformCfioData;
  332. EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;
  333. EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;
  334. EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;
  335. EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;
  336. EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;
  337. EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;
  338. EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;
  339. EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;
  340. EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;
  341. UINT8 CfioEnabled;
  342. UINT32 SsidSvid;
  343. UINT16 AudioSubsystemDeviceId;
  344. UINT64 AcpiOemId;
  345. UINT64 AcpiOemTableId;
  346. UINT16 MemCfgID;
  347. } EFI_PLATFORM_INFO_HOB;
  348. #pragma pack()
  349. EFI_STATUS
  350. GetPlatformInfoHob (
  351. IN CONST EFI_PEI_SERVICES **PeiServices,
  352. OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
  353. );
  354. EFI_STATUS
  355. InstallPlatformClocksNotify (
  356. IN CONST EFI_PEI_SERVICES **PeiServices
  357. );
  358. EFI_STATUS
  359. InstallPlatformSysCtrlGPIONotify (
  360. IN CONST EFI_PEI_SERVICES **PeiServices
  361. );
  362. #endif