SataRegisters.h 8.7 KB

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  1. /** @file
  2. Header file for AHCI mode of ATA host controller.
  3. Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
  4. Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
  5. This program and the accompanying materials
  6. are licensed and made available under the terms and conditions of the BSD License
  7. which accompanies this distribution. The full text of the license may be found at
  8. http://opensource.org/licenses/bsd-license.php
  9. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11. **/
  12. #ifndef __SATA_REGISTERS_H__
  13. #define __SATA_REGISTERS_H__
  14. #define EFI_AHCI_BAR_INDEX 0x05
  15. #define EFI_AHCI_CAPABILITY_OFFSET 0x0000
  16. #define EFI_AHCI_CAP_SSS BIT27
  17. #define EFI_AHCI_CAP_SMPS BIT28
  18. #define EFI_AHCI_CAP_S64A BIT31
  19. #define EFI_AHCI_GHC_OFFSET 0x0004
  20. #define EFI_AHCI_GHC_RESET BIT0
  21. #define EFI_AHCI_GHC_IE BIT1
  22. #define EFI_AHCI_GHC_ENABLE BIT31
  23. #define EFI_AHCI_IS_OFFSET 0x0008
  24. #define EFI_AHCI_PI_OFFSET 0x000C
  25. #define EFI_AHCI_MAX_PORTS 32
  26. //
  27. // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  28. //
  29. #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
  30. //
  31. // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
  32. //
  33. #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
  34. //
  35. // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  36. //
  37. #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
  38. #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
  39. #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
  40. #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
  41. #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
  42. //
  43. // Each PRDT entry can point to a memory block up to 4M byte
  44. //
  45. #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
  46. #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
  47. #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
  48. #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
  49. #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
  50. #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
  51. #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
  52. #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
  53. #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
  54. #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
  55. #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
  56. #define EFI_AHCI_FIS_BIST_LENGTH 12
  57. #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
  58. #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
  59. #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
  60. #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
  61. #define EFI_AHCI_D2H_FIS_OFFSET 0x40
  62. #define EFI_AHCI_DMA_FIS_OFFSET 0x00
  63. #define EFI_AHCI_PIO_FIS_OFFSET 0x20
  64. #define EFI_AHCI_SDB_FIS_OFFSET 0x58
  65. #define EFI_AHCI_FIS_TYPE_MASK 0xFF
  66. #define EFI_AHCI_U_FIS_OFFSET 0x60
  67. //
  68. // Port register
  69. //
  70. #define EFI_AHCI_PORT_START 0x0100
  71. #define EFI_AHCI_PORT_REG_WIDTH 0x0080
  72. #define EFI_AHCI_PORT_CLB 0x0000
  73. #define EFI_AHCI_PORT_CLBU 0x0004
  74. #define EFI_AHCI_PORT_FB 0x0008
  75. #define EFI_AHCI_PORT_FBU 0x000C
  76. #define EFI_AHCI_PORT_IS 0x0010
  77. #define EFI_AHCI_PORT_IS_DHRS BIT0
  78. #define EFI_AHCI_PORT_IS_PSS BIT1
  79. #define EFI_AHCI_PORT_IS_SSS BIT2
  80. #define EFI_AHCI_PORT_IS_SDBS BIT3
  81. #define EFI_AHCI_PORT_IS_UFS BIT4
  82. #define EFI_AHCI_PORT_IS_DPS BIT5
  83. #define EFI_AHCI_PORT_IS_PCS BIT6
  84. #define EFI_AHCI_PORT_IS_DIS BIT7
  85. #define EFI_AHCI_PORT_IS_PRCS BIT22
  86. #define EFI_AHCI_PORT_IS_IPMS BIT23
  87. #define EFI_AHCI_PORT_IS_OFS BIT24
  88. #define EFI_AHCI_PORT_IS_INFS BIT26
  89. #define EFI_AHCI_PORT_IS_IFS BIT27
  90. #define EFI_AHCI_PORT_IS_HBDS BIT28
  91. #define EFI_AHCI_PORT_IS_HBFS BIT29
  92. #define EFI_AHCI_PORT_IS_TFES BIT30
  93. #define EFI_AHCI_PORT_IS_CPDS BIT31
  94. #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
  95. #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
  96. #define EFI_AHCI_PORT_OFFSET(PortNum) \
  97. (EFI_AHCI_PORT_START + ((PortNum) * EFI_AHCI_PORT_REG_WIDTH))
  98. #define EFI_AHCI_PORT_IE 0x0014
  99. #define EFI_AHCI_PORT_CMD 0x0018
  100. #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
  101. #define EFI_AHCI_PORT_CMD_ST BIT0
  102. #define EFI_AHCI_PORT_CMD_SUD BIT1
  103. #define EFI_AHCI_PORT_CMD_POD BIT2
  104. #define EFI_AHCI_PORT_CMD_CLO BIT3
  105. #define EFI_AHCI_PORT_CMD_CR BIT15
  106. #define EFI_AHCI_PORT_CMD_FRE BIT4
  107. #define EFI_AHCI_PORT_CMD_FR BIT14
  108. #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
  109. #define EFI_AHCI_PORT_CMD_PMA BIT17
  110. #define EFI_AHCI_PORT_CMD_HPCP BIT18
  111. #define EFI_AHCI_PORT_CMD_MPSP BIT19
  112. #define EFI_AHCI_PORT_CMD_CPD BIT20
  113. #define EFI_AHCI_PORT_CMD_ESP BIT21
  114. #define EFI_AHCI_PORT_CMD_ATAPI BIT24
  115. #define EFI_AHCI_PORT_CMD_DLAE BIT25
  116. #define EFI_AHCI_PORT_CMD_ALPE BIT26
  117. #define EFI_AHCI_PORT_CMD_ASP BIT27
  118. #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
  119. #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
  120. #define EFI_AHCI_PORT_TFD 0x0020
  121. #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
  122. #define EFI_AHCI_PORT_TFD_BSY BIT7
  123. #define EFI_AHCI_PORT_TFD_DRQ BIT3
  124. #define EFI_AHCI_PORT_TFD_ERR BIT0
  125. #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
  126. #define EFI_AHCI_PORT_SIG 0x0024
  127. #define EFI_AHCI_PORT_SSTS 0x0028
  128. #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
  129. #define EFI_AHCI_PORT_SSTS_DET 0x0001
  130. #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
  131. #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
  132. #define EFI_AHCI_PORT_SCTL 0x002C
  133. #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
  134. #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
  135. #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
  136. #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
  137. #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
  138. #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
  139. #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
  140. #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
  141. #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
  142. #define EFI_AHCI_PORT_SERR 0x0030
  143. #define EFI_AHCI_PORT_SERR_RDIE BIT0
  144. #define EFI_AHCI_PORT_SERR_RCE BIT1
  145. #define EFI_AHCI_PORT_SERR_TDIE BIT8
  146. #define EFI_AHCI_PORT_SERR_PCDIE BIT9
  147. #define EFI_AHCI_PORT_SERR_PE BIT10
  148. #define EFI_AHCI_PORT_SERR_IE BIT11
  149. #define EFI_AHCI_PORT_SERR_PRC BIT16
  150. #define EFI_AHCI_PORT_SERR_PIE BIT17
  151. #define EFI_AHCI_PORT_SERR_CW BIT18
  152. #define EFI_AHCI_PORT_SERR_BDE BIT19
  153. #define EFI_AHCI_PORT_SERR_DE BIT20
  154. #define EFI_AHCI_PORT_SERR_CRCE BIT21
  155. #define EFI_AHCI_PORT_SERR_HE BIT22
  156. #define EFI_AHCI_PORT_SERR_LSE BIT23
  157. #define EFI_AHCI_PORT_SERR_TSTE BIT24
  158. #define EFI_AHCI_PORT_SERR_UFT BIT25
  159. #define EFI_AHCI_PORT_SERR_EX BIT26
  160. #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
  161. #define EFI_AHCI_PORT_SACT 0x0034
  162. #define EFI_AHCI_PORT_CI 0x0038
  163. #define EFI_AHCI_PORT_SNTF 0x003C
  164. #endif