InitController.c 5.7 KB

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  1. /** @file
  2. Initialize SATA Phy, Serdes, and Controller.
  3. Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
  4. Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
  5. This program and the accompanying materials are licensed and made available
  6. under the terms and conditions of the BSD License which accompanies this
  7. distribution. The full text of the license may be found at
  8. http://opensource.org/licenses/bsd-license.php
  9. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11. **/
  12. #include "SataRegisters.h"
  13. #include <Library/AmdSataInitLib.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/IoLib.h>
  16. #include <Library/NonDiscoverableDeviceRegistrationLib.h>
  17. #include <Protocol/NonDiscoverableDevice.h>
  18. STATIC
  19. VOID
  20. ResetSataController (
  21. EFI_PHYSICAL_ADDRESS AhciBaseAddr
  22. )
  23. {
  24. // Make a minimal global reset for HBA regiser
  25. MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
  26. // Clear all interrupts
  27. MmioWrite32 (AhciBaseAddr + EFI_AHCI_PORT_IS, EFI_AHCI_PORT_IS_CLEAR);
  28. // Turn on interrupts and ensure that the HBA is working in AHCI mode
  29. MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET,
  30. EFI_AHCI_GHC_IE | EFI_AHCI_GHC_ENABLE);
  31. }
  32. STATIC
  33. VOID
  34. SetSataCapabilities (
  35. EFI_PHYSICAL_ADDRESS AhciBaseAddr
  36. )
  37. {
  38. UINT32 Capability;
  39. Capability = 0;
  40. if (FixedPcdGetBool (PcdSataSssSupport)) // Staggered Spin-Up Support bit
  41. Capability |= EFI_AHCI_CAP_SSS;
  42. if (FixedPcdGetBool (PcdSataSmpsSupport)) // Mechanical Presence Support bit
  43. Capability |= EFI_AHCI_CAP_SMPS;
  44. MmioOr32 (AhciBaseAddr + EFI_AHCI_CAPABILITY_OFFSET, Capability);
  45. }
  46. STATIC
  47. VOID
  48. InitializeSataPorts (
  49. EFI_PHYSICAL_ADDRESS AhciBaseAddr,
  50. UINTN PortCount
  51. )
  52. {
  53. INTN PortNum;
  54. BOOLEAN IsCpd;
  55. BOOLEAN IsMpsp;
  56. UINT32 PortRegAddr;
  57. UINT32 RegVal;
  58. // Set Ports Implemented (PI)
  59. MmioWrite32 (AhciBaseAddr + EFI_AHCI_PI_OFFSET, (1 << PortCount) - 1);
  60. IsCpd = FixedPcdGetBool (PcdSataPortCpd);
  61. IsMpsp = FixedPcdGetBool (PcdSataPortMpsp);
  62. if (!IsCpd && !IsMpsp) {
  63. return;
  64. }
  65. for (PortNum = 0; PortNum < PortCount; PortNum++) {
  66. PortRegAddr = EFI_AHCI_PORT_OFFSET (PortNum) + EFI_AHCI_PORT_CMD;
  67. RegVal = MmioRead32(AhciBaseAddr + PortRegAddr);
  68. if (IsCpd)
  69. RegVal |= EFI_AHCI_PORT_CMD_CPD;
  70. else
  71. RegVal &= ~EFI_AHCI_PORT_CMD_CPD;
  72. if (IsMpsp)
  73. RegVal |= EFI_AHCI_PORT_CMD_MPSP;
  74. else
  75. RegVal &= ~EFI_AHCI_PORT_CMD_MPSP;
  76. RegVal |= EFI_AHCI_PORT_CMD_HPCP;
  77. MmioWrite32(AhciBaseAddr + PortRegAddr, RegVal);
  78. }
  79. }
  80. STATIC
  81. EFI_STATUS
  82. InitializeSataController (
  83. EFI_PHYSICAL_ADDRESS AhciBaseAddr,
  84. UINTN SataPortCount,
  85. UINTN StartPort
  86. )
  87. {
  88. UINT8 SataChPerSerdes;
  89. UINT32 PortNum;
  90. UINT32 EvenPort;
  91. UINT32 OddPort;
  92. SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes);
  93. for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) {
  94. EvenPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> (PortNum * 2)) & 3;
  95. OddPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
  96. SataPhyInit ((StartPort + PortNum) / SataChPerSerdes, EvenPort, OddPort);
  97. }
  98. //
  99. // Reset SATA controller
  100. //
  101. ResetSataController (AhciBaseAddr);
  102. //
  103. // Set SATA capabilities
  104. //
  105. SetSataCapabilities (AhciBaseAddr);
  106. //
  107. // Set and intialize the Sata ports
  108. //
  109. InitializeSataPorts (AhciBaseAddr, SataPortCount);
  110. return RegisterNonDiscoverableMmioDevice (
  111. NonDiscoverableDeviceTypeAhci,
  112. NonDiscoverableDeviceDmaTypeCoherent,
  113. NULL,
  114. NULL,
  115. 1,
  116. AhciBaseAddr, SIZE_4KB);
  117. }
  118. #define STYX_SOC_VERSION_MASK 0xFFF
  119. #define STYX_SOC_VERSION_A0 0x000
  120. #define STYX_SOC_VERSION_B0 0x010
  121. #define STYX_SOC_VERSION_B1 0x011
  122. EFI_STATUS
  123. EFIAPI
  124. StyxSataPlatformDxeEntryPoint (
  125. IN EFI_HANDLE ImageHandle,
  126. IN EFI_SYSTEM_TABLE *SystemTable
  127. )
  128. {
  129. UINT32 PortNum;
  130. EFI_STATUS Status;
  131. //
  132. // Perform SATA workarounds
  133. //
  134. for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
  135. SetCwMinSata0 (PortNum);
  136. }
  137. Status = InitializeSataController (FixedPcdGet32(PcdSata0CtrlAxiSlvPort),
  138. FixedPcdGet8(PcdSata0PortCount), 0);
  139. if (EFI_ERROR (Status)) {
  140. DEBUG ((DEBUG_WARN, "%a: failed to initialize primary SATA controller!\n",
  141. __FUNCTION__));
  142. return Status;
  143. }
  144. for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
  145. SetPrdSingleSata0 (PortNum);
  146. }
  147. //
  148. // Ignore the second SATA controller on pre-B1 silicon
  149. //
  150. if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
  151. return EFI_SUCCESS;
  152. }
  153. if (FixedPcdGet8(PcdSata1PortCount) > 0) {
  154. for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
  155. SetCwMinSata1 (PortNum);
  156. }
  157. Status = InitializeSataController (FixedPcdGet32(PcdSata1CtrlAxiSlvPort),
  158. FixedPcdGet8(PcdSata1PortCount),
  159. FixedPcdGet8(PcdSata0PortCount));
  160. if (EFI_ERROR (Status)) {
  161. DEBUG ((DEBUG_WARN, "%a: failed to initialize secondary SATA controller!\n",
  162. __FUNCTION__));
  163. } else {
  164. for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
  165. SetPrdSingleSata1 (PortNum);
  166. }
  167. }
  168. }
  169. return EFI_SUCCESS;
  170. }