PlatInitDxe.c 6.0 KB

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  1. /** @file
  2. Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
  3. This program and the accompanying materials
  4. are licensed and made available under the terms and conditions of the BSD License
  5. which accompanies this distribution. The full text of the license may be found at
  6. http://opensource.org/licenses/bsd-license.php
  7. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  8. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  9. **/
  10. #include <Base.h>
  11. #include <PiDxe.h>
  12. #include <Uefi.h>
  13. #include <Library/ArmLib.h>
  14. #include <Library/BaseMemoryLib.h>
  15. #include <Library/DebugLib.h>
  16. #include <Library/HobLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <Library/UefiDriverEntryPoint.h>
  19. #include <Library/UefiBootServicesTableLib.h>
  20. #include <Common/CoreState.h>
  21. #include <Library/ArmSmcLib.h>
  22. #include <IndustryStandard/ArmStdSmc.h>
  23. #include <Guid/ArmMpCoreInfo.h>
  24. #include <Protocol/AmdMpCoreInfo.h>
  25. #include <Protocol/AmdMpBoot.h>
  26. STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 };
  27. STATIC AMD_MP_BOOT_PROTOCOL mAmdMpBootProtocol = { 0 };
  28. STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 };
  29. STATIC
  30. ARM_CORE_INFO *
  31. AmdStyxGetArmCoreInfoTable (
  32. OUT UINTN *NumEntries
  33. );
  34. STATIC
  35. EFI_STATUS
  36. AmdStyxGetPmuSpiFromMpId (
  37. IN UINT32 MpId,
  38. OUT UINT32 *PmuSpi
  39. );
  40. STATIC
  41. EFI_PHYSICAL_ADDRESS
  42. AmdStyxGetMpParkingBase (
  43. OUT UINTN *MpParkingSize
  44. );
  45. STATIC
  46. VOID
  47. AmdStyxParkSecondaryCore (
  48. ARM_CORE_INFO *ArmCoreInfo,
  49. EFI_PHYSICAL_ADDRESS SecondaryEntry
  50. );
  51. #pragma pack(push, 1)
  52. typedef struct _PMU_INFO {
  53. UINT32 MpId;
  54. UINT32 PmuSpi;
  55. } PMU_INFO;
  56. STATIC
  57. PMU_INFO mPmuInfo[] = {
  58. {0x000, 7},
  59. {0x001, 8},
  60. {0x100, 9},
  61. {0x101, 10},
  62. {0x200, 11},
  63. {0x201, 12},
  64. {0x300, 13},
  65. {0x301, 14}
  66. };
  67. #pragma pack(pop)
  68. #define MAX_CPUS sizeof(mPmuInfo) / sizeof(PMU_INFO)
  69. EFI_STATUS
  70. EFIAPI
  71. PlatInitDxeEntryPoint (
  72. IN EFI_HANDLE ImageHandle,
  73. IN EFI_SYSTEM_TABLE *SystemTable
  74. )
  75. {
  76. EFI_STATUS Status;
  77. EFI_PHYSICAL_ADDRESS MpParkingBase;
  78. UINTN MpParkingSize;
  79. ARM_CORE_INFO *ArmCoreInfoTable;
  80. UINTN ArmCoreCount;
  81. EFI_HANDLE Handle = NULL;
  82. DEBUG ((EFI_D_ERROR, "PlatInitDxe Loaded\n"));
  83. // Get core information
  84. ArmCoreCount = 0;
  85. ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount);
  86. ASSERT (ArmCoreInfoTable != NULL);
  87. ASSERT (ArmCoreCount != 0);
  88. // Install CoreInfo Protocol
  89. mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable;
  90. mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId;
  91. mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase;
  92. Status = gBS->InstallProtocolInterface (
  93. &Handle,
  94. &gAmdMpCoreInfoProtocolGuid,
  95. EFI_NATIVE_INTERFACE,
  96. (VOID *)&mAmdMpCoreInfoProtocol
  97. );
  98. ASSERT_EFI_ERROR (Status);
  99. // Install MP-Boot Protocol
  100. if (!FixedPcdGetBool (PcdPsciOsSupport) &&
  101. FixedPcdGetBool (PcdTrustedFWSupport)) {
  102. // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory
  103. MpParkingBase = 0;
  104. MpParkingSize = ArmCoreCount * SIZE_4KB;
  105. Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType,
  106. EFI_SIZE_TO_PAGES (MpParkingSize),
  107. &MpParkingBase);
  108. if (EFI_ERROR (Status) || MpParkingBase == 0) {
  109. DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase."));
  110. } else {
  111. mAmdMpBootInfo.MpParkingBase = MpParkingBase;
  112. mAmdMpBootInfo.MpParkingSize = MpParkingSize;
  113. mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable;
  114. mAmdMpBootInfo.ArmCoreCount = ArmCoreCount;
  115. mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore;
  116. mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo;
  117. Status = gBS->InstallProtocolInterface (
  118. &Handle,
  119. &gAmdMpBootProtocolGuid,
  120. EFI_NATIVE_INTERFACE,
  121. (VOID *)&mAmdMpBootProtocol
  122. );
  123. if (EFI_ERROR (Status)) {
  124. DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol."));
  125. gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize));
  126. }
  127. }
  128. }
  129. return Status;
  130. }
  131. STATIC
  132. ARM_CORE_INFO *
  133. AmdStyxGetArmCoreInfoTable (
  134. OUT UINTN *NumEntries
  135. )
  136. {
  137. EFI_HOB_GUID_TYPE *Hob;
  138. ASSERT (NumEntries != NULL);
  139. Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
  140. if (Hob == NULL) {
  141. return NULL;
  142. }
  143. *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
  144. return GET_GUID_HOB_DATA (Hob);
  145. }
  146. STATIC
  147. EFI_STATUS
  148. AmdStyxGetPmuSpiFromMpId (
  149. IN UINT32 MpId,
  150. OUT UINT32 *PmuSpi
  151. )
  152. {
  153. UINT32 i;
  154. for (i = 0; i < MAX_CPUS; ++i) {
  155. if (mPmuInfo[ i ].MpId == MpId) {
  156. *PmuSpi = mPmuInfo[ i ].PmuSpi;
  157. return EFI_SUCCESS;
  158. }
  159. }
  160. return EFI_INVALID_PARAMETER;
  161. }
  162. STATIC
  163. EFI_PHYSICAL_ADDRESS
  164. AmdStyxGetMpParkingBase (
  165. OUT UINTN *MpParkingSize
  166. )
  167. {
  168. ASSERT (MpParkingSize != NULL);
  169. *MpParkingSize = mAmdMpBootInfo.MpParkingBase;
  170. return mAmdMpBootInfo.MpParkingBase;
  171. }
  172. STATIC
  173. VOID
  174. AmdStyxParkSecondaryCore (
  175. ARM_CORE_INFO *ArmCoreInfo,
  176. EFI_PHYSICAL_ADDRESS SecondaryEntry
  177. )
  178. {
  179. ARM_SMC_ARGS SmcRegs = {0};
  180. UINTN MpId;
  181. MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId);
  182. SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64;
  183. SmcRegs.Arg1 = MpId;
  184. SmcRegs.Arg2 = SecondaryEntry;
  185. SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext);
  186. ArmCallSmc (&SmcRegs);
  187. if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS ||
  188. SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) {
  189. DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId));
  190. } else {
  191. DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId));
  192. }
  193. }