MpBootDxe.c 5.8 KB

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  1. /** @file
  2. Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
  3. This program and the accompanying materials
  4. are licensed and made available under the terms and conditions of the BSD License
  5. which accompanies this distribution. The full text of the license may be found at
  6. http://opensource.org/licenses/bsd-license.php
  7. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  8. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  9. **/
  10. #include <Library/ArmLib.h>
  11. #include <Library/ArmSmcLib.h>
  12. #include <Library/BaseMemoryLib.h>
  13. #include <Library/CacheMaintenanceLib.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/UefiDriverEntryPoint.h>
  16. #include <Library/UefiBootServicesTableLib.h>
  17. #include <Guid/ArmMpCoreInfo.h>
  18. #include <Protocol/AmdMpBoot.h>
  19. /* These externs are used to relocate our Pen code into pre-allocated memory */
  20. extern VOID *SecondariesPenStart;
  21. extern VOID *SecondariesPenEnd;
  22. extern UINTN *AsmParkingBase;
  23. extern UINTN *AsmMailboxBase;
  24. STATIC
  25. EFI_PHYSICAL_ADDRESS
  26. ConfigurePen (
  27. IN EFI_PHYSICAL_ADDRESS MpParkingBase,
  28. IN UINTN MpParkingSize,
  29. IN ARM_CORE_INFO *ArmCoreInfoTable,
  30. IN UINTN ArmCoreCount
  31. )
  32. {
  33. EFI_PHYSICAL_ADDRESS PenBase;
  34. UINTN PenSize;
  35. UINTN MailboxBase;
  36. UINTN CoreNum;
  37. UINTN CoreMailbox;
  38. UINTN CoreParking;
  39. //
  40. // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#.
  41. // For details, refer to the "Multi-processor Startup for ARM Platforms" document:
  42. // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx
  43. //
  44. PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64));
  45. PenSize = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart;
  46. // Relocate the Pen code
  47. CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize);
  48. // Put spin-table mailboxes below the pen code so we know where they are relative to code.
  49. // Make sure this is 8 byte aligned.
  50. MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart);
  51. if (MailboxBase % sizeof(UINT64) != 0) {
  52. MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64);
  53. }
  54. // Update variables used in the Pen code
  55. *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase;
  56. *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase;
  57. for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
  58. // Clear the jump address at spin-table slot
  59. CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64);
  60. *((UINTN*)(CoreMailbox)) = 0x0;
  61. // Clear the jump address and set Core# at mp-parking slot
  62. CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB;
  63. *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0;
  64. *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum;
  65. // Update table entry to be consumed by FDT parser
  66. ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox;
  67. }
  68. // flush the cache before launching secondary cores
  69. WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize);
  70. return PenBase;
  71. }
  72. EFI_STATUS
  73. EFIAPI
  74. MpBootDxeEntryPoint (
  75. IN EFI_HANDLE ImageHandle,
  76. IN EFI_SYSTEM_TABLE *SystemTable
  77. )
  78. {
  79. EFI_STATUS Status;
  80. AMD_MP_BOOT_PROTOCOL *MpBootProtocol;
  81. EFI_PHYSICAL_ADDRESS MpParkingBase;
  82. UINTN MpParkingSize;
  83. ARM_CORE_INFO *ArmCoreInfoTable;
  84. UINTN ArmCoreCount;
  85. UINTN CoreNum;
  86. EFI_PHYSICAL_ADDRESS PenBase;
  87. DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n"));
  88. MpBootProtocol = NULL;
  89. Status = gBS->LocateProtocol (
  90. &gAmdMpBootProtocolGuid,
  91. NULL,
  92. (VOID **)&MpBootProtocol
  93. );
  94. if (EFI_ERROR (Status) || MpBootProtocol == NULL) {
  95. DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n"));
  96. return EFI_UNSUPPORTED;
  97. }
  98. if ((VOID *)MpBootProtocol->MpBootInfo == NULL) {
  99. DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n"));
  100. return EFI_UNSUPPORTED;
  101. }
  102. MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase;
  103. if ((VOID *)MpParkingBase == NULL) {
  104. DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n"));
  105. return EFI_UNSUPPORTED;
  106. }
  107. if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) {
  108. DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n"));
  109. return EFI_UNSUPPORTED;
  110. }
  111. ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable;
  112. if (ArmCoreInfoTable == NULL) {
  113. DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n"));
  114. return EFI_UNSUPPORTED;
  115. }
  116. ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount;
  117. if (ArmCoreCount < 2) {
  118. DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount));
  119. return EFI_UNSUPPORTED;
  120. }
  121. MpParkingSize = ArmCoreCount * SIZE_4KB;
  122. if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) {
  123. DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n",
  124. MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount));
  125. return EFI_UNSUPPORTED;
  126. }
  127. if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) {
  128. DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n"));
  129. return EFI_UNSUPPORTED;
  130. }
  131. // Move secondary cores to our new Pen
  132. PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount);
  133. for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
  134. MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase);
  135. }
  136. return EFI_SUCCESS;
  137. }