Iort.c 16 KB

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  1. /** @file
  2. Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
  3. This program and the accompanying materials
  4. are licensed and made available under the terms and conditions of the BSD License
  5. which accompanies this distribution. The full text of the license may be found at
  6. http://opensource.org/licenses/bsd-license.php
  7. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  8. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  9. **/
  10. #include <AmdStyxAcpiLib.h>
  11. #include <IndustryStandard/IoRemappingTable.h>
  12. #define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
  13. #define STYX_PCIE_SMMU_BASE 0xE0A00000
  14. #define STYX_PCIE_SMMU_SIZE 0x10000
  15. #define STYX_PCIE_SMMU_INTERRUPT 0x16d
  16. #define STYX_ETH0_SMMU_BASE 0xE0600000
  17. #define STYX_ETH0_SMMU_SIZE 0x10000
  18. #define STYX_ETH0_SMMU_INTERRUPT 0x170
  19. #define STYX_ETH1_SMMU_BASE 0xE0800000
  20. #define STYX_ETH1_SMMU_SIZE 0x10000
  21. #define STYX_ETH1_SMMU_INTERRUPT 0x16f
  22. #define STYX_SATA0_SMMU_BASE 0xE0200000
  23. #define STYX_SATA0_SMMU_SIZE 0x10000
  24. #define STYX_SATA0_SMMU_INTERRUPT 0x16c
  25. #define STYX_SATA1_SMMU_BASE 0xE0C00000
  26. #define STYX_SATA1_SMMU_SIZE 0x10000
  27. #define STYX_SATA1_SMMU_INTERRUPT 0x16b
  28. #pragma pack(1)
  29. typedef struct {
  30. EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
  31. EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1];
  32. } STYX_SMMU_NODE;
  33. typedef struct {
  34. EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
  35. EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
  36. } STYX_RC_NODE;
  37. typedef struct {
  38. EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node;
  39. CONST CHAR8 Name[11];
  40. EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32];
  41. } STYX_NC_NODE;
  42. typedef struct {
  43. EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
  44. STYX_SMMU_NODE PciSmmuNode;
  45. STYX_RC_NODE PciRcNode;
  46. #if DO_XGBE
  47. STYX_SMMU_NODE Eth0SmmuNode;
  48. STYX_NC_NODE Eth0NamedNode;
  49. STYX_SMMU_NODE Eth1SmmuNode;
  50. STYX_NC_NODE Eth1NamedNode;
  51. #endif
  52. STYX_SMMU_NODE Sata0SmmuNode;
  53. STYX_NC_NODE Sata0NamedNode;
  54. STYX_SMMU_NODE Sata1SmmuNode;
  55. STYX_NC_NODE Sata1NamedNode;
  56. } STYX_IO_REMAPPING_STRUCTURE;
  57. #define __STYX_SMMU_NODE(Base, Size, Irq) \
  58. { \
  59. { \
  60. EFI_ACPI_IORT_TYPE_SMMUv1v2, \
  61. sizeof(STYX_SMMU_NODE), \
  62. 0x0, \
  63. 0x0, \
  64. 0x0, \
  65. 0x0, \
  66. }, \
  67. Base, \
  68. Size, \
  69. EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \
  70. EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \
  71. FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
  72. SMMU_NSgIrpt), \
  73. 0x1, \
  74. sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
  75. 0x0, \
  76. 0x0, \
  77. Irq, \
  78. EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
  79. 0x0, \
  80. 0x0, \
  81. }, { \
  82. { \
  83. Irq, \
  84. EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
  85. }, \
  86. }
  87. #define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \
  88. { \
  89. In, \
  90. Num, \
  91. Out, \
  92. FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
  93. Flags \
  94. }
  95. #define __STYX_ID_MAPPING_SINGLE(Out, Ref) \
  96. { \
  97. 0x0, \
  98. 0x0, \
  99. Out, \
  100. FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
  101. EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \
  102. }
  103. #define __STYX_NAMED_COMPONENT_NODE(Name) \
  104. { \
  105. { \
  106. EFI_ACPI_IORT_TYPE_NAMED_COMP, \
  107. sizeof(STYX_NC_NODE), \
  108. 0x0, \
  109. 0x0, \
  110. 0x20, \
  111. FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \
  112. }, \
  113. 0x0, \
  114. EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \
  115. 0x0, \
  116. 0x0, \
  117. EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \
  118. EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \
  119. 40, \
  120. }, \
  121. Name
  122. STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = {
  123. {
  124. AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
  125. STYX_IO_REMAPPING_STRUCTURE,
  126. EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
  127. #if DO_XGBE
  128. 10, // NumNodes
  129. #else
  130. 6, // NumNodes
  131. #endif
  132. sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
  133. 0 // Reserved
  134. }, {
  135. // PciSmmuNode
  136. __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE,
  137. STYX_PCIE_SMMU_SIZE,
  138. STYX_PCIE_SMMU_INTERRUPT)
  139. }, {
  140. // PciRcNode
  141. {
  142. {
  143. EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
  144. sizeof(STYX_RC_NODE), // Length
  145. 0x0, // Revision
  146. 0x0, // Reserved
  147. 0x1, // NumIdMappings
  148. FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference
  149. },
  150. EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
  151. 0x0, // AllocationHints
  152. 0x0, // Reserved
  153. EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
  154. EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
  155. EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
  156. 0x0, // PciSegmentNumber
  157. }, {
  158. __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0),
  159. }
  160. #if DO_XGBE
  161. }, {
  162. // Eth0SmmuNode
  163. __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE,
  164. STYX_ETH0_SMMU_SIZE,
  165. STYX_ETH0_SMMU_INTERRUPT)
  166. }, {
  167. // Eth0NamedNode
  168. __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"),
  169. {
  170. __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode),
  171. __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode),
  172. __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode),
  173. __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode),
  174. __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode),
  175. __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode),
  176. __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode),
  177. __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode),
  178. __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode),
  179. __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode),
  180. __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode),
  181. __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode),
  182. __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode),
  183. __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode),
  184. __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode),
  185. __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode),
  186. __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode),
  187. __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode),
  188. __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode),
  189. __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode),
  190. __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode),
  191. __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode),
  192. __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode),
  193. __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode),
  194. __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode),
  195. __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode),
  196. __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode),
  197. __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode),
  198. __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode),
  199. __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode),
  200. __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode),
  201. __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode),
  202. }
  203. }, {
  204. // Eth1SmmuNode
  205. __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE,
  206. STYX_ETH1_SMMU_SIZE,
  207. STYX_ETH1_SMMU_INTERRUPT)
  208. }, {
  209. // Eth1NamedNode
  210. __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"),
  211. {
  212. __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode),
  213. __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode),
  214. __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode),
  215. __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode),
  216. __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode),
  217. __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode),
  218. __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode),
  219. __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode),
  220. __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode),
  221. __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode),
  222. __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode),
  223. __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode),
  224. __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode),
  225. __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode),
  226. __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode),
  227. __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode),
  228. __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode),
  229. __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode),
  230. __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode),
  231. __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode),
  232. __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode),
  233. __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode),
  234. __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode),
  235. __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode),
  236. __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode),
  237. __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode),
  238. __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode),
  239. __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode),
  240. __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode),
  241. __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode),
  242. __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode),
  243. __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode),
  244. }
  245. #endif
  246. }, {
  247. // Sata0SmmuNode
  248. __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE,
  249. STYX_SATA0_SMMU_SIZE,
  250. STYX_SATA0_SMMU_INTERRUPT)
  251. }, {
  252. // Sata0NamedNode
  253. __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"),
  254. {
  255. __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode),
  256. __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode),
  257. __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode),
  258. __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode),
  259. __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode),
  260. __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode),
  261. __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode),
  262. __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode),
  263. __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode),
  264. __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode),
  265. __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode),
  266. __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode),
  267. __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode),
  268. __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode),
  269. __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode),
  270. __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode),
  271. __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode),
  272. __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode),
  273. __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode),
  274. __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode),
  275. __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode),
  276. __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode),
  277. __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode),
  278. __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode),
  279. __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode),
  280. __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode),
  281. __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode),
  282. __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode),
  283. __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode),
  284. __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode),
  285. __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode),
  286. __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode),
  287. }
  288. }, {
  289. // Sata1SmmuNode
  290. __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE,
  291. STYX_SATA1_SMMU_SIZE,
  292. STYX_SATA1_SMMU_INTERRUPT)
  293. }, {
  294. // Sata1NamedNode
  295. __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"),
  296. {
  297. __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode),
  298. __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode),
  299. __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode),
  300. __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode),
  301. __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode),
  302. __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode),
  303. __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode),
  304. __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode),
  305. __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode),
  306. __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode),
  307. __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode),
  308. __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode),
  309. __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode),
  310. __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode),
  311. __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode),
  312. __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode),
  313. __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode),
  314. __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode),
  315. __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode),
  316. __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode),
  317. __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode),
  318. __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode),
  319. __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode),
  320. __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode),
  321. __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode),
  322. __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode),
  323. __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode),
  324. __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode),
  325. __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode),
  326. __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode),
  327. __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode),
  328. __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode),
  329. }
  330. }
  331. };
  332. #pragma pack()
  333. #define STYX_SOC_VERSION_MASK 0xFFF
  334. #define STYX_SOC_VERSION_A0 0x000
  335. #define STYX_SOC_VERSION_B0 0x010
  336. #define STYX_SOC_VERSION_B1 0x011
  337. EFI_ACPI_DESCRIPTION_HEADER *
  338. IortHeader (
  339. VOID
  340. )
  341. {
  342. if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
  343. //
  344. // Silicon revisions prior to B1 have only one SATA port,
  345. // so omit the nodes of the second port in this case.
  346. //
  347. AcpiIort.Iort.NumNodes -= 2;
  348. }
  349. return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header;
  350. }