Platform.h 12 KB

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  1. /** @file
  2. * Platform headers
  3. *
  4. * Copyright 2020 NXP
  5. * Copyright 2020 Puresoftware Ltd
  6. *
  7. * SPDX-License-Identifier: BSD-2-Clause-Patent
  8. *
  9. **/
  10. #ifndef LX2160ARDB_PLATFORM_H
  11. #define LX2160ARDB_PLATFORM_H
  12. #define EFI_ACPI_ARM_OEM_REVISION 0x00000000
  13. // Soc defines
  14. #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
  15. #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
  16. #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
  17. #define SVR_LX2160A 0x873600
  18. // Gic
  19. #define GIC_VERSION 3
  20. #define GICD_BASE 0x6000000
  21. #define GICI_BASE 0x6020000
  22. #define GICR_BASE 0x06200000
  23. #define GICR_LEN 0x200000
  24. #define GICC_BASE 0x0c0c0000
  25. #define GICH_BASE 0x0c0d0000
  26. #define GICV_BASE 0x0c0e0000
  27. // UART
  28. #define UART0_BASE 0x21C0000
  29. #define UART1_BASE 0x21D0000
  30. #define UART2_BASE 0x21E0000
  31. #define UART3_BASE 0x21F0000
  32. #define UART0_IT 64
  33. #define UART1_IT 65
  34. #define UART2_IT 104
  35. #define UART3_IT 105
  36. #define UART_LEN 0x10000
  37. #define SPCR_FLOW_CONTROL_NONE 0
  38. // Timer
  39. #define TIMER_BLOCK_COUNT 1
  40. #define TIMER_FRAME_COUNT 4
  41. #define TIMER_WATCHDOG_COUNT 1
  42. #define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase
  43. #define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase
  44. #define TIMER_GT_BLOCK_0_ADDRESS 0x2890000 // a.k.a CNTCTLBase (Secure)
  45. #define TIMER_GT_BASE_0_ADDRESS 0x28A0000 // a.k.a CNTBase0
  46. #define TIMER_GT_BASE_1_ADDRESS 0x28B0000 // a.k.a CNTBase1
  47. #define TIMER_GT_BASE_2_ADDRESS 0x28C0000 // a.k.a CNTBase2
  48. #define TIMER_GT_BASE_3_ADDRESS 0x28D0000 // a.k.a CNTBase3
  49. #define TIMER_GT_BASE_0_EL0_ADDRESS 0x28E0000 // a.k.a CNTBase0EL0
  50. #define TIMER_GT_BASE_2_EL0_ADDRESS 0x28F0000 // a.k.a CNTBase2EL0
  51. #define TIMER_WDT0_REFRESH_BASE 0x2390000
  52. #define TIMER_WDT0_CONTROL_BASE 0x23A0000
  53. #define TIMER_SEC_IT 29
  54. #define TIMER_NON_SEC_IT 30
  55. #define TIMER_VIRT_IT 27
  56. #define TIMER_HYP_IT 26
  57. #define TIMER_FRAME0_IT 78
  58. #define TIMER_FRAME1_IT 79
  59. #define TIMER_FRAME2_IT 92
  60. #define TIMER_FRAME3_IT 93
  61. #define TIMER_WDT0_IT 91
  62. #define DEFAULT_PLAT_FREQ 700000000
  63. // Mcfg
  64. #define LX2160A_PCI_SEG0_CONFIG_BASE 0x9000000000
  65. #define LX2160A_PCI_SEG0 0x2
  66. #define LX2160A_PCI_SEG_BUSNUM_MIN 0x0
  67. #define LX2160A_PCI_SEG_BUSNUM_MAX 0xff
  68. #define LX2160A_PCI_SEG1_CONFIG_BASE 0xA000000000
  69. #define LX2160A_PCI_SEG1 0x4
  70. // Platform specific info needed by Configuration Manager
  71. #define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','X','2','1','6','0',' ',' ')
  72. #define PLAT_PCI_SEG0_CONFIG_BASE LX2160A_PCI_SEG0_CONFIG_BASE
  73. #define PLAT_PCI_SEG0 LX2160A_PCI_SEG0
  74. #define PLAT_PCI_SEG_BUSNUM_MIN LX2160A_PCI_SEG_BUSNUM_MIN
  75. #define PLAT_PCI_SEG_BUSNUM_MAX LX2160A_PCI_SEG_BUSNUM_MAX
  76. #define PLAT_PCI_SEG1_CONFIG_BASE LX2160A_PCI_SEG1_CONFIG_BASE
  77. #define PLAT_PCI_SEG1 LX2160A_PCI_SEG1
  78. #define PLAT_GIC_VERSION GIC_VERSION
  79. #define PLAT_GICD_BASE GICD_BASE
  80. #define PLAT_GICI_BASE GICI_BASE
  81. #define PLAT_GICR_BASE GICR_BASE
  82. #define PLAT_GICR_LEN GICR_LEN
  83. #define PLAT_GICC_BASE GICC_BASE
  84. #define PLAT_GICH_BASE GICH_BASE
  85. #define PLAT_GICV_BASE GICV_BASE
  86. #define PLAT_CPU_COUNT 16
  87. #define PLAT_GTBLOCK_COUNT 1
  88. #define PLAT_GTFRAME_COUNT 4
  89. #define PLAT_PCI_CONFG_COUNT 2
  90. #define PLAT_WATCHDOG_COUNT 1
  91. #define PLAT_GIC_REDISTRIBUTOR_COUNT 1
  92. #define PLAT_GIC_ITS_COUNT 1
  93. /* GIC CPU Interface information
  94. GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency)
  95. */
  96. #define PLAT_GIC_CPU_INTERFACE { \
  97. GICC_ENTRY (0, GET_MPID (0, 0), 23, 0x19, 0), \
  98. GICC_ENTRY (1, GET_MPID (0, 1), 23, 0x19, 0), \
  99. GICC_ENTRY (2, GET_MPID (1, 0), 23, 0x19, 0), \
  100. GICC_ENTRY (3, GET_MPID (1, 1), 23, 0x19, 0), \
  101. GICC_ENTRY (4, GET_MPID (2, 0), 23, 0x19, 0), \
  102. GICC_ENTRY (5, GET_MPID (2, 1), 23, 0x19, 0), \
  103. GICC_ENTRY (6, GET_MPID (3, 0), 23, 0x19, 0), \
  104. GICC_ENTRY (7, GET_MPID (3, 1), 23, 0x19, 0), \
  105. GICC_ENTRY (8, GET_MPID (4, 0), 23, 0x19, 0), \
  106. GICC_ENTRY (9, GET_MPID (4, 1), 23, 0x19, 0), \
  107. GICC_ENTRY (10, GET_MPID (5, 0), 23, 0x19, 0), \
  108. GICC_ENTRY (11, GET_MPID (5, 1), 23, 0x19, 0), \
  109. GICC_ENTRY (12, GET_MPID (6, 0), 23, 0x19, 0), \
  110. GICC_ENTRY (13, GET_MPID (6, 1), 23, 0x19, 0), \
  111. GICC_ENTRY (14, GET_MPID (7, 0), 23, 0x19, 0), \
  112. GICC_ENTRY (15, GET_MPID (7, 1), 23, 0x19, 0) \
  113. }
  114. // watchdogs
  115. #define PLAT_WATCHDOG_INFO \
  116. { \
  117. TIMER_WDT0_CONTROL_BASE, \
  118. TIMER_WDT0_REFRESH_BASE, \
  119. TIMER_WDT0_IT, \
  120. SBSA_WATCHDOG_FLAGS \
  121. } \
  122. #define PLAT_TIMER_BLOCK_INFO \
  123. { \
  124. { \
  125. TIMER_GT_BLOCK_0_ADDRESS, \
  126. PLAT_GTFRAME_COUNT, \
  127. (CM_OBJECT_TOKEN)((UINT8*)&FslPlatformRepositoryInfo + \
  128. OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, GTBlock0TimerInfo)) \
  129. } \
  130. } \
  131. #define PLAT_TIMER_FRAME_INFO \
  132. { \
  133. { \
  134. 0, /* UINT8 GTFrameNumber */ \
  135. TIMER_GT_BASE_0_ADDRESS, /* UINT64 CntBaseX */ \
  136. TIMER_GT_BASE_0_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \
  137. TIMER_FRAME0_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
  138. GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
  139. TIMER_FRAME0_IT, /* UINT32 GTxVirtualTimerGSIV */ \
  140. GTDT_FRAME_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
  141. 0 /* UINT32 GTxCommonFlags */ \
  142. }, /* Gtdt.Frames[0] */ \
  143. { \
  144. 1, /* UINT8 GTFrameNumber */ \
  145. TIMER_GT_BASE_1_ADDRESS, /* UINT64 CntBaseX */ \
  146. GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \
  147. TIMER_FRAME1_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
  148. GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
  149. 0, /* UINT32 GTxVirtualTimerGSIV */ \
  150. 0, /* UINT32 GTxVirtualTimerFlags */ \
  151. GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
  152. }, /* Gtdt.Frames[1] */ \
  153. { \
  154. 2, /* UINT8 GTFrameNumber */ \
  155. TIMER_GT_BASE_2_ADDRESS, /* UINT64 CntBaseX */ \
  156. TIMER_GT_BASE_2_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \
  157. TIMER_FRAME2_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
  158. GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
  159. 0, /* UINT32 GTxVirtualTimerGSIV */ \
  160. 0, /* UINT32 GTxVirtualTimerFlags */ \
  161. GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
  162. },/* Gtdt.Frames[2] */ \
  163. { \
  164. 3, /* UINT8 GTFrameNumber */ \
  165. TIMER_GT_BASE_3_ADDRESS, /* UINT64 CntBaseX */ \
  166. GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \
  167. TIMER_FRAME3_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
  168. GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
  169. 0, /* UINT32 GTxVirtualTimerGSIV */ \
  170. 0, /* UINT32 GTxVirtualTimerFlags */ \
  171. GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
  172. }, /* Gtdt.Frames[3] */ \
  173. } \
  174. #define PLAT_GIC_DISTRIBUTOR_INFO \
  175. { \
  176. PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
  177. 0, /* UINT32 SystemVectorBase */ \
  178. PLAT_GIC_VERSION /* UINT8 GicVersion */ \
  179. } \
  180. #define PLAT_GIC_REDISTRIBUTOR_INFO \
  181. { \
  182. PLAT_GICR_BASE, /* UINT64 DiscoveryRangeBaseAddress */ \
  183. PLAT_GICR_LEN /* UINT32 DiscoveryRangeLength */ \
  184. } \
  185. #define PLAT_GIC_ITS_INFO \
  186. { \
  187. 0, /* UINT32 GIC ITS ID */ \
  188. PLAT_GICI_BASE, /* UINT64 The 64-bit physical address for ITS */ \
  189. 0 /* UINT32 Populate the GIC ITS affinity in SRAT. */ \
  190. } \
  191. #define PLAT_MCFG_INFO \
  192. { \
  193. { \
  194. PLAT_PCI_SEG0_CONFIG_BASE, \
  195. PLAT_PCI_SEG0, \
  196. PLAT_PCI_SEG_BUSNUM_MIN, \
  197. PLAT_PCI_SEG_BUSNUM_MAX, \
  198. }, \
  199. { \
  200. PLAT_PCI_SEG1_CONFIG_BASE, \
  201. PLAT_PCI_SEG1, \
  202. PLAT_PCI_SEG_BUSNUM_MIN, \
  203. PLAT_PCI_SEG_BUSNUM_MAX, \
  204. } \
  205. } \
  206. #define PLAT_SPCR_INFO \
  207. { \
  208. UART0_BASE, \
  209. UART0_IT, \
  210. 115200, \
  211. 0, \
  212. EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART \
  213. } \
  214. #endif // LX2160ARDB_PLATFORM_H