PchSpi.c 5.0 KB

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  1. /** @file
  2. PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
  3. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PchSpi.h"
  7. //
  8. // Global variables
  9. //
  10. GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
  11. //
  12. // mPchSpiResvMmioAddr keeps the reserved MMIO range assiged to SPI.
  13. // In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
  14. // won't overlap with SMRAM range, and trusted.
  15. //
  16. GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
  17. /**
  18. <b>SPI Runtime SMM Module Entry Point</b>\n
  19. - <b>Introduction</b>\n
  20. The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
  21. - @pre
  22. - EFI_SMM_BASE2_PROTOCOL
  23. - Documented in System Management Mode Core Interface Specification .
  24. - @result
  25. The SPI SMM driver produces @link _PCH_SPI2_PROTOCOL PCH_SPI2_PROTOCOL @endlink with GUID
  26. gPchSmmSpi2ProtocolGuid which is different from SPI RUNTIME driver.
  27. - <b>Integration Check List</b>\n
  28. - This driver supports Descriptor Mode only.
  29. - This driver supports Hardware Sequence only.
  30. - When using SMM SPI Protocol to perform flash access in an SMI handler,
  31. and the SMI occurrence is asynchronous to normal mode code execution,
  32. proper synchronization mechanism must be applied, e.g. disable SMI before
  33. the normal mode SendSpiCmd() starts and re-enable SMI after
  34. the normal mode SendSpiCmd() completes.
  35. @note The implementation of SendSpiCmd() uses GBL_SMI_EN in
  36. SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
  37. not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
  38. So the synchronization at caller level is likely needed.
  39. @param[in] ImageHandle Image handle of this driver.
  40. @param[in] SystemTable Global system service table.
  41. @retval EFI_SUCCESS Initialization complete.
  42. @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
  43. @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
  44. @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
  45. **/
  46. EFI_STATUS
  47. EFIAPI
  48. InstallPchSpi (
  49. IN EFI_HANDLE ImageHandle,
  50. IN EFI_SYSTEM_TABLE *SystemTable
  51. )
  52. {
  53. EFI_STATUS Status;
  54. //
  55. // Init PCH spi reserved MMIO address.
  56. //
  57. mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
  58. ///
  59. /// Allocate pool for SPI protocol instance
  60. ///
  61. Status = gSmst->SmmAllocatePool (
  62. EfiRuntimeServicesData, /// MemoryType don't care
  63. sizeof (SPI_INSTANCE),
  64. (VOID **) &mSpiInstance
  65. );
  66. if (EFI_ERROR (Status)) {
  67. return Status;
  68. }
  69. if (mSpiInstance == NULL) {
  70. return EFI_OUT_OF_RESOURCES;
  71. }
  72. ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
  73. ///
  74. /// Initialize the SPI protocol instance
  75. ///
  76. Status = SpiProtocolConstructor (mSpiInstance);
  77. if (EFI_ERROR (Status)) {
  78. return Status;
  79. }
  80. //
  81. // Install the SMM PCH_SPI2_PROTOCOL interface
  82. //
  83. Status = gSmst->SmmInstallProtocolInterface (
  84. &(mSpiInstance->Handle),
  85. &gPchSmmSpi2ProtocolGuid,
  86. EFI_NATIVE_INTERFACE,
  87. &(mSpiInstance->SpiProtocol)
  88. );
  89. if (EFI_ERROR (Status)) {
  90. gSmst->SmmFreePool (mSpiInstance);
  91. return EFI_DEVICE_ERROR;
  92. }
  93. return EFI_SUCCESS;
  94. }
  95. /**
  96. Acquire PCH spi mmio address.
  97. It is not expected for this BAR0 to change because the SPI device is hidden
  98. from the OS for SKL PCH LP/H B stepping and above (refer to section 3.5.1),
  99. but if it is ever different from the preallocated address, reassign it back.
  100. In SMM, it always override the BAR0 and returns the reserved MMIO range for SPI.
  101. @param[in] SpiInstance Pointer to SpiInstance to initialize
  102. @retval PchSpiBar0 return SPI MMIO address
  103. **/
  104. UINTN
  105. AcquireSpiBar0 (
  106. IN SPI_INSTANCE *SpiInstance
  107. )
  108. {
  109. //
  110. // SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
  111. //
  112. return mSpiResvMmioAddr;
  113. }
  114. /**
  115. Release pch spi mmio address. Do nothing.
  116. @param[in] SpiInstance Pointer to SpiInstance to initialize
  117. @retval None
  118. **/
  119. VOID
  120. ReleaseSpiBar0 (
  121. IN SPI_INSTANCE *SpiInstance
  122. )
  123. {
  124. }
  125. /**
  126. This function is a hook for Spi to disable BIOS Write Protect
  127. @retval EFI_SUCCESS The protocol instance was properly initialized
  128. @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
  129. **/
  130. EFI_STATUS
  131. EFIAPI
  132. DisableBiosWriteProtect (
  133. VOID
  134. )
  135. {
  136. return EFI_SUCCESS;
  137. }
  138. /**
  139. This function is a hook for Spi to enable BIOS Write Protect
  140. **/
  141. VOID
  142. EFIAPI
  143. EnableBiosWriteProtect (
  144. VOID
  145. )
  146. {
  147. }