FspWrapperPlatformSecLib.c 7.0 KB

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  1. /** @file
  2. Provide FSP wrapper platform sec related function.
  3. Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <Ppi/SecPlatformInformation.h>
  8. #include <Ppi/SecPerformance.h>
  9. #include <Ppi/FirmwareVolumeInfo.h>
  10. #include <Ppi/TopOfTemporaryRam.h>
  11. #include <Ppi/PeiCoreFvLocation.h>
  12. #include <Guid/FirmwareFileSystem2.h>
  13. #include <Library/LocalApicLib.h>
  14. #include <Library/BaseMemoryLib.h>
  15. #include <Library/DebugLib.h>
  16. #include <Library/IoLib.h>
  17. /**
  18. This interface conveys state information out of the Security (SEC) phase into PEI.
  19. @param[in] PeiServices Pointer to the PEI Services Table.
  20. @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
  21. @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
  22. @retval EFI_SUCCESS The data was successfully returned.
  23. @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
  24. **/
  25. EFI_STATUS
  26. EFIAPI
  27. SecPlatformInformation (
  28. IN CONST EFI_PEI_SERVICES **PeiServices,
  29. IN OUT UINT64 *StructureSize,
  30. OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
  31. );
  32. /**
  33. This interface conveys performance information out of the Security (SEC) phase into PEI.
  34. This service is published by the SEC phase. The SEC phase handoff has an optional
  35. EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
  36. PEI Foundation. As such, if the platform supports collecting performance data in SEC,
  37. this information is encapsulated into the data structure abstracted by this service.
  38. This information is collected for the boot-strap processor (BSP) on IA-32.
  39. @param[in] PeiServices The pointer to the PEI Services Table.
  40. @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
  41. @param[out] Performance The pointer to performance data collected in SEC phase.
  42. @retval EFI_SUCCESS The data was successfully returned.
  43. **/
  44. EFI_STATUS
  45. EFIAPI
  46. SecGetPerformance (
  47. IN CONST EFI_PEI_SERVICES **PeiServices,
  48. IN PEI_SEC_PERFORMANCE_PPI *This,
  49. OUT FIRMWARE_SEC_PERFORMANCE *Performance
  50. );
  51. PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
  52. SecGetPerformance
  53. };
  54. EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
  55. (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
  56. };
  57. EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
  58. {
  59. EFI_PEI_PPI_DESCRIPTOR_PPI,
  60. &gEfiPeiCoreFvLocationPpiGuid,
  61. &mPeiCoreFvLocationPpi
  62. }
  63. };
  64. EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
  65. {
  66. EFI_PEI_PPI_DESCRIPTOR_PPI,
  67. &gTopOfTemporaryRamPpiGuid,
  68. NULL // To be patched later.
  69. },
  70. {
  71. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  72. &gPeiSecPerformancePpiGuid,
  73. &mSecPerformancePpi
  74. },
  75. };
  76. #define LEGACY_8259_MASK_REGISTER_MASTER 0x21
  77. #define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
  78. #define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
  79. #define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
  80. /**
  81. Write to mask and edge/level triggered registers of master and slave 8259 PICs.
  82. @param[in] Mask low byte for master PIC mask register,
  83. high byte for slave PIC mask register.
  84. @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
  85. high byte for slave PIC edge/level triggered register.
  86. **/
  87. VOID
  88. Interrupt8259WriteMask (
  89. IN UINT16 Mask,
  90. IN UINT16 EdgeLevel
  91. )
  92. {
  93. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
  94. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
  95. IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
  96. IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
  97. }
  98. /**
  99. A developer supplied function to perform platform specific operations.
  100. It's a developer supplied function to perform any operations appropriate to a
  101. given platform. It's invoked just before passing control to PEI core by SEC
  102. core. Platform developer may modify the SecCoreData passed to PEI Core.
  103. It returns a platform specific PPI list that platform wishes to pass to PEI core.
  104. The Generic SEC core module will merge this list to join the final list passed to
  105. PEI core.
  106. @param[in,out] SecCoreData The same parameter as passing to PEI core. It
  107. could be overridden by this function.
  108. @return The platform specific PPI list to be passed to PEI core or
  109. NULL if there is no need of such platform specific PPI list.
  110. **/
  111. EFI_PEI_PPI_DESCRIPTOR *
  112. EFIAPI
  113. SecPlatformMain (
  114. IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
  115. )
  116. {
  117. EFI_PEI_PPI_DESCRIPTOR *PpiList;
  118. UINT8 TopOfTemporaryRamPpiIndex;
  119. UINT8 *CopyDestinationPointer;
  120. DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
  121. DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
  122. DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
  123. DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
  124. DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
  125. DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
  126. DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
  127. DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
  128. InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
  129. //
  130. // Set all 8259 interrupts to edge triggered and disabled
  131. //
  132. Interrupt8259WriteMask (0xFFFF, 0x0000);
  133. //
  134. // Use middle of Heap as temp buffer, it will be copied by caller.
  135. // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
  136. //
  137. PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
  138. CopyDestinationPointer = (UINT8 *) PpiList;
  139. TopOfTemporaryRamPpiIndex = 0;
  140. if (PcdGet8 (PcdFspModeSelection) == 0) {
  141. //
  142. // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
  143. //
  144. CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
  145. TopOfTemporaryRamPpiIndex = 1;
  146. CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
  147. }
  148. CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
  149. //
  150. // Patch TopOfTemporaryRamPpi
  151. //
  152. PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
  153. return PpiList;
  154. }