PlatformEarlyInit.c 32 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformEarlyInit.c
  6. Abstract:
  7. Do platform specific PEI stage initializations.
  8. --*/
  9. #include "PlatformEarlyInit.h"
  10. static EFI_PEI_STALL_PPI mStallPpi = {
  11. PEI_STALL_RESOLUTION,
  12. Stall
  13. };
  14. static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
  15. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  16. &gEfiPeiStallPpiGuid,
  17. &mStallPpi
  18. };
  19. //
  20. // The reserved SMBus addresses are defined in PlatformDxe.h file.
  21. //
  22. static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  23. static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {
  24. SMBUS_BASE_ADDRESS,
  25. SMBUS_BUS_DEV_FUNC,
  26. PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
  27. mSmbusRsvdAddresses
  28. };
  29. static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {
  30. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  31. &gPeiSmbusPolicyPpiGuid,
  32. &mSmbusPolicyPpi
  33. };
  34. static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {
  35. ProgramToneFrequency,
  36. GenerateBeepTone
  37. };
  38. static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {
  39. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  40. &gPeiSpeakerInterfacePpiGuid,
  41. &mSpeakerInterfacePpi
  42. };
  43. static EFI_PEI_RESET_PPI mResetPpi = { IchReset };
  44. static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
  45. {
  46. EFI_PEI_PPI_DESCRIPTOR_PPI,
  47. &gEfiPeiMasterBootModePpiGuid,
  48. NULL
  49. },
  50. {
  51. (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  52. &gEfiPeiResetPpiGuid,
  53. &mResetPpi
  54. }
  55. };
  56. static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
  57. {
  58. EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
  59. &gEfiEndOfPeiSignalPpiGuid,
  60. (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
  61. },
  62. {
  63. (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  64. &gEfiPeiMemoryDiscoveredPpiGuid,
  65. (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
  66. }
  67. };
  68. /**
  69. Parse the status registers for figuring out the wake-up event and save it into
  70. an GUID HOB which will be referenced later. However, modification is required
  71. to meet the chipset register definition and the practical hardware design. Thus,
  72. this is just an example.
  73. @param PeiServices pointer to the PEI Service Table
  74. @param EFI_SUCCESS Always return Success
  75. @retval None
  76. **/
  77. EFI_STATUS
  78. EFIAPI
  79. GetWakeupEventAndSaveToHob (
  80. IN CONST EFI_PEI_SERVICES **PeiServices
  81. )
  82. {
  83. UINT16 Pm1Sts;
  84. UINTN Gpe0Sts;
  85. UINTN WakeEventData;
  86. //
  87. // Read the ACPI registers
  88. //
  89. Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
  90. Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
  91. //
  92. // Figure out the wake-up event
  93. //
  94. if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
  95. WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
  96. } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
  97. WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
  98. } else if (Gpe0Sts != 0) {
  99. WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
  100. } else {
  101. WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
  102. }
  103. DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
  104. DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));
  105. return EFI_SUCCESS;
  106. }
  107. EFI_STATUS
  108. GetSetupVariable (
  109. IN CONST EFI_PEI_SERVICES **PeiServices,
  110. IN SYSTEM_CONFIGURATION *SystemConfiguration
  111. )
  112. {
  113. UINTN VariableSize;
  114. EFI_STATUS Status;
  115. EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
  116. VariableSize = sizeof (SYSTEM_CONFIGURATION);
  117. ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
  118. Status = (*PeiServices)->LocatePpi (
  119. PeiServices,
  120. &gEfiPeiReadOnlyVariable2PpiGuid,
  121. 0,
  122. NULL,
  123. (void **)&Variable
  124. );
  125. ASSERT_EFI_ERROR (Status);
  126. //
  127. // Use normal setup default from NVRAM variable,
  128. // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
  129. //
  130. VariableSize = sizeof(SYSTEM_CONFIGURATION);
  131. Status = Variable->GetVariable (
  132. Variable,
  133. L"Setup",
  134. &gEfiSetupVariableGuid,
  135. NULL,
  136. &VariableSize,
  137. SystemConfiguration
  138. );
  139. if (EFI_ERROR (Status)) {
  140. return Status;
  141. }
  142. if (VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
  143. //
  144. // The setup variable is corrupted
  145. //
  146. return EFI_NOT_FOUND;
  147. }
  148. return EFI_SUCCESS;
  149. }
  150. EFI_STATUS
  151. VlvPolicyInit (
  152. IN CONST EFI_PEI_SERVICES **PeiServices,
  153. IN SYSTEM_CONFIGURATION *SystemConfiguration
  154. )
  155. {
  156. EFI_STATUS Status;
  157. EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;
  158. VLV_POLICY_PPI *mVlvPolicyPpi;
  159. Status = (*PeiServices)->AllocatePool(
  160. PeiServices,
  161. sizeof (EFI_PEI_PPI_DESCRIPTOR),
  162. (void **)&mVlvPolicyPpiDesc
  163. );
  164. ASSERT_EFI_ERROR (Status);
  165. Status = (*PeiServices)->AllocatePool(
  166. PeiServices,
  167. sizeof (VLV_POLICY_PPI),
  168. (void **)&mVlvPolicyPpi
  169. );
  170. ASSERT_EFI_ERROR (Status);
  171. //
  172. // Initialize PPI
  173. //
  174. (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);
  175. mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  176. mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
  177. mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
  178. mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;
  179. mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;
  180. mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;
  181. mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
  182. if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
  183. mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
  184. } else {
  185. mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
  186. }
  187. mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
  188. mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
  189. mVlvPolicyPpi->PlatformData.DynSR = 1;
  190. DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));
  191. mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;
  192. DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));
  193. mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;
  194. if (SystemConfiguration->ISPEn == 0) {
  195. mVlvPolicyPpi->ISPPciDevConfig = 0;
  196. DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));
  197. }
  198. Status = (*PeiServices)->InstallPpi(
  199. PeiServices,
  200. mVlvPolicyPpiDesc
  201. );
  202. ASSERT_EFI_ERROR (Status);
  203. return EFI_SUCCESS;
  204. }
  205. EFI_STATUS
  206. ConfigureSoCGpio (
  207. IN SYSTEM_CONFIGURATION *SystemConfiguration
  208. )
  209. {
  210. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
  211. if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
  212. DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
  213. //
  214. //Silicon Steppings
  215. //
  216. switch (PchStepping()) {
  217. case PchA0: // SOC A0 and A1
  218. case PchA1:
  219. DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
  220. SystemConfiguration->LpsseMMCEnabled = 1;
  221. SystemConfiguration->LpsseMMC45Enabled = 0;
  222. break;
  223. case PchB0: // SOC B0 and later
  224. default:
  225. DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
  226. SystemConfiguration->LpsseMMCEnabled = 0;
  227. SystemConfiguration->LpsseMMC45Enabled = 1;
  228. break;
  229. }
  230. } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
  231. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
  232. SystemConfiguration->LpsseMMCEnabled = 1;
  233. SystemConfiguration->LpsseMMC45Enabled = 0;
  234. } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
  235. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
  236. SystemConfiguration->LpsseMMCEnabled = 0;
  237. SystemConfiguration->LpsseMMC45Enabled = 1;
  238. } else { // Disable eMMC controllers
  239. DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
  240. SystemConfiguration->LpsseMMCEnabled = 0;
  241. SystemConfiguration->LpsseMMC45Enabled = 0;
  242. }
  243. /*
  244. 20.1.1 EMMC
  245. SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
  246. SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
  247. SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
  248. SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
  249. SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
  250. SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
  251. MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
  252. MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
  253. MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
  254. MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
  255. MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
  256. */
  257. if (SystemConfiguration->LpsseMMCEnabled== 1) {
  258. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
  259. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
  260. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
  261. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
  262. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
  263. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
  264. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
  265. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
  266. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
  267. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
  268. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
  269. }
  270. /*
  271. eMMC 4.5 controller
  272. SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
  273. SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
  274. SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
  275. SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
  276. SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
  277. SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
  278. MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
  279. MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
  280. MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
  281. MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
  282. MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
  283. */
  284. if (SystemConfiguration->LpsseMMC45Enabled== 1) {
  285. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
  286. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
  287. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
  288. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
  289. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
  290. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
  291. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
  292. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
  293. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
  294. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
  295. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
  296. }
  297. //
  298. // Change GPIOC_0 setting to allow MMIO access under Android.
  299. //
  300. IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
  301. (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
  302. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
  303. return EFI_SUCCESS;
  304. }
  305. EFI_STATUS
  306. MeasuredBootInit (
  307. IN CONST EFI_PEI_SERVICES **PeiServices,
  308. IN SYSTEM_CONFIGURATION *SystemConfiguration
  309. )
  310. {
  311. if (SystemConfiguration->MeasuredBootEnable) {
  312. PcdSetBool (PcdMeasuredBootEnable, TRUE);
  313. } else {
  314. PcdSetBool (PcdMeasuredBootEnable, FALSE);
  315. }
  316. return EFI_SUCCESS;
  317. }
  318. EFI_STATUS
  319. ConfigureLpssAndSccGpio (
  320. IN SYSTEM_CONFIGURATION *SystemConfiguration,
  321. IN EFI_PLATFORM_INFO_HOB *PlatformInfo
  322. )
  323. {
  324. /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
  325. GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
  326. GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
  327. GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
  328. */
  329. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
  330. /*
  331. 19.1.1 PWM0
  332. PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
  333. 19.1.2 PWM1
  334. PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
  335. */
  336. if (SystemConfiguration->LpssPwm0Enabled== 1) {
  337. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
  338. } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
  339. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
  340. }
  341. if (SystemConfiguration->LpssPwm1Enabled== 1) {
  342. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
  343. } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
  344. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
  345. }
  346. /*
  347. 19.1.3 UART1
  348. UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
  349. UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
  350. UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
  351. UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
  352. */
  353. if (SystemConfiguration->LpssHsuart0Enabled== 1) {
  354. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
  355. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
  356. if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
  357. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
  358. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
  359. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
  360. } else {
  361. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
  362. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
  363. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
  364. }
  365. } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
  366. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
  367. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
  368. }
  369. /*
  370. 19.1.4 UART2
  371. UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
  372. UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
  373. UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
  374. UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
  375. */
  376. if (SystemConfiguration->LpssHsuart1Enabled== 1) {
  377. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
  378. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
  379. if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
  380. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
  381. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B
  382. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B
  383. } else {
  384. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
  385. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
  386. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
  387. }
  388. } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
  389. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
  390. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
  391. }
  392. /*
  393. 19.1.5 SPI
  394. SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
  395. SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
  396. SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
  397. SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
  398. */
  399. if (SystemConfiguration->LpssSpiEnabled== 1) {
  400. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
  401. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
  402. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
  403. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
  404. } else if (SystemConfiguration->LpssSpiEnabled== 0) {
  405. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
  406. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
  407. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
  408. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
  409. }
  410. /*
  411. 19.1.6 I2C0
  412. I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
  413. I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
  414. */
  415. if (SystemConfiguration->LpssI2C0Enabled== 1) {
  416. MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
  417. MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
  418. }
  419. /*
  420. 19.1.7 I2C1
  421. I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
  422. I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
  423. */
  424. if (SystemConfiguration->LpssI2C1Enabled== 1) {
  425. MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
  426. MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
  427. }
  428. /*
  429. 19.1.8 I2C2
  430. I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
  431. I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
  432. */
  433. if (SystemConfiguration->LpssI2C2Enabled== 1) {
  434. MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
  435. MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
  436. }
  437. /*
  438. 19.1.9 I2C3
  439. I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
  440. I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
  441. */
  442. if (SystemConfiguration->LpssI2C3Enabled== 1) {
  443. MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
  444. MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
  445. }
  446. /*
  447. 19.1.10 I2C4
  448. I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
  449. I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
  450. */
  451. if (SystemConfiguration->LpssI2C4Enabled== 1) {
  452. MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
  453. MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
  454. }
  455. /*
  456. 19.1.11 I2C5
  457. I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
  458. I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
  459. */
  460. //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
  461. if (SystemConfiguration->LpssI2C5Enabled== 1) {
  462. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
  463. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
  464. } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
  465. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
  466. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
  467. }
  468. /*
  469. 19.1.12 I2C6
  470. I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
  471. I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
  472. */
  473. if (SystemConfiguration->LpssI2C6Enabled== 1) {
  474. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
  475. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
  476. } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
  477. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
  478. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
  479. }
  480. /*
  481. 20.1.2 SDIO
  482. SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
  483. SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
  484. SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
  485. SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
  486. SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
  487. SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
  488. */
  489. if (SystemConfiguration->LpssSdioEnabled== 1) {
  490. MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
  491. MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
  492. MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
  493. MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
  494. MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
  495. MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
  496. }
  497. /*
  498. 20.1.3 SD Card
  499. SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
  500. SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
  501. SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
  502. SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
  503. SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
  504. SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
  505. SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
  506. SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
  507. SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
  508. SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
  509. */
  510. if (SystemConfiguration->LpssSdcardEnabled == 1) {
  511. if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
  512. MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
  513. MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
  514. MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
  515. MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
  516. MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
  517. MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
  518. MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
  519. MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
  520. MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
  521. }
  522. }
  523. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
  524. return EFI_SUCCESS;
  525. }
  526. EFI_STATUS
  527. ConfigureLpeGpio (
  528. IN SYSTEM_CONFIGURATION *SystemConfiguration
  529. )
  530. {
  531. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
  532. if (SystemConfiguration->PchAzalia == 0) {
  533. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
  534. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
  535. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
  536. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
  537. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
  538. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
  539. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
  540. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
  541. }
  542. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
  543. return EFI_SUCCESS;
  544. }
  545. EFI_STATUS
  546. ConfigureSciSmiGpioRout (
  547. IN EFI_PLATFORM_INFO_HOB *PlatformInfo)
  548. {
  549. UINT32 GPI_Routing;
  550. GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
  551. //
  552. // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  553. //
  554. if(PlatformInfo->BoardRev == 3) {
  555. GPI_Routing = GPI_Routing & 0xfffc3ffc;
  556. GPI_Routing = GPI_Routing | 0x00024002;
  557. }
  558. //
  559. // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  560. //
  561. else {
  562. GPI_Routing = GPI_Routing & 0x3fff3ffc;
  563. GPI_Routing = GPI_Routing | 0x80004002;
  564. }
  565. MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
  566. return EFI_SUCCESS;
  567. }
  568. EFI_STATUS
  569. ConfigureMipiCsi (
  570. VOID)
  571. {
  572. //
  573. //Configure the platform clock for MIPI-CSI usage
  574. //PLT_CLK0
  575. //
  576. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
  577. //
  578. //PLT_CLK1
  579. //
  580. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));
  581. //
  582. //PLT_CLK2
  583. //
  584. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));
  585. return EFI_SUCCESS;
  586. }
  587. EFI_STATUS
  588. ConfigureUSBULPI (
  589. VOID)
  590. {
  591. //
  592. //Configure USB ULPI
  593. //USB_ULPI_0_CLK
  594. //
  595. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));
  596. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));
  597. //
  598. //USB_ULPI_0_DATA0
  599. //
  600. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));
  601. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));
  602. //
  603. //USB_ULPI_0_DATA1
  604. //
  605. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));
  606. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));
  607. //
  608. //USB_ULPI_0_DATA2
  609. //
  610. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));
  611. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));
  612. //
  613. //USB_ULPI_0_DATA3
  614. //
  615. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));
  616. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));
  617. //
  618. //USB_ULPI_0_DATA4
  619. //
  620. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));
  621. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));
  622. //
  623. //USB_ULPI_0_DATA5
  624. //
  625. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));
  626. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));
  627. //
  628. //USB_ULPI_0_DATA6
  629. //
  630. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));
  631. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));
  632. //
  633. //USB_ULPI_0_DATA7
  634. //
  635. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));
  636. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));
  637. //
  638. //USB_ULPI_0_DIR
  639. //
  640. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));
  641. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));
  642. //
  643. //USB_ULPI_0_NXT
  644. //
  645. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));
  646. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));
  647. //
  648. //USB_ULPI_0_STP
  649. //
  650. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));
  651. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));
  652. //
  653. //USB_ULPI_0_REFCLK
  654. //
  655. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));
  656. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));
  657. return EFI_SUCCESS;
  658. }
  659. EFI_STATUS
  660. DisableRTD3 (
  661. VOID)
  662. {
  663. //
  664. //Disable RTD3
  665. //
  666. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));
  667. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));
  668. return EFI_SUCCESS;
  669. }
  670. /**
  671. Platform specific initializations in stage1.
  672. @param FfsHeader Pointer to the PEIM FFS file header.
  673. @param PeiServices General purpose services available to every PEIM.
  674. @retval EFI_SUCCESS Operation completed successfully.
  675. @retval Otherwise Platform initialization failed.
  676. **/
  677. EFI_STATUS
  678. EFIAPI
  679. PlatformEarlyInitEntry (
  680. IN EFI_PEI_FILE_HANDLE FileHandle,
  681. IN CONST EFI_PEI_SERVICES **PeiServices
  682. )
  683. {
  684. EFI_STATUS Status;
  685. SYSTEM_CONFIGURATION SystemConfiguration;
  686. EFI_PLATFORM_INFO_HOB *PlatformInfo;
  687. EFI_PEI_HOB_POINTERS Hob;
  688. EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
  689. //
  690. // Initialize SmbusPolicy PPI
  691. //
  692. Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
  693. ASSERT_EFI_ERROR (Status);
  694. //
  695. // Initialize Stall PPIs
  696. //
  697. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
  698. ASSERT_EFI_ERROR (Status);
  699. //
  700. // Initialize platform PPIs
  701. //
  702. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);
  703. ASSERT_EFI_ERROR (Status);
  704. //
  705. // Variable initialization
  706. //
  707. ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
  708. //
  709. // Set the some PCI and chipset range as UC
  710. // And align to 1M at leaset
  711. //
  712. Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  713. ASSERT (Hob.Raw != NULL);
  714. PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
  715. //
  716. // Initialize PlatformInfo HOB
  717. //
  718. MultiPlatformInfoInit(PeiServices, PlatformInfo);
  719. //
  720. // Do basic MCH init
  721. //
  722. MchInit (PeiServices);
  723. //
  724. // Set the new boot mode
  725. //
  726. Status = UpdateBootMode (PeiServices, PlatformInfo);
  727. ASSERT_EFI_ERROR (Status);
  728. SetPlatformBootMode (PeiServices, PlatformInfo);
  729. //
  730. // Get setup variable. This can only be done after BootMode is updated
  731. //
  732. Status = GetSetupVariable (PeiServices, &SystemConfiguration);
  733. if (EFI_ERROR (Status)) {
  734. DEBUG ((DEBUG_INFO, "PlatformEarlyInitEntry: Setup Variable does not exist.\n"));
  735. DEBUG ((DEBUG_INFO, "PlatformEarlyInitEntry: Set PcdNvStoreDefaultId to STANDARD\n"));
  736. //
  737. // Set the default NV store to STANDARD defaults
  738. //
  739. PcdSet16S (PcdSetNvStoreDefaultId, 0x0000);
  740. //
  741. // Get setup variable. Must succeed at this point.
  742. //
  743. Status = GetSetupVariable (PeiServices, &SystemConfiguration);
  744. ASSERT_EFI_ERROR (Status);
  745. }
  746. CheckOsSelection(PeiServices, &SystemConfiguration);
  747. //
  748. // Update PlatformInfo HOB according to setup variable
  749. //
  750. PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
  751. InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
  752. //
  753. // Initialize VlvPolicy PPI
  754. //
  755. Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
  756. ASSERT_EFI_ERROR (Status);
  757. //
  758. // Soc specific GPIO setting
  759. //
  760. ConfigureSoCGpio(&SystemConfiguration);
  761. //
  762. // Baylake Board specific.
  763. //
  764. if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||
  765. PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
  766. PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
  767. PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
  768. PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
  769. PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
  770. PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
  771. PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
  772. PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
  773. PlatformInfo->BoardId == BOARD_ID_CVH) {
  774. ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
  775. }
  776. //
  777. // Configure LPE
  778. // Alpine Valley and Bayley Bay board specific
  779. //
  780. ConfigureLpeGpio(&SystemConfiguration);
  781. //
  782. // Bayley Bay Board specific.
  783. //
  784. ConfigureSciSmiGpioRout(PlatformInfo);
  785. if (SystemConfiguration.LpssI2C3Enabled == 1) {
  786. ConfigureMipiCsi();
  787. }
  788. //
  789. // Do basic CPU init
  790. //
  791. Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);
  792. //
  793. // Perform basic SSA related platform initialization
  794. //
  795. PlatformSsaInit (&SystemConfiguration,PeiServices);
  796. //
  797. // Do basic PCH init
  798. //
  799. Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
  800. ASSERT_EFI_ERROR (Status);
  801. //
  802. // Initialize platform PPIs
  803. //
  804. Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
  805. ASSERT_EFI_ERROR (Status);
  806. if (PlatformInfo->BoardId != BOARD_ID_CVH) {
  807. InstallPlatformClocksNotify (PeiServices);
  808. InstallPlatformSysCtrlGPIONotify(PeiServices);
  809. }
  810. //
  811. // Initialize platform PPIs
  812. //
  813. Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
  814. ASSERT_EFI_ERROR (Status);
  815. //
  816. // Initialize Measured Boot
  817. //
  818. Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
  819. ASSERT_EFI_ERROR (Status);
  820. return Status;
  821. }