Cpu.S 2.7 KB

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  1. //------------------------------------------------------------------------------
  2. //
  3. // RISC-V CPU functions.
  4. //
  5. // Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  6. //
  7. // SPDX-License-Identifier: BSD-2-Clause-Patent
  8. //
  9. //------------------------------------------------------------------------------
  10. #include <Base.h>
  11. #include <RiscVImpl.h>
  12. .data
  13. .text
  14. .align 3
  15. //
  16. // Set machine mode scratch.
  17. // @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
  18. //
  19. ASM_FUNC (RiscVSetMachineScratch)
  20. csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
  21. ret
  22. //
  23. // Get machine mode scratch.
  24. // @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
  25. //
  26. ASM_FUNC (RiscVGetMachineScratch)
  27. csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
  28. ret
  29. //
  30. // Get machine trap cause CSR.
  31. //
  32. ASM_FUNC (RiscVGetMachineTrapCause)
  33. csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
  34. ret
  35. //
  36. // Get machine interrupt enable
  37. //
  38. ASM_FUNC (RiscVReadMachineInterruptEnable)
  39. csrr a0, RISCV_CSR_MACHINE_MIE
  40. ret
  41. //
  42. // Get machine interrupt pending
  43. //
  44. ASM_FUNC (RiscVReadMachineInterruptPending)
  45. csrr a0, RISCV_CSR_MACHINE_MIP
  46. ret
  47. //
  48. // Get machine status
  49. //
  50. ASM_FUNC (RiscVReadMachineStatus)
  51. csrr a0, RISCV_CSR_MACHINE_MSTATUS
  52. ret
  53. //
  54. // Set machine status
  55. //
  56. ASM_FUNC (RiscVWriteMachineStatus)
  57. csrw RISCV_CSR_MACHINE_MSTATUS, a0
  58. ret
  59. //
  60. // Get machine trap vector
  61. //
  62. ASM_FUNC (RiscVReadMachineTrapVector)
  63. csrr a0, RISCV_CSR_MACHINE_MTVEC
  64. ret
  65. //
  66. // Read machine ISA
  67. //
  68. ASM_FUNC (RiscVReadMachineIsa)
  69. csrr a0, RISCV_CSR_MACHINE_MISA
  70. ret
  71. //
  72. // Read machine vendor ID
  73. //
  74. ASM_FUNC (RiscVReadMachineVendorId)
  75. csrr a0, RISCV_CSR_MACHINE_MVENDORID
  76. ret
  77. //
  78. // Read machine architecture ID
  79. //
  80. ASM_FUNC (RiscVReadMachineArchitectureId)
  81. csrr a0, RISCV_CSR_MACHINE_MARCHID
  82. ret
  83. //
  84. // Read machine implementation ID
  85. //
  86. ASM_FUNC (RiscVReadMachineImplementId)
  87. csrr a0, RISCV_CSR_MACHINE_MIMPID
  88. ret
  89. //
  90. // Set Supervisor mode scratch.
  91. // @param a0 : Value set to Supervisor mode scratch
  92. //
  93. ASM_FUNC (RiscVSetSupervisorScratch)
  94. csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
  95. ret
  96. //
  97. // Get Supervisor mode scratch.
  98. // @retval a0 : Value in Supervisor mode scratch
  99. //
  100. ASM_FUNC (RiscVGetSupervisorScratch)
  101. csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
  102. ret
  103. //
  104. // Set Supervisor mode trap vector.
  105. // @param a0 : Value set to Supervisor mode trap vector
  106. //
  107. ASM_FUNC (RiscVSetSupervisorStvec)
  108. csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
  109. ret
  110. //
  111. // Get Supervisor mode scratch.
  112. // @retval a0 : Value in Supervisor mode trap vector
  113. //
  114. ASM_FUNC (RiscVGetSupervisorStvec)
  115. csrr a0, RISCV_CSR_SUPERVISOR_STVEC
  116. ret